JP2913500B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2913500B2 JP2913500B2 JP5342886A JP34288693A JP2913500B2 JP 2913500 B2 JP2913500 B2 JP 2913500B2 JP 5342886 A JP5342886 A JP 5342886A JP 34288693 A JP34288693 A JP 34288693A JP 2913500 B2 JP2913500 B2 JP 2913500B2
- Authority
- JP
- Japan
- Prior art keywords
- main surface
- insulating member
- external
- conductor film
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Description
【０００１】[0001]
【産業上の利用分野】本発明は電界効果トランジスタ等
の半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a field effect transistor.
【０００２】[0002]
【従来の技術】図５に示すように、金属放熱板１の上に
電界効果トランジスタチップ２を固着すると共に、セラ
ミック製の絶縁体枠３を固着し、この絶縁体枠３に金属
片から成る外部リード４を固着し、チップ２と外部リー
ド４とを内部リード線５で接続し、チップ２を保護樹脂
（図示せず）で被覆して電界効果トランジスタを構成す
ることが知られている。なお、図５には図示はされてい
ないが、セラミック絶縁体枠３の上面に金属膜を設け、
ここに外部リード４を固着することがある。2. Description of the Related Art As shown in FIG. 5, a field effect transistor chip 2 is fixed on a metal heat radiating plate 1 and a ceramic insulator frame 3 is fixed, and the insulator frame 3 is made of a metal piece. It is known that an external lead 4 is fixed, the chip 2 and the external lead 4 are connected by an internal lead wire 5, and the chip 2 is covered with a protective resin (not shown) to form a field effect transistor. Although not shown in FIG. 5, a metal film is provided on the upper surface of the ceramic insulator frame 3.
The external lead 4 may be fixed here.
【０００３】[0003]
【発明が解決しようとする課題】ところで、図５では絶
縁体枠３がセラミックであるので高価になるばかりでな
く、金属片から成る外部リード４を絶縁体枠３に固着す
るので、組立作業が煩雑になり、必然的に半導体装置が
コスト高になった。In FIG. 5, since the insulator frame 3 is made of ceramic, it is not only expensive, but also the external lead 4 made of a metal piece is fixed to the insulator frame 3, so that the assembling work is not required. It became complicated, and the cost of the semiconductor device was inevitably increased.
【０００４】そこで、本発明の目的はコストの低減を図
ることができる半導体装置を提供することにある。Accordingly, an object of the present invention is to provide a semiconductor device capable of reducing costs.
【０００５】[0005]
【課題を解決するための手段】上記目的を達成するため
の本発明は、半導体素子と放熱体と外部接続体と内部接
続体とから成り、前記半導体素子は前記放熱体の一方の
主面に固着され、前記外部接続体は絶縁部材とこの表面
に形成された導体膜とから成り、前記絶縁部材は前記放
熱体の一方の主面に直接又は導体膜を介して固着された
第１の部分と前記放熱体の一方の主面の延長方向に前記
放熱体の一方の主面から張り出した第２の部分とを有
し、前記絶縁部材の前記第１の部分の主面の少なくとも
一部及び前記第２の部分の主面の少なくとも一部に導体
膜が設けられ、前記第１の部分の導体膜と前記第２の部
分の導体膜とは互いに接続され、前記半導体素子と前記
第１の部分の前記導体膜とが前記内部接続体によって電
気的に接続され、前記絶縁部材の前記第２の部分が可撓
性を有している半導体装置に係わるものである。なお、
請求項２に示すように、絶縁部材に環状部分と外部リー
ド用部分とを設け、環状部分によって半導体素子を囲む
ことが望ましい。また、請求項３に示すように外部リー
ド用部分を帯状に形成することが望ましい。また、請求
項４に示すように保護樹脂を設けることが望ましい。SUMMARY OF THE INVENTION In order to achieve the above object, the present invention comprises a semiconductor element, a radiator, an external connector, and an internal connector, wherein the semiconductor element is provided on one main surface of the radiator. A first portion fixed to the external connection body, the first portion fixed to one main surface of the radiator directly or via the conductor film; And a second portion protruding from one main surface of the heat radiator in an extension direction of one main surface of the heat radiator, and at least a part of a main surface of the first portion of the insulating member and A conductor film is provided on at least a part of a main surface of the second portion, the conductor film of the first portion and the conductor film of the second portion are connected to each other, and the semiconductor element and the first A part of the conductor film is electrically connected to the internal connection body, Those related to the semiconductor device in which the second portion of the insulating member is flexible. In addition,
As described in claim 2, the insulating member has an annular portion and an external lead.
And a semiconductor device surrounded by an annular portion.
It is desirable. Further, it is desirable to form a partial external Lee <br/> de in a strip as shown in claim 3. Further, it is desirable to provide a protective resin as described in claim 4.
【０００６】[0006]
【発明の作用及び効果】各請求項の発明によれば、外部
リードを金属片によって独立に形成しないで絶縁部材に
導体膜を形成することによって得るので、組立作業が容
易になり、コストの低減を図ることができる。また、請
求項２の発明によれば、絶縁部材の環状部分によって半
導体素子を取り囲むので、環状部分が半導体素子の容器
として機能し、半導体素子が保護される。また、請求項
１及び３の発明によれば、絶縁部材の第２の部分又は外
部リード用部分が可撓性を有するので、外部回路装置に
対する接続を容易に達成することができる。また、請求
項４の発明によれば半導体素子の保護を良好に達成する
ことができる。According to the present invention, since the external leads are obtained by forming the conductor film on the insulating member without being formed independently of the metal pieces, the assembling work is facilitated and the cost is reduced. Can be achieved. In addition,
According to the invention as set forth in claim 2, the annular portion of the insulating member forms a half.
An annular part surrounds the conductor element, so the annular part
And the semiconductor element is protected. According to the first and third aspects of the present invention, the second portion or the outer portion of the insulating member is provided.
Parts since the read unit content is flexible, can be easily achieved connection to external circuit devices. Further, according to the invention of claim 4, protection of the semiconductor element can be favorably achieved.
【０００７】[0007]
【実施例】次に、図１〜図４を参照して本発明の実施例
に係わる電界効果トランジスタについて説明する。図１
の電界効果トランジスタ１０は、銅片にニッケルと金の
メッキを順次施した厚さ約０．６ｍｍの放熱体即ち放熱
板１１と、ポリイミド樹脂板から成り可撓性を有する厚
さ約０．１ｍｍの絶縁部材１２と、半導体素子としての
電界効果トランジスタチップ１３とを有する。Next, a field effect transistor according to an embodiment of the present invention will be described with reference to FIGS. FIG.
The field effect transistor 10 is composed of a radiator or heat radiator 11 having a thickness of about 0.6 mm in which copper pieces are sequentially plated with nickel and gold and a polyimide resin plate having a thickness of about 0.1 mm having flexibility. And an electric field effect transistor chip 13 as a semiconductor element.
【０００８】放熱板１１は一方の主面に突起状の台座部
１１ａを有しており、電界効果トランジスタチップ１３
はこの台座部１１ａに半田１４によって固着されてい
る。なお、台座部１１ａの一方の側に形成された突起部
１１ｂはチップ１３の位置決め部として機能する。本実
施例の放熱板１１の平面形状は略正方形となっている
が、円形等にしてもよい。The radiating plate 11 has a projecting pedestal portion 11a on one main surface, and the
Is fixed to the pedestal portion 11a by solder. The protrusion 11b formed on one side of the pedestal 11a functions as a positioning portion for the chip 13. The planar shape of the heat radiating plate 11 of this embodiment is substantially square, but may be circular.
【０００９】絶縁部材１２は多数装置分の絶縁部材を製
作できる大面積のポリイミド樹脂板を打ち抜き加工して
形成されたものであり、図２及び３に示すように環状
（枠状）の第１の部分１２ａとこの第１の部分１２ａの
両側に帯状に張り出した第２及び第３の部分１２ｂ、１
２ｃとを備えている。外部リードとして機能する第２及
び第３の部分１２ｂ、１２ｃは略四角形の第１の部分１
２ａよりも幅狭の帯状部分であるが、第１の部分１２ａ
との境界領域の強度を高めるために境界領域が先端より
も幅広に形成されている。The insulating member 12 is formed by stamping out a large-area polyimide resin plate capable of manufacturing insulating members for a number of devices. As shown in FIGS. 2 and 3, an annular (frame-shaped) first member is formed. Portion 12a, and second and third portions 12b, 1b, which protrude in a band shape on both sides of the first portion 12a.
2c. The second and third portions 12b and 12c functioning as external leads are substantially rectangular first portions 1
Although it is a band-like portion narrower than 2a, the first portion 12a
The boundary region is formed wider than the front end in order to increase the strength of the boundary region.
【００１０】本体部又はチップ収容部又は素子保護部又
は環状部分と呼ぶことができる第１の部分１２ａはこの
一方の主面（上面）から他方の主面（下面）に貫通して
いる四角形のチップ収容孔１８を有する。第１の部分１
２ａの上面には一対のソース接続用導体膜１５ａ、１５
ｂが配設され、また下面にもソース接続用導体膜１５ｃ
が配設され、これ等が第１の部分１２ａの一対の側面に
それぞれ形成された半円状溝１２ｄにおける導体膜によ
って接続されている。The first portion 12a, which can be referred to as a main body portion, a chip housing portion, an element protection portion, or an annular portion, has a rectangular shape penetrating from one main surface (upper surface) to the other main surface (lower surface). It has a chip accommodation hole 18. First part 1
A pair of source connection conductor films 15a, 15
b, and the source connecting conductor film 15c is also provided on the lower surface.
Are connected by a conductor film in a semicircular groove 12d formed on each of a pair of side surfaces of the first portion 12a.
【００１１】第１の部分１２ａから帯状に延びている第
２及び第３の部分１２ｂ、１２ｃは少なくともこの主面
に対して垂直な方向に可撓性を有し、弾性変形可能であ
る。この弾性変形量は第２及び第３の部分１２ｂ、１２
ｃの先端部がこの第２及び第３の部分１２ｂ、１２ｃの
長さの２％以上（好ましくは５％以上）垂直方向に変位
できる量であることが望ましい。各図において第１の部
分１２ａの左側と第２の部分１２ｂの上面にドレイン接
続用導体膜１６ａが帯状に配設され、左側の第２の部分
１２ｂの下面にも図１及び図３に示すようにドレイン接
続用導体膜１６ｂが配設され、これ等が第２の部分１２
ｂの先端の側面の溝１２ｅの導体膜１６ｃによって相互
に接続されている。同様に第１の部分１２ａの右側と第
３の部分１２ｃの上面にゲート接続用導体膜１７ａが帯
状に配設され、右側の第３の部分１２ｃの下面にもゲー
ト接続用導体膜１７ｂが配設され、これ等が第３の部分
１２ｃの先端の側面の溝１２ｆの導体膜１７ｃによって
相互に接続されている。各導体膜１５ａ、１５ｂ、１５
ｃ、１６ａ、１６ｂ、１６ｃ、１７ａ、１７ｂ、１７ｃ
は絶縁部材１２上の銅箔を所定パターンにエッチングす
ることによって形成された下地層の上に銅メッキ層とニ
ッケルメッキ層と金メッキ層とを順次に形成したもので
ある。なお、この各導体層を銅箔を使用しないで金属メ
ッキ層又は金属蒸着層で形成することもできる。また、
溝１２ｄ、１２ｅ、１２ｆの導体膜を絶縁部材１２の上
面及び下面の導体膜と別に形成してもよい。The second and third portions 12b and 12c extending in a strip shape from the first portion 12a have flexibility in at least a direction perpendicular to the main surface and are elastically deformable. This amount of elastic deformation depends on the second and third portions 12b, 12b.
It is desirable that the tip of c be displaced in the vertical direction by 2% or more (preferably 5% or more) of the length of the second and third portions 12b and 12c. In each figure, the drain connection conductor film 16a is disposed in a strip shape on the left side of the first portion 12a and on the upper surface of the second portion 12b, and the lower surface of the left second portion 12b is also shown in FIGS. The conductor film 16b for drain connection is disposed as described above,
b are connected to each other by the conductor film 16c of the groove 12e on the side surface at the tip of b. Similarly, a gate connecting conductor film 17a is disposed in a band shape on the right side of the first portion 12a and on the upper surface of the third portion 12c, and a gate connecting conductor film 17b is disposed on the lower surface of the right third portion 12c. These are connected to each other by the conductor film 17c of the groove 12f on the side surface of the tip of the third portion 12c. Each conductor film 15a, 15b, 15
c, 16a, 16b, 16c, 17a, 17b, 17c
In the figure, a copper plating layer, a nickel plating layer, and a gold plating layer are sequentially formed on a base layer formed by etching a copper foil on the insulating member 12 into a predetermined pattern. In addition, each of the conductor layers may be formed of a metal plating layer or a metal deposition layer without using a copper foil. Also,
The conductor films of the grooves 12d, 12e, and 12f may be formed separately from the conductor films on the upper and lower surfaces of the insulating member 12.
【００１２】合成樹脂から成る絶縁部材１２に導体膜１
５ａ、１５ｂ、１５ｃ、１６ａ、１６ｂ、１６ｃ、１７
ａ、１７ｂ、１７ｃを設けることによって構成された素
子保護及び外部接続体１９は放熱体としての放熱板１１
の上面に固着されている。即ち、絶縁部材１２の孔１８
の中にチップ１３が収容されるように素子保護及び外部
接続体１９が配置され、第１の部分１２ａの下面のソー
ス接続用導体膜１５ｃが半田２０によって、金属放熱板
１１に固着されている。電界効果トランジスタチップ１
３は周知のように上面にドレイン電極、ゲート電極及び
ソース電極を有し、ドレイン電極は内部接続体としての
リード細線２１によって上面のドレイン接続用導体膜１
６ａに接続され、ゲート電極はリード細線２２によって
上面のゲート接続用導体膜１７ａに接続され、ソース電
極は２本のリード細線２３、２４によって上面のソース
接続用導体膜１５ａ、１５ｂに接続されている。A conductor film 1 is provided on an insulating member 12 made of synthetic resin.
5a, 15b, 15c, 16a, 16b, 16c, 17
a, 17b, and 17c are provided to protect the element and the external connector 19 from the heat radiating plate 11 as a heat radiator.
Is fixed to the upper surface of. That is, the hole 18 of the insulating member 12
The element protection and external connection body 19 is arranged so that the chip 13 is accommodated therein, and the source connection conductor film 15 c on the lower surface of the first portion 12 a is fixed to the metal heat dissipation plate 11 by solder 20. . Field effect transistor chip 1
3 has a drain electrode, a gate electrode, and a source electrode on the upper surface as is well known, and the drain electrode is formed by a thin lead wire 21 as an internal connection body.
6a, the gate electrode is connected to the upper gate connecting conductor film 17a by a fine lead wire 22, and the source electrode is connected to the upper source connecting conductor films 15a, 15b by two thin lead wires 23, 24. I have.
【００１３】保護樹脂２５は図１に示すようにチップ１
３を被覆するようにチップ収容孔１８に充填され且つリ
ード細線２１〜２４を被覆するように第１の部分１２ａ
の上に配設されている。この保護樹脂２５は周知のポッ
ティング法又はトランスファモールド法で形成される。As shown in FIG. 1, the protective resin 25 is
3 is filled in the chip receiving hole 18 and the first portion 12a is
It is arranged above. This protective resin 25 is formed by a well-known potting method or a transfer molding method.
【００１４】電界効果トランジスタ１０は例えば図４に
示すように使用される。即ち、外部放熱体２６に開口２
７を有する回路基板２８が半田２９で固着されたものを
用意し、回路基板２８の開口２７に電界効果トランジス
タ１０の放熱板１１を挿入し、この底面を半田によって
外部放熱体２６に固着する。また絶縁部材１２のリード
として機能する第２の部分１２ｂのドレイン接続用導体
膜１６ｂ、１６ｃを回路基板２８の上面の第１の配線導
体３１に半田３２で固着し、同様に第３の部分１２ｃの
ゲート接続用導体膜１７ｂ、１７ｃを回路基板２８の上
面の第２の配線導体３３に半田３４で固着する。この
時、リードとして機能する第２及び第３の部分１２ｂ、
１２ｃは可撓性を有するので、従来の金属リードと同様
に回路基板２８の配線導体３１、３３との高さの差を吸
収するように弾性変形して良好に半田接続される。ま
た、半田３２、３４が第２及び第３の部分１２ｂ、１２
ｃの先端の溝１２ｅ、１２ｆに挿入されて強固な結合が
達成される。The field effect transistor 10 is used, for example, as shown in FIG. That is, the opening 2 is formed in the external radiator 26.
A circuit board 28 having a circuit board 7 is fixed by solder 29, a heat sink 11 of the field effect transistor 10 is inserted into an opening 27 of the circuit board 28, and the bottom surface is fixed to an external heat sink 26 by solder. Further, the drain connection conductor films 16b and 16c of the second portion 12b functioning as leads of the insulating member 12 are fixed to the first wiring conductor 31 on the upper surface of the circuit board 28 with solder 32, and similarly, the third portion 12c The gate connecting conductor films 17b and 17c are fixed to the second wiring conductor 33 on the upper surface of the circuit board 28 with solder 34. At this time, the second and third portions 12b functioning as leads are provided.
Since 12c has flexibility, it is elastically deformed so as to absorb the difference in height between the wiring conductors 31 and 33 of the circuit board 28, as in the case of the conventional metal lead, and is favorably soldered. In addition, the solders 32 and 34 are used as the second and third portions 12b and 12b.
c is inserted into the grooves 12e and 12f at the tip of c to achieve a strong connection.
【００１５】また、本実施例ではポリイミド樹脂板の打
ち抜き加工で絶縁部材１２を量産することができ、且つ
独立した金属リード片が不要になるので、図５に示す従
来のセラミック製の絶縁体枠３と外部リード４を使用す
るものに比べて大幅なコストの低減が可能になる。Further, in the present embodiment, the insulating member 12 can be mass-produced by punching a polyimide resin plate, and independent metal lead pieces are not required. Therefore, the conventional ceramic insulator frame shown in FIG. The cost can be significantly reduced as compared with the case where the external lead 3 and the external lead 4 are used.
【００１６】[0016]
【変形例】本発明は上述の実施例に限定されるものでな
く、例えば次の変形が可能なものである。 （１） 溝１２ｄ、１２ｅ、１２ｆの代りに貫通孔を設
け、ここに導体を充填して上下の導体層を接続すること
ができる。 （２） 第２及び第３の部分１２ｂ、１２ｃの可撓性を
この長さの増大を伴わないで得るために、図６に示すよ
うに第１の部分１２ａと第２及び第３の部分１２ｂ、１
２ｃとの境界領域のみを幅狭にし、これ等の先端を幅広
にし、幅広の先端部で電気的接続を確実に達成してもよ
い。 （３） 図７に示すように、第１の部分１２ａを第２及
び第３の部分１２ｂ、１２ｃよりも厚く形成し、第２及
び第３の部分１２ｂ、１２ｃの可撓性を高めてもよい。 （４） 電界効果トランジスタ以外のバイポ−ラトラン
ジスタ、ダイオ−ド等の半導体素子にも適用可能であ
る。また、１６ａをゲ−ト接続用導体膜、１７ａをドレ
イン接続用導体膜とすることができる。[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible. (1) A through hole may be provided instead of the grooves 12d, 12e, and 12f, and a conductor may be filled in the through hole to connect the upper and lower conductor layers. (2) In order to obtain the flexibility of the second and third portions 12b and 12c without increasing the length, as shown in FIG. 6, the first portion 12a and the second and third portions are provided. 12b, 1
Only the boundary region with 2c may be narrowed, and the leading ends thereof may be widened, so that the wide leading end portion reliably achieves electrical connection. (3) As shown in FIG. 7, even if the first portion 12a is formed thicker than the second and third portions 12b, 12c, the flexibility of the second and third portions 12b, 12c is increased. Good. (4) The present invention can be applied to semiconductor elements such as bipolar transistors and diodes other than field effect transistors. Also, 16a can be a gate connection conductor film and 17a can be a drain connection conductor film.
【図１】本発明の実施例の電界効果トランジスタを図２
のＡ−Ａ線を拡大して示す断面図である。FIG. 1 shows a field effect transistor according to an embodiment of the present invention in FIG.
FIG. 2 is an enlarged cross-sectional view taken along line AA of FIG.
【図２】図１の電界効果トランジスタの平面図である。FIG. 2 is a plan view of the field-effect transistor of FIG.
【図３】図２の素子保護及び外部接続体の底面図であ
る。FIG. 3 is a bottom view of the device protection and external connection body of FIG. 2;
【図４】図１の電界効果トランジスタを回路基板に取り
付けた状態を示す断面図である。FIG. 4 is a cross-sectional view showing a state where the field-effect transistor of FIG. 1 is mounted on a circuit board.
【図５】従来の電界効果トランジスタの断面図である。FIG. 5 is a sectional view of a conventional field-effect transistor.
【図６】変形例の素子保護及び外部接続体の平面図であ
る。FIG. 6 is a plan view of an element protection and external connection body of a modification.
【図７】別の変形例の素子保護及び外部接続体の断面図
である。FIG. 7 is a sectional view of an element protection and external connection body of another modification.
１１ 放熱板 １２ 絶縁部材 １３ チップ １６ａ、１６ｂ、１６ｃ、１７ａ、１７ｂ、１７ｃ 導
体膜DESCRIPTION OF SYMBOLS 11 Heat sink 12 Insulating member 13 Chip 16a, 16b, 16c, 17a, 17b, 17c Conductive film
Claims (4)
接続体とから成り、 前記半導体素子は前記放熱体の一方の主面に固着され、 前記外部接続体は絶縁部材とこの表面に形成された導体
膜とから成り、 前記絶縁部材は前記放熱体の一方の主面に直接又は導体
膜を介して固着された第１の部分と前記放熱体の一方の
主面の延長方向に前記放熱体の一方の主面から張り出し
た第２の部分とを有し、 前記絶縁部材の前記第１の部分の主面の少なくとも一部
及び前記第２の部分の主面の少なくとも一部に導体膜が
設けられ、 前記第１の部分の導体膜と前記第２の部分の導体膜とは
互いに接続され、 前記半導体素子と前記第１の部分の前記導体膜とが前記
内部接続体によって電気的に接続され、 前記絶縁部材の前記第２の部分が可撓性を有しているこ
とを特徴とする半導体装置。1. A semiconductor device comprising a semiconductor element, a heat radiator, an external connector and an internal connector, wherein the semiconductor element is fixed to one main surface of the heat radiator, and the external connector is formed on an insulating member and this surface. The insulating member is provided on the first main surface of the heat radiator directly or via a conductive film, and the heat radiating member extends in the extending direction of the one main surface of the heat radiator. A second portion protruding from one main surface of the body, and a conductive film on at least a part of a main surface of the first portion and at least a part of a main surface of the second portion of the insulating member. The conductor film of the first portion and the conductor film of the second portion are connected to each other, and the semiconductor element and the conductor film of the first portion are electrically connected by the internal connector. Connected, the second portion of the insulating member has flexibility Wherein a.
部リード用導体膜と内部接続体とから成り、 前記半導体素子は前記放熱体の一方の主面の中央に固着
され、前記絶縁部材は中央に孔を有する環状部分とこの環状部
分から張り出している外部リード用部分とを有し、 前記環状部分は前記孔の中に前記半導体素子を収容する
ように配置され且つ前記放熱体の一方の主面に直接又は
導体膜を介して固着され、 前記外部リード用部分は前記環状部分に支持され且つ前
記放熱体の一方の主面から張り出すように形成され、 前記外部リード用導体膜は前記絶縁部材の前記環状部分
及び前記外部リード用部分に形成され、 前記内部接続体は前記半導体素子と前記導体膜とを接続
し ていることを特徴とする半導体装置。2. A semiconductor device, a radiator, a plate-like insulating member, and an outer member.
The semiconductor element is fixed to the center of one main surface of the heat radiator, and the insulating member has an annular portion having a hole at the center and the annular portion.
An external lead portion that protrudes from the outside, and the annular portion accommodates the semiconductor element in the hole.
And directly or on one main surface of the heat radiator
The portion for external leads is fixed through a conductive film, and the portion for external leads is
The external lead conductor film is formed so as to protrude from one main surface of the heat radiator, and the external lead conductor film is formed in the annular portion of the insulating member.
And the external connection portion is formed on the external lead portion, and the internal connection body connects the semiconductor element and the conductor film.
Wherein a being.
りも幅狭に形成された帯状部分であり、且つその主面に
対して垂直な方向に可撓性を有するように形成されてい
ることを特徴とする請求項２記載の半導体装置。Wherein said outer lead for parts are strip portion formed narrower than said annular portion, and that is formed so as to have flexibility in a direction perpendicular to the main surface 3. The semiconductor device according to claim 2, wherein:
脂が設けられていることを特徴とする請求項２又は３記
載の半導体装置。4. The semiconductor device according to claim 2 or 3, wherein the protective resin covering the semiconductor element is provided.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5342886A JP2913500B2 (en) | 1993-12-14 | 1993-12-14 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5342886A JP2913500B2 (en) | 1993-12-14 | 1993-12-14 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07169874A JPH07169874A (en) | 1995-07-04 |
| JP2913500B2 true JP2913500B2 (en) | 1999-06-28 |
Family
ID=18357277
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5342886A Expired - Fee Related JP2913500B2 (en) | 1993-12-14 | 1993-12-14 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2913500B2 (en) |
-
1993
- 1993-12-14 JP JP5342886A patent/JP2913500B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07169874A (en) | 1995-07-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR950012921B1 (en) | Plastic mold semiconductor device | |
| US6566164B1 (en) | Exposed copper strap in a semiconductor package | |
| JP4264375B2 (en) | Power semiconductor module | |
| KR100229858B1 (en) | Semiconductor device | |
| US20040061138A1 (en) | Power semiconductor device with high radiating efficiency | |
| JP4570092B2 (en) | Semiconductor module | |
| JPH1174433A (en) | Semiconductor device | |
| JP7158392B2 (en) | power semiconductor module | |
| JPH064595Y2 (en) | Hybrid IC | |
| JP7210868B2 (en) | semiconductor equipment | |
| CN110914975B (en) | Power semiconductor module | |
| US5063434A (en) | Plastic molded type power semiconductor device | |
| US6717260B2 (en) | Clip-type lead frame for source mounted die | |
| KR20050042724A (en) | Semiconductor apparatus | |
| KR20050011714A (en) | Power semiconductor module with base plate resistant to bending | |
| KR20050004007A (en) | Semiconductor device and hybrid integrated circuit device | |
| US6664629B2 (en) | Semiconductor device | |
| US5324890A (en) | Direct bond copper-output footprint | |
| JP2913500B2 (en) | Semiconductor device | |
| JP2002118215A (en) | Semiconductor device | |
| JP2533011B2 (en) | Surface mount semiconductor device | |
| KR19980063740A (en) | Multilayer Leadframe for Molded Packages | |
| JPS6329413B2 (en) | ||
| EP0181975B1 (en) | Semiconductor device comprising a support body | |
| KR100212392B1 (en) | Semiconductor package |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| LAPS | Cancellation because of no payment of annual fees |