JPH11340377A - Surface mount type semiconductor device - Google Patents

Surface mount type semiconductor device

Info

Publication number
JPH11340377A
JPH11340377A JP14088398A JP14088398A JPH11340377A JP H11340377 A JPH11340377 A JP H11340377A JP 14088398 A JP14088398 A JP 14088398A JP 14088398 A JP14088398 A JP 14088398A JP H11340377 A JPH11340377 A JP H11340377A
Authority
JP
Japan
Prior art keywords
lead
semiconductor device
resin
resin package
hall element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14088398A
Other languages
Japanese (ja)
Inventor
Motoo Adachi
元男 足立
Kazuhide Sato
和秀 佐藤
Hiroshi Sakai
浩史 酒井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP14088398A priority Critical patent/JPH11340377A/en
Publication of JPH11340377A publication Critical patent/JPH11340377A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/3754—Coating
    • H01L2224/37599—Material
    • H01L2224/376—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PROBLEM TO BE SOLVED: To improve heat radiation characteristic at the time of mounting a small-sized surface mount type semiconductor device, and improve magnetic field detection characteristic at the time of mounting a Hall element. SOLUTION: A Hall element 3 is sealed in a resin package 1 where a first resin molding part 1a which is molded on one side interposing leads 2a, 2b and is relatively thin and a second resin molding part which is molded on the other side interposing the leads 2a, 2b and is relatively thick are collectively molded integrally. The leads 2a, 2b protruded outside the resin package 1 are bent in the direction of the first resin molding part 1a which is relatively thick, and the main surface of the Hall element 3 is mounted in the upside direction of the resin package 1.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、小型の表面実装型
半導体装置に関し、特にホール素子に適した表面実装型
半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a small-sized surface-mounted semiconductor device, and more particularly to a surface-mounted semiconductor device suitable for a Hall element.

【０００２】[0002]

【従来の技術】電子回路基板の小型化および高密度実装
化に伴い、ダイオードなどに代表される半導体装置は、
ますます小型化、表面実装化が要求されている。2. Description of the Related Art With the miniaturization and high-density mounting of electronic circuit boards, semiconductor devices typified by diodes and the like are:
There is an increasing demand for miniaturization and surface mounting.

【０００３】図４は従来の表面実装型半導体装置の断面
図である。樹脂パッケージ１は、対向するリード２ａ、
２ｂを挟んで下側に成形された第１の樹脂成形部１ａ
と、リードを挟んで上側に成形された第２の樹脂成形部
１ｂとが一体成形されてなる。樹脂パッケージ１内に
は、一方のリード２ａに半導体素子３がその主面を樹脂
パッケージ１の底面に向けて搭載され、他方のリード２
ｂとボンディングワイヤ４で結線されている。FIG. 4 is a sectional view of a conventional surface mount type semiconductor device. The resin package 1 includes opposing leads 2a,
First resin molded part 1a molded on the lower side with respect to 2b
And a second resin molded part 1b molded upward with the lead interposed therebetween. In the resin package 1, the semiconductor element 3 is mounted on one lead 2 a with its main surface facing the bottom of the resin package 1, and the other lead 2 a
b and a bonding wire 4.

【０００４】このような表面実装型半導体装置は、樹脂
パッケージ１の寸法が、例えば高さ１．５ｍｍ以下とい
う小型化を実現するため、半導体素子３を封止するのに
最低限の厚みをもった第１の樹脂成形部１ａに対し、第
２の樹脂成形部１ｂの厚みを相対的に薄く成形してい
る。In such a surface-mount type semiconductor device, the size of the resin package 1 is reduced to, for example, 1.5 mm or less in height. The thickness of the second resin molded part 1b is relatively thinner than that of the first resin molded part 1a.

【０００５】樹脂パッケージ１の外方に突出したリード
２ａ、２ｂは、第１の樹脂成形部１ａに向けてクランク
形状に曲折し、プリント基板に表面実装できるように樹
脂パッケージ１の底面と略同一面に延在している。The leads 2a and 2b projecting outward from the resin package 1 are bent in a crank shape toward the first resin molded portion 1a, and are substantially the same as the bottom surface of the resin package 1 so that they can be surface-mounted on a printed circuit board. Extending to the surface.

【０００６】[0006]

【発明が解決しようとする課題】以上説明した従来の表
面実装型半導体装置は、プリント基板に実装する際、相
対的に厚みの厚い第１の樹脂成形部がプリント基板側に
位置するため、リードおよび半導体素子とプリント基板
との距離が長くなり、放熱性が悪いという問題がある。In the conventional surface mount type semiconductor device described above, when mounted on a printed circuit board, the first resin molded portion having a relatively large thickness is located on the printed circuit board side. In addition, there is a problem that the distance between the semiconductor element and the printed circuit board is increased, and heat radiation is poor.

【０００７】また、半導体素子としてホール素子を採用
した場合、図５に示すように、表面実装型半導体装置は
プリント基板６に実装され、その上方に配置した磁石７
から発生する磁界をホール素子３が検出し、ホール素子
の出力端子から磁界の強さに応じた出力電圧を発生させ
て使用する。ところが、従来の表面実装型半導体装置で
は、リード２ａ、２ｂを挟んで樹脂パッケージ１の上側
に成形した第２の樹脂成形部１ｂにホール素子３を封止
するための十分な厚みがないため、リードを挟んで樹脂
パッケージ１の下側に成形した第１の樹脂成形部１ａに
ホール素子３を封止している。このため、リードよりも
下側にホール素子３を搭載、すなわち、ホール素子３の
主面がプリント基板６側に向けて搭載される。この結
果、ホール素子３の主面と磁石７との距離が長くなり、
ホール素子３の磁界検出特性が低下するという問題があ
る。When a Hall element is employed as a semiconductor element, as shown in FIG. 5, a surface-mount type semiconductor device is mounted on a printed circuit board 6 and a magnet 7 disposed above the printed circuit board 6.
The Hall element 3 detects a magnetic field generated by the Hall element, and generates and uses an output voltage according to the strength of the magnetic field from an output terminal of the Hall element. However, in the conventional surface mount type semiconductor device, the second resin molded portion 1b molded above the resin package 1 with the leads 2a and 2b interposed therebetween does not have a sufficient thickness for sealing the Hall element 3; The Hall element 3 is sealed in a first resin molded portion 1a molded below the resin package 1 with the lead therebetween. For this reason, the Hall element 3 is mounted below the lead, that is, the main surface of the Hall element 3 is mounted toward the printed circuit board 6 side. As a result, the distance between the main surface of the Hall element 3 and the magnet 7 increases,
There is a problem that the magnetic field detection characteristics of the Hall element 3 deteriorate.

【０００８】本発明は、上記の問題を解決するものであ
り、小型の表面実装型半導体装置の実装時の放熱特性を
向上することができ、さらにホール素子を搭載した場合
に磁界検出特性を向上することができる表面実装型半導
体装置を提供することを目的とする。The present invention has been made to solve the above-mentioned problems, and can improve the heat radiation characteristics when a small surface-mount type semiconductor device is mounted, and can further improve the magnetic field detection characteristics when a Hall element is mounted. It is an object of the present invention to provide a surface-mount type semiconductor device capable of performing the above.

【０００９】[0009]

【課題を解決するための手段】本発明は、樹脂パッケー
ジ内にリードおよびこのリードに搭載した半導体素子を
封止し、前記樹脂パッケージの外方に突出したリードを
表面実装できるように曲折した表面実装型半導体装置に
おいて、前記樹脂パッケージは、リードを挟んで一方に
成形した相対的に厚みの薄い第１の樹脂成形部と、リー
ドを挟んで他方に成形した相対的に厚みの厚い第２の樹
脂成形部とを一体成形してなり、前記樹脂パッケージの
外方に突出したリードが、相対的に厚みの薄い前記第１
の樹脂成形部の方向に曲折し、かつ、前記半導体素子の
主面を、前記リードが曲折した方向の逆方向に向けて搭
載した表面実装型半導体装置である。SUMMARY OF THE INVENTION The present invention is directed to a method of sealing a lead and a semiconductor element mounted on the lead in a resin package, and forming a bent surface so that a lead protruding outward from the resin package can be surface-mounted. In the mounting type semiconductor device, the resin package includes a relatively thin first resin molded portion molded on one side with a lead interposed therebetween, and a relatively thick second resin molded portion molded on the other side with the lead interposed therebetween. The resin molded part is integrally molded, and the lead protruding outward from the resin package is provided with a relatively thin first lead.
And a main surface of the semiconductor element is mounted in a direction opposite to a direction in which the lead is bent.

【００１０】この構成によると、相対的に厚みの薄い第
１の樹脂成形部に向けてリードを曲折しているため、プ
リント基板実装時には相対的に厚みの薄い第１の樹脂成
形部を下側に、すなわちプリント基板側に向けて実装さ
れることとなる。このため、プリント基板とリードおよ
び半導体素子との距離が短くなり、放熱性を向上するこ
とができる。According to this configuration, since the lead is bent toward the first resin molded portion having a relatively small thickness, the first resin molded portion having a relatively small thickness is placed on the lower side when the printed circuit board is mounted. , That is, toward the printed circuit board side. For this reason, the distance between the printed board, the lead, and the semiconductor element is shortened, and the heat dissipation can be improved.

【００１１】また、相対的に厚みの厚い第２の樹脂成形
部がリードを挟んで上側に成形されているため、リード
の上方に半導体素子を封止できる。この結果、ホール素
子を採用した場合において、その主面が上側、すなわち
実装時に磁石が配置された側に向けて搭載することがで
き、ホール素子の磁界検出特性を向上することができ
る。Further, since the relatively thick second resin molded portion is molded above the lead, the semiconductor element can be sealed above the lead. As a result, when the Hall element is adopted, the Hall element can be mounted with its main surface facing upward, that is, on the side where the magnets are arranged during mounting, and the magnetic field detection characteristics of the Hall element can be improved.

【００１２】[0012]

【発明の実施の形態】以下、本発明の実施の形態につい
て図面を参照しながら説明する。Embodiments of the present invention will be described below with reference to the drawings.

【００１３】（実施の形態１）図１は本実施の形態によ
る表面実装型半導体装置の断面図である。樹脂パッケー
ジ１の寸法は、縦１．５ｍｍ、横２．９ｍｍ、高さ１．
１ｍｍである。リードは、半導体素子搭載用が１端子と
ワイヤボンディング用が２端子の３端子タイプである
が、図中、ワイヤボンディング用の１本は省略し、２
ａ、２ｂの２端子のみを表示する。なお、半導体素子３
には、ホール素子を用いている。(Embodiment 1) FIG. 1 is a sectional view of a surface mount type semiconductor device according to the present embodiment. The dimensions of the resin package 1 are 1.5 mm in length, 2.9 mm in width, and 1.
1 mm. The lead is of a three-terminal type having one terminal for mounting a semiconductor element and two terminals for wire bonding. In FIG.
Only the two terminals a and 2b are displayed. The semiconductor element 3
Uses a Hall element.

【００１４】樹脂パッケージ１は、対向するリード２
ａ、２ｂを挟んで下側に成形された第１の樹脂成形部１
ａと、リードを挟んで上側に成形された第２の樹脂成形
部１ｂとが一体成形されてなる。第１の樹脂成形部の厚
みは０．３ｍｍ、第２の樹脂成形部の厚みは０．８ｍｍ
であり、樹脂パッケージ１の下側に位置する第１の樹脂
成形部１ａの厚みが相対的に薄く成形されている。樹脂
パッケージ１内には、一方のリード２ａにホール素子３
が、その主面を樹脂パッケージ１の上面に向けて搭載さ
れ、他方のリード２ｂとボンディングワイヤ４で結線さ
れている。樹脂パッケージ１の外方に突出したリード２
ａ、２ｂは、厚みの薄い第１の樹脂成形部１ａの方向に
クランク形状に曲折し、樹脂パッケージ１の底面と略同
一面に延在している。The resin package 1 is composed of opposing leads 2
a, the first resin molded part 1 formed on the lower side with respect to 2b
a and a second resin molded portion 1b molded upward with the lead interposed therebetween. The thickness of the first resin molded part is 0.3 mm, and the thickness of the second resin molded part is 0.8 mm
The thickness of the first resin molded portion 1a located below the resin package 1 is relatively small. In the resin package 1, one of the leads 2a has a Hall element 3 attached thereto.
Are mounted with their main surfaces facing the upper surface of the resin package 1, and are connected to the other leads 2 b by bonding wires 4. Lead 2 projecting outward from resin package 1
a and 2b are bent in the shape of a crank in the direction of the first resin molded portion 1a having a small thickness, and extend substantially in the same plane as the bottom surface of the resin package 1.

【００１５】このような構成であるため、プリント基板
に実装した際には、相対的に厚みの薄い第１の樹脂成形
部がプリント基板側に配置され、リードおよび半導体素
子とプリント基板との距離が短くなり、放熱性が向上す
る。With this configuration, when mounted on a printed circuit board, the first resin molded portion having a relatively small thickness is arranged on the printed circuit board side, and the distance between the lead and the semiconductor element and the printed circuit board is reduced. And the heat radiation is improved.

【００１６】また、相対的に厚みの厚い第２の樹脂成形
部がリードを挟んで上側に成形されているため、リード
の上側に半導体素子を搭載、すなわち半導体素子の主面
を樹脂パッケージの上方に向けて搭載できる。この結
果、プリント基板実装時には、磁石を配置した側に半導
体素子の主面が向き、ホール素子の磁界検出特性を向上
することができる。Further, since the relatively thick second resin molded portion is molded above the lead, the semiconductor element is mounted above the lead, that is, the main surface of the semiconductor element is placed above the resin package. Can be mounted for As a result, when the printed circuit board is mounted, the main surface of the semiconductor element faces the side where the magnet is arranged, and the magnetic field detection characteristics of the Hall element can be improved.

【００１７】本発明は、以上説明した構造に限ることな
く、例えば図２に示すように、樹脂パッケージ１内の一
方のリード２ｂをあらかじめ曲折しておき、半導体素子
１の主面に直接、リード２ｂを接続した構造や、図３に
示すように、ボンディングワイヤの代わりに、金属製の
接続端子５を採用した構造など本発明の思想に逸脱しな
い限り、適宜変更可能である。The present invention is not limited to the structure described above. For example, as shown in FIG. 2, one lead 2b in the resin package 1 is bent in advance, and the lead 2b is directly connected to the main surface of the semiconductor element 1. The structure can be changed as appropriate without departing from the spirit of the present invention, such as a structure connecting 2b and a structure employing metal connection terminals 5 instead of bonding wires as shown in FIG.

【００１８】[0018]

【発明の効果】以上説明したように本発明によれば、小
型の表面実装型半導体装置においても、実装時の放熱性
を向上することができる。As described above, according to the present invention, even in a small surface mount type semiconductor device, the heat radiation during mounting can be improved.

【００１９】また、半導体素子としてホール素子を搭載
した場合、素子の主面を磁石が配置された側に向けるこ
とができるため、磁界検出特性が向上する。When a Hall element is mounted as a semiconductor element, the main surface of the element can be directed to the side where the magnets are arranged, so that the magnetic field detection characteristics are improved.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の一実施の形態による表面実装型半導体
装置を示す断面図FIG. 1 is a sectional view showing a surface-mounted semiconductor device according to an embodiment of the present invention;

【図２】本発明の他の実施形態による表面実装型半導体
装置を示す断面図FIG. 2 is a sectional view showing a surface-mounted semiconductor device according to another embodiment of the present invention;

【図３】本発明のさらに他の実施形態による表面実装型
半導体装置を示す断面図FIG. 3 is a sectional view showing a surface-mounted semiconductor device according to still another embodiment of the present invention;

【図４】従来の表面実装型半導体装置を示す断面図FIG. 4 is a cross-sectional view showing a conventional surface mount type semiconductor device.

【図５】従来の表面実装型半導体装置にホール素子を用
いた場合の説明図FIG. 5 is an explanatory view of a case where a Hall element is used in a conventional surface mount semiconductor device.

【符号の説明】[Explanation of symbols]

１ 樹脂パッケージ １ａ 第１の樹脂成形部 １ｂ 第２の樹脂成形部 ２ａ リード ２ｂ リード ３ 半導体素子 ４ ボンディングワイヤ ５ 接続端子 ６ プリント基板 ７ 磁石 DESCRIPTION OF SYMBOLS 1 Resin package 1a 1st resin molding part 1b 2nd resin molding part 2a Lead 2b Lead 3 Semiconductor element 4 Bonding wire 5 Connection terminal 6 Printed circuit board 7 Magnet

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】 樹脂パッケージ内にリードおよびこのリ
ードに搭載した半導体素子を封止し、前記樹脂パッケー
ジの外方に突出したリードを表面実装できるように曲折
した表面実装型半導体装置において、前記樹脂パッケー
ジは、リードを挟んで一方に成形した相対的に厚みの薄
い第１の樹脂成形部と、リードを挟んで他方に成形した
相対的に厚みの厚い第２の樹脂成形部とを一体成形して
なり、前記樹脂パッケージの外方に突出したリードが、
相対的に厚みの薄い前記第１の樹脂成形部の方向に曲折
し、かつ、前記半導体素子の主面を、前記リードが曲折
した方向の逆方向に向けて搭載したことを特徴とする表
面実装型半導体装置。1. A surface-mounted semiconductor device in which a lead and a semiconductor element mounted on the lead are sealed in a resin package and a lead protruding outward from the resin package is bent so as to be surface-mounted. The package is formed by integrally molding a relatively thin first resin molded portion molded on one side with the lead interposed therebetween and a relatively thick second resin molded portion molded on the other side with the lead interposed therebetween. The leads protruding outward from the resin package,
A surface mounting portion which is bent in the direction of the first resin molded portion having a relatively small thickness, and has a main surface of the semiconductor element mounted in a direction opposite to a direction in which the leads are bent. Type semiconductor device. 【請求項２】 前記樹脂パッケージの寸法は、高さ１．
５ｍｍ以下である請求項１記載の表面実装型半導体装
置。2. The resin package has a height of 1.
2. The surface-mounted semiconductor device according to claim 1, which is not more than 5 mm. 【請求項３】 前記半導体素子は、ホール素子である請
求項１および２記載の表面実装型半導体装置。3. The surface-mounted semiconductor device according to claim 1, wherein said semiconductor element is a Hall element.
JP14088398A 1998-05-22 1998-05-22 Surface mount type semiconductor device Pending JPH11340377A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14088398A JPH11340377A (en) 1998-05-22 1998-05-22 Surface mount type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14088398A JPH11340377A (en) 1998-05-22 1998-05-22 Surface mount type semiconductor device

Publications (1)

Publication Number Publication Date
JPH11340377A true JPH11340377A (en) 1999-12-10

Family

ID=15278997

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14088398A Pending JPH11340377A (en) 1998-05-22 1998-05-22 Surface mount type semiconductor device

Country Status (1)

Country Link
JP (1) JPH11340377A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006060106A (en) * 2004-08-23 2006-03-02 Origin Electric Co Ltd Lead member and surface mounted semiconductor device
JP2009168721A (en) * 2008-01-18 2009-07-30 Nippon Thompson Co Ltd Small sliding device
JP2014002165A (en) * 2013-08-08 2014-01-09 Nippon Thompson Co Ltd Small slide device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006060106A (en) * 2004-08-23 2006-03-02 Origin Electric Co Ltd Lead member and surface mounted semiconductor device
JP2009168721A (en) * 2008-01-18 2009-07-30 Nippon Thompson Co Ltd Small sliding device
JP2014002165A (en) * 2013-08-08 2014-01-09 Nippon Thompson Co Ltd Small slide device

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