JPH0547975A - Lead frame and surface package-type semiconductor device - Google Patents
Lead frame and surface package-type semiconductor deviceInfo
- Publication number
- JPH0547975A JPH0547975A JP2255706A JP25570690A JPH0547975A JP H0547975 A JPH0547975 A JP H0547975A JP 2255706 A JP2255706 A JP 2255706A JP 25570690 A JP25570690 A JP 25570690A JP H0547975 A JPH0547975 A JP H0547975A
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- island
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- islands
- leads
- lead frame
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 (イ)産業上の利用分野 本発明はアイランドサイズを最大にできる表面 実装用のリードフレームと半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a surface mounting lead frame and a semiconductor device capable of maximizing an island size.
(ロ)従来の技術 従来より軽薄短小化を実現する1つの手段とし て、プリント基板の導電パターン上にリードを対 向接着する所謂CP、PCPと称される表面実装 型の半導体パッケージがある(例えば、特開平0 1−184059号公報)。第8図と第9図は斯 る装置を示し、(1)は半導体チップ、(2)は半導体 チップ(1)を搭載するアイランド、(3)はアイラン ド(2)を保持する為のタイバー、(4)(5)はリー ド、(6)はワイヤ、(7)はモールド樹脂である。(B) Conventional technology As one means to realize lighter, thinner, smaller, and smaller devices than before, there are surface-mounted semiconductor packages called CP and PCP, in which leads are face-bonded to the conductive pattern of the printed circuit board ( For example, JP-A-01-184059). FIGS. 8 and 9 show such a device, (1) is a semiconductor chip, (2) is an island on which the semiconductor chip (1) is mounted, and (3) is a tie bar for holding the island (2). , (4) and (5) are leads, (6) is a wire, and (7) is a molding resin.
このような表面実装型ですら、近年は一層の高 密度化と大出力化が求められており、そのために 搭載される半導体チップ(1)も1個から2個へま たはより大きなチップを搭載することが望まれて いる。従ってこれらの要求に対応するため、リー ドフレームのアイランド(2)も大きくしたいとい う要求があった。また、放熱性の点でアイランド (2)の裏面を露出したいという意向もあった。 In recent years, even with such surface mount type, higher density and higher output have been demanded, and for this reason, the number of semiconductor chips (1) to be mounted is reduced from one to two or larger chips. It is desired to be installed. Therefore, to meet these demands, there was a demand to increase the size of the leadframe island (2). There was also an intention to expose the back surface of the island (2) in terms of heat dissipation.
(ハ)発明が解決しようとする課題 しかしながら、リードフレームは1枚の板状材 料から打ち抜きまたはエッチングにより製造さ れ、その加工に板厚と同程度の抜きしろを要する ので、リード(4)(5)とアイランド(2)との間隔を 狭めることができず、そのために外形寸法が定め られたパッケージではアイランド(2)の面積を増 大できない欠点があった。(C) Problems to be Solved by the Invention However, since the lead frame is manufactured by punching or etching from one plate-shaped material, and the processing requires a margin equal to the plate thickness, the lead (4) The distance between (5) and the island (2) cannot be narrowed, and therefore, there is a drawback in that the area of the island (2) cannot be increased in a package whose outer dimensions are defined.
これを解決する1つの手法としてリードフレー ムの板厚自体を薄くして前記抜きしろの分を小さ くすることが考えられる。しかしながら、この手 法ではアイランド(2)の板厚も薄くなり、前述し たアイランド(2)の裏面を露出する構成ではアイ ランド(2)周囲に段差を形成する潰し加工ができ なくなる欠点があった。潰し加工で段差を付けて おかないと、アイランド(2)と樹脂との密着力が 弱く実用に耐えない。 As one method to solve this, it is considered that the thickness of the lead frame is reduced to reduce the amount of the clearance. However, with this method, the plate thickness of the island (2) also becomes thin, and the above-mentioned configuration in which the back surface of the island (2) is exposed has the drawback that the crushing process that forms a step around the island (2) cannot be performed. It was If there is no level difference in the crushing process, the adhesion between the island (2) and the resin will be weak and it will not be practical.
(ニ)課題を解決するための手段 本発明は上記従来の欠点に鑑み成されたもの で、アイランド(11)の板厚に比べリード(12)の板 厚が薄いリードフレームを用い、リード(12)の先 端部(13)とアイランド(11)との間隔をリード(12) の板厚程度まで狭めることにより、アイランド(1 1)の面積を増大したリードフレームとその半導体 装置を提供するものである。(D) Means for Solving the ProblemsThe present invention has been made in view of the above-mentioned drawbacks of the related art, and uses a lead frame in which the lead (12) is thinner than the island (11). Provided is a lead frame and its semiconductor device in which the area of the island (11) is increased by reducing the distance between the tip (13) of the (12) and the island (11) to about the thickness of the lead (12). It is a thing.
(ホ)作用 本発明によれば、リード(12)の板厚を薄くした 分抜きしろが少くて済み、その分をアイランド(1 1)面積の増大に用いることができる。また、アイ ランド(11)部は潰し加工を処せるだけの板厚を持 たせているので、段差(20)によってアイランド(1 1)と樹脂(19)との密着性を保つことができる。(E) Function According to the present invention, the lead (12) can be thinned to reduce the extraction margin and can be used for increasing the area of the island (11). Further, since the land portion (11) has a plate thickness sufficient for crushing, the step (20) can maintain the adhesion between the island (11) and the resin (19).
(ヘ)実施例 以下に本発明の一実施例を図面を参照しながら 詳細に説明する。(F) Embodiment One embodiment of the present invention will be described in detail below with reference to the drawings.
第1図は本発明のリードフレームを示す平面図 であり、(11)は半導体チップを搭載するためのア イランド、(12)は先端をアイランド(11)に近接す るように延在しその先端に拡張部(13)を有する リード、(14)はアイランド(11)を連結細条(15)に 保持するタイバーである。このリードフレームは 2チップ構成用に設計され、チップの基板電位を 共用とする場合用に1つのアイランド(11)を持つ 第1のパターン(16)を、異電位とする場合用に2 つのアイランド(11)を持つ第2のパターン(17)を 設計できるようにしてある。2チップの組合わせ は、トランジスタ−トランジスタ、トランジス タ−ダイオード、ダイオード−ダイオードの3種 類である。(18)はユーザ設計によって前記基板電 位の取り出しリードとして使うことが可能な保持 リードであり、第1のパターン(16)と第2のパ ターン(17)とで形状が等しいのは金型の共用を可 能とするためである。尚、図面上では第1と第2 のパターン(16)(17)が混在するが製造上は一定長 さの短冊状リードフレームにどちらか一方のパ ターンを形成したものを利用する。FIG. 1 is a plan view showing a lead frame of the present invention. (11) is an island for mounting a semiconductor chip, and (12) is a tip extending near the island (11). A lead having an extension portion (13) at the tip, and a tie bar (14) for holding the island (11) in the connecting strip (15). This lead frame is designed for a two-chip configuration, and the first pattern ( 16 ) has one island (11) for sharing the substrate potential of the chip and two islands for different potentials. The second pattern ( 17 ) with (11) can be designed. There are three types of two-chip combinations: transistor-transistor, transistor-diode, and diode-diode. (18) is a holding lead that can be used as a lead for taking out the substrate potential according to the user design, and the first pattern ( 16 ) and the second pattern ( 17 ) have the same shape in the mold. This is because it is possible to share. Although the first and second patterns ( 16 ) and ( 17 ) are mixed in the drawing, a strip-shaped lead frame having a fixed length and one of the patterns formed is used in manufacturing.
リードフレームはリード(12)部形成用の薄い部 分とアイランド(11)部形成用の厚い部分を有する 1枚の銅系素材から成る板状材料を打ち抜き加工 することにより製造される。板厚はリード(12)用 の薄い部分で0.2mm、アイランド用の厚い部分 で0.4mmである。 The lead frame is manufactured by punching a sheet of copper-based material having a thin portion for forming the lead (12) portion and a thick portion for forming the island (11) portion. The plate thickness is 0.2 mm in the thin part for the lead (12) and 0.4 mm in the thick part for the island.
リード(12)とアイランド(11)とは前記板状材料 の薄い部分で切断され、そのため両者の間隔(図 示x)は板厚と同じか又は板厚の80%程度まで 狭めることができる。リード(12)とタイバー(14) との間隔も同じである。リード(12)先端の拡張部 (13)は金ワイヤ等のボンディングポストとして、 および樹脂(19)からの抜け防止の意味で拡張され ている。 The lead (12) and the island (11) are cut at a thin portion of the plate-like material, so that the distance between them (x in the figure) can be made equal to the plate thickness or can be reduced to about 80% of the plate thickness. The distance between the lead (12) and the tie bar (14) is also the same. The extended portion (13) at the tip of the lead (12) is extended as a bonding post for a gold wire or the like, and for the purpose of preventing the resin (19) from coming off.
アイランド(11)はタイバー(14)に近い部分と前 記切断を受ける部分で前記薄い板厚を有し、その 他のリード(12)とは隣接しない部分は前記厚い板 厚を有する。そして厚い板厚を有するアイランド (11)の周囲3辺には、第2図のAA線断面図に示 す如く樹脂(19)からのアイランド(11)の剥離を防 止する突出部(20)を形成するために深さ0.2mm 程の潰し加工を処してある。この潰し加工は板厚 が大体0.4mm以上ないと加工が困難となる。 The island (11) has the thin plate thickness at the portion close to the tie bar (14) and the portion to be cut as described above, and the thick plate thickness at the portion not adjacent to the other leads (12). Then, on three sides around the island (11) having a large plate thickness, as shown in the cross-sectional view taken along the line AA in FIG. A crushing process is performed to a depth of about 0.2 mm to form This crushing process becomes difficult unless the plate thickness is 0.4 mm or more.
タイバー(14)はリード(12)を打ち抜いた後スタ ンピング加工により第3図に示すように上方へ折 り曲げ、樹脂(19)の厚みのほぼ半分となる位置で 再度折り曲げて水平に延在させる。同図において (21)は半導体チップ、(22)はボンディングワイヤ を示す。 The tie bar (14) is punched out from the lead (12) and then bent upward by stamping, as shown in Fig. 3, and bent again at a position where it is approximately half the thickness of the resin (19) and extends horizontally. Let In the figure, (21) is a semiconductor chip, and (22) is a bonding wire.
上記本願のリードフレームは、リード(12)を形 成する部分の板厚を薄くしたので打ち抜き加工に 要する抜きしろを小さくできる。そのためリード (12)の拡張部(13)とアイランド(11)との間隔を狭 めることができ、狭めた分だけアイランド(11)の 面積を増大できる。従って2チップ構成にも十分 対応できるだけのアイランド(11)面積を確保する ことができる。 In the lead frame of the present application, since the plate thickness of the portion forming the lead (12) is thin, the punching margin required for punching can be reduced. Therefore, the distance between the extended portion (13) of the lead (12) and the island (11) can be narrowed, and the area of the island (11) can be increased by the narrowed distance. Therefore, it is possible to secure the area of the island (11) sufficient to support the 2-chip configuration.
また、リード(12)の拡張部(13)とタイバー(14) との間隔も同様に狭めることができるので、拡張 部(13)をタイバー(14)に向って拡大することが可 能である。拡張部(13)はボンディングポストとし て一定の面積があれば足りるので、前記タイバー (14)へ向って拡大したことをアイランド(11)面積 の一層の増大に寄与させることが可能である。 Further, since the distance between the expansion portion (13) of the lead (12) and the tie bar (14) can be similarly narrowed, the expansion portion (13) can be expanded toward the tie bar (14). .. Since it is sufficient for the expansion portion (13) to have a certain area as a bonding post, the expansion toward the tie bar (14) can contribute to the further increase in the area of the island (11).
第4図と第5図、第6図と第7図に斯るリード フレームにより構成した半導体装置を示す。第4 図と第5図は第1のパターン(16)のリードフレー ムを利用したもので、共通のアイランド(11)に2 個の半導体チップ(21)をダイボンドし、チップ(2 1)表面の電極とリード(12)とをボンディングワイ ヤ(22)でワイヤボンドし、主要部を樹脂(19)で モールドし、タイバー(14)等を切断して個々に分 割したものである。リード(12)のうち樹脂(19)内 部に封止される部分を内部リード(12a)、樹脂(1 9)の外側になる部分を外部リード(12b)と称す る。樹脂(19)はアイランド(11)の裏面のうち板厚 が厚い部分だけを露出するように主要部を封止 し、導出された外部リード(12b)はフォーミング により表面実装可能なリード形状に曲げられる。FIGS. 4 and 5 and FIGS. 6 and 7 show a semiconductor device constituted by the lead frame. Figures 4 and 5 use the lead frame of the first pattern ( 16 ), and two semiconductor chips (21) are die-bonded to a common island (11), and the surface of the chip (21) is shown. The electrode and the lead (12) are wire-bonded with a bonding wire (22), the main part is molded with a resin (19), and the tie bar (14) and the like are cut and individually divided. A portion of the lead (12) sealed in the resin (19) is called an internal lead (12a), and a portion outside the resin (19) is called an external lead (12b). The resin (19) seals the main part of the back surface of the island (11) so as to expose only the thick part, and the derived external leads (12b) are bent into a lead shape that can be surface-mounted by forming. Be done.
この構成はアイランド(11)が共通であるので、 搭載するチップ(21)はチップ(21)の基板電位を共 通にできる組合わせに限られる。前記基板電位を タイバー(14)をリードとして取り出すか保持リー ド(18)をリードとして取り出すかはユーザの任意 である。後者であればタイバー(18)は不要である から適当な長さで切断する。 Since the island (11) is common in this configuration, the mounted chip (21) is limited to a combination in which the substrate potential of the chip (21) can be made common. It is up to the user to take out the substrate potential from the tie bar (14) as a lead or the holding lead (18) as a lead. In the latter case, the tie bar (18) is not needed, so cut it at an appropriate length.
プリント基板(図示せず)上へは、アイランド (11)の裏面がプリント基板又はプリント基板表面 に形成した配線パターンに密着するように各リー ド(12)を半田付けする。リード(12)をフォーミン グ形状にしたのは、前記半田付け時にリード(12) とアイランド(11)間で半田によるブリッジが形成 され両者が短絡する事故を防ぐために、リード(1 2)の先端部分と樹脂(19)との間に空間を設けたも のである。 Each lead (12) is soldered onto the printed circuit board (not shown) so that the back surface of the island (11) is in close contact with the printed circuit board or the wiring pattern formed on the surface of the printed circuit board. The forming of the leads (12) was done in order to prevent a short circuit between the leads (12) and the island (11) due to the formation of a bridge due to solder during the soldering as described above. A space is provided between the portion and the resin (19).
斯る本発明の半導体装置によれば、限られたサ イズ内でアイランド(11)の面積を最大にできるの で、1パッケージ2チップ構成を採ることができ る。また、アイランド(11)の裏面を露出したこと によりある程度の大出力化が可能であり且つアイ ランド(11)の潰し加工によって樹脂(19)とアイラ ンド(11)の密着性をも確保できる。さらにリード (12)の板厚を薄くしたことによりリード(12)の フォーミングを容易に行うことができる。 According to such a semiconductor device of the present invention, the area of the island (11) can be maximized within a limited size, so that a one-package / two-chip configuration can be adopted. Further, by exposing the back surface of the island (11), it is possible to increase the output to some extent, and the crushing process of the land (11) can secure the adhesion between the resin (19) and the eyeland (11). Further, the lead (12) can be easily formed by reducing the plate thickness of the lead (12).
第6図と第7図は他の実施例であり、第1図に おける第2のパターン(17)を利用したものであ る。アイランド(11)が中央で切断され夫々に半導 体チップ(21)を固着すると共にボンディングワイ ヤ(22)で対応するリード(12)と半導体チップ(21) とをワイヤボンドしてある。この構成はアイラン ド(11)の板厚が厚い部分を切断するので当然に抜 きしろが大きくなるものの、2つのアイランド(1 1)が電気的に独立するので、2つの半導体チップ (21)の基板電位を共用できない回路構成に利用で きる。また、基板電位を保持リード(18)から取り 出すものとしてタイバー(14)を途中で切断した例 を図示してある。FIGS. 6 and 7 show another embodiment, which utilizes the second pattern ( 17 ) in FIG. The island (11) is cut at the center, and the semiconductor chips (21) are fixed to each of them, and the corresponding leads (12) and the semiconductor chips (21) are wire-bonded by the bonding wires (22). This structure cuts the thick part of the island (11), which naturally increases the removal margin, but since the two islands (11) are electrically independent, the two semiconductor chips (21) It can be used for circuit configurations that cannot share the substrate potential. Further, an example in which the tie bar (14) is cut in the middle to extract the substrate potential from the holding lead (18) is shown.
斯る構成によれば、2つの半導体チップ(21)の 基板電位を互いに独立させることができるので、 回路応用の幅が広い半導体装置を提供できる。 According to such a configuration, the substrate potentials of the two semiconductor chips (21) can be made independent of each other, so that it is possible to provide a semiconductor device having a wide range of circuit applications.
(ト)発明の効果 以上に説明した通り、本発明によればリード(1 2)の板厚を薄くしたことによりリード(12)の先端 部(13)とアイランド(11)との間隔(第1図x)を 狭めることができるので、その分をアイランド(1 1)の面積の増大特にリード(12)の延在方向と同一方 向の長さを増大して、2チップ構成とすることが できる利点を有する。また、アイランド(11)には 潰し加工により段差(20)を形成することができる ので、アイランド(11)の裏面を露出した半導体装 置にできる利点を有する。さらに、リード(12)の 板厚を薄くしたことによりリード(12)のフォーミ ング加工が容易にできるという利点をも有する。(G) Effect of the Invention As described above, according to the present invention, the gap between the tip portion (13) of the lead (12) and the island (11) is reduced by thinning the lead (12). 1 x) can be narrowed, so the area of the island (11) should be increased, especially by increasing the length in the same direction as the extending direction of the leads (12) to form a 2-chip structure. It has the advantage that Further, since the step (20) can be formed in the island (11) by crushing, there is an advantage that the back surface of the island (11) can be exposed. Furthermore, there is an advantage that the forming process of the lead (12) can be easily performed by reducing the plate thickness of the lead (12).
そして、1パッケージ2チップ構成とすることに より電子機器の一層の軽薄短小化に対応できる利 点をも有する。Moreover, the one-package, two-chip configuration also has the advantage of being able to respond to further miniaturization of electronic equipment.
第1図は本発明のリードフレームを示す平面 図、第2図と第3図は第1図のAA線断面図と側 面図、第4図と第5図は第1のパターン(16)によ り組立てた半導体装置を示す平面図と側面図、第 6図と第7図は第2のパターン(17)により組立て た半導体装置を示す平面図と側面図、第8図と第 9図は従来例を示す平面図と側面図である。FIG. 1 is a plan view showing a lead frame of the present invention, FIGS. 2 and 3 are sectional views and a side view taken along the line AA of FIG. 1, and FIGS. 4 and 5 are first patterns ( 16 ). And FIG. 7 are plan views and side views showing the semiconductor device assembled according to the second pattern ( 17 ), and FIG. 8 and FIG. [Fig. 3] is a plan view and a side view showing a conventional example.
Claims (7)
該 アイランドに先端を近接する如く延在し前記先端 に拡張部を有する内部リードと、前記アイランド を連結細条に保持するタイバーとを具備するリー ドフレームにおいて、前記内部リードとタイバー の板厚を前記アイランドの板厚より薄くすると共 に、前記内部リードの先端部と前記アイランドと の間隔を前記内部リードの板厚に略等しい値まで 狭めたことを特徴とするリードフレーム。1. An island for fixing a semiconductor chip,
In a lead frame including an inner lead extending near the tip of the island and having an expanded portion at the tip, and a tie bar for holding the island in a connecting strip, the plate thicknesses of the inner lead and the tie bar are A lead frame, which is thinner than the plate thickness of the island, and narrows a distance between the tip portion of the inner lead and the island to a value substantially equal to the plate thickness of the inner lead.
処 されていることを特徴とする請求項第1項記載の リードフレーム。2. The lead frame according to claim 1, wherein the peripheral end face of the island is crushed.
特 徴とする請求項第1項記載のリードフレーム。3. The lead frame according to claim 1, wherein the island is a set of two islands.
該 アイランドに先端を近接する如く延在する内部 リードと、前記アイランドの裏面側を露出するよ うに主要部をモールドした樹脂と、前記内部リー ドから連続して前記樹脂の外部に延在し且つ表面 実装用にフォーミングした外部リードとを具備し た表面実装型半導体装置において、 前記内部リードの板厚を前記アイランドの板厚 より薄くすると共に、前記内部リードと前記アイ ランドとの間隔を前記内部リードの板厚に略等し い値まで狭めたことを特徴とする表面実装型半導 体装置。4. An island for fixing a semiconductor chip,
An inner lead extending so that its tip is close to the island, a resin whose main part is molded so as to expose the back surface side of the island, and a resin continuously extending from the inner lead to the outside of the resin and In a surface mount type semiconductor device having an external lead formed for surface mounting, the thickness of the inner lead is made thinner than that of the island, and the distance between the inner lead and the island is set to the inner side. A surface-mount type semiconductor device characterized by narrowing the lead thickness to a value that is approximately equal.
特 徴とする請求項第4項記載の表面実装型半導体装 置。5. The surface mount type semiconductor device according to claim 4, wherein two semiconductor chips are mounted.
イ ランド上に固着したことを特徴とする請求項第5 項記載の表面実装型半導体装置。6. The surface mount semiconductor device according to claim 5, wherein the two semiconductor chips are fixed on one common island.
ン ド上に夫々固着したことを特徴とする請求項第5 項記載の表面実装型半導体装置。7. The surface mount type semiconductor device according to claim 5, wherein the two semiconductor chips are respectively fixed on two islands.
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JP2255706A JP2538407B2 (en) | 1990-09-25 | 1990-09-25 | Surface mount semiconductor device |
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JP2255706A JP2538407B2 (en) | 1990-09-25 | 1990-09-25 | Surface mount semiconductor device |
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JP3157148A Division JP2533012B2 (en) | 1991-06-27 | 1991-06-27 | Surface mount semiconductor device |
JP3157146A Division JP2533011B2 (en) | 1991-06-27 | 1991-06-27 | Surface mount semiconductor device |
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Cited By (3)
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---|---|---|---|---|
DE19732625B4 (en) * | 1996-07-30 | 2005-04-28 | Nec Electronics Corp | Semiconductor Small Package |
JP2007165714A (en) * | 2005-12-15 | 2007-06-28 | Renesas Technology Corp | Semiconductor device |
CN107799498A (en) * | 2016-09-06 | 2018-03-13 | 精工半导体有限公司 | The manufacture method of semiconductor device |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS6441145U (en) * | 1987-09-08 | 1989-03-13 | ||
JPH0233451U (en) * | 1988-08-24 | 1990-03-02 |
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1990
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JPS6441145U (en) * | 1987-09-08 | 1989-03-13 | ||
JPH0233451U (en) * | 1988-08-24 | 1990-03-02 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19732625B4 (en) * | 1996-07-30 | 2005-04-28 | Nec Electronics Corp | Semiconductor Small Package |
JP2007165714A (en) * | 2005-12-15 | 2007-06-28 | Renesas Technology Corp | Semiconductor device |
CN107799498A (en) * | 2016-09-06 | 2018-03-13 | 精工半导体有限公司 | The manufacture method of semiconductor device |
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