JPS62206868A - Electronic device - Google Patents
Electronic deviceInfo
- Publication number
- JPS62206868A JPS62206868A JP61048398A JP4839886A JPS62206868A JP S62206868 A JPS62206868 A JP S62206868A JP 61048398 A JP61048398 A JP 61048398A JP 4839886 A JP4839886 A JP 4839886A JP S62206868 A JPS62206868 A JP S62206868A
- Authority
- JP
- Japan
- Prior art keywords
- external connection
- external connecting
- semiconductor chip
- connection terminal
- connecting terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 21
- 230000017525 heat dissipation Effects 0.000 claims abstract description 12
- 239000000463 material Substances 0.000 claims description 3
- 239000005022 packaging material Substances 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 22
- 229920005989 resin Polymers 0.000 abstract description 6
- 239000011347 resin Substances 0.000 abstract description 6
- 238000007789 sealing Methods 0.000 abstract description 5
- 238000005476 soldering Methods 0.000 description 8
- 230000009977 dual effect Effects 0.000 description 4
- 238000005452 bending Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は電子装置、特に面付は実装される半導体集積回
路１発熱量の大きなトランジスタ等に利用して有効な技
術に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a technique that is effective for use in electronic devices, particularly in semiconductor integrated circuits 1 that are surface-mounted, such as transistors that generate a large amount of heat.
上記半導体集積回路の如き電子装置には、パッケージか
ら突出した複数の外部接続端子をプリント基板に形成さ
れた挿通孔に挿入し、半田付けするように形成したデエ
アルインライン型電子装置がある。Among the electronic devices such as the semiconductor integrated circuits described above, there is an in-line type electronic device in which a plurality of external connection terminals protruding from a package are inserted into insertion holes formed in a printed circuit board and soldered.
しかし実装の容易化、実装密度の向上、更に電子装置の
小型化等があいまって、ｒｓｏｌｉｄ ＳｔａｔｅＴｅ
ｃｈｎｏｌｏｇｙ日本版Ｊ （Ｓｅｐｔｅｍｂｅｒ １
９８２、ｐｐ６９〜７７）Ｋ記載されているように面付
は実装型の電子装置が次第に市場に出回るようになって
きた。However, with the combination of ease of mounting, improvement in packaging density, and miniaturization of electronic devices, rsolid StateTe
chnology Japanese version J (September 1
982, pp. 69-77) K, electronic devices of the imposition-mounted type are gradually becoming available on the market.
その概要は、パッケージの側面から突出した外部接続端
子を、下方に折り曲げ、その先端を更に水平方向に折り
曲げたものである。The outline is that the external connection terminal protruding from the side of the package is bent downward, and its tip is further bent in the horizontal direction.
本発明者等は、上記面付は実装型電子装置の放熱、更に
実装時の機械的強度の向上を図るべく種々の検討を行っ
た。以下は、公知とされた技術ではないが、本発明者等
によって検討された技術であり、その概要は次のとおり
である。The present inventors have conducted various studies in order to improve the heat dissipation of the mounted electronic device and the mechanical strength during mounting by using the above-mentioned surface mounting. Although the following is not a publicly known technique, it is a technique studied by the present inventors, and the outline thereof is as follows.
すなわち、面付は実装型の電子装置は、外部接続端子自
体の形状が小さく、端子間の距離も小である。さもＫ、
実装装置による自動実装も容易である。That is, in a surface-mounted electronic device, the shape of the external connection terminal itself is small, and the distance between the terminals is also small. SamoK,
Automatic mounting using a mounting device is also easy.
一方、パワートランジスタの如き消費電力が大きい電子
装置も開発されているが、この種の電子装置では半導体
チップの発熱量も太き（、放熱性の良いパッケージに半
導体チップを搭載する必要がある。On the other hand, electronic devices such as power transistors that consume a large amount of power have also been developed, but in this type of electronic device, the amount of heat generated by the semiconductor chip is large (and the semiconductor chip must be mounted in a package with good heat dissipation.
本発明者等の検討によると、面付は実装型の電子装置は
高密度実装化を達成するため外部接続端子が細（小さい
。そのため、外部接続端子は変形し易（、しかも端子間
距離が微小であるから短絡等の不測の事故が発生する可
能性が大きいことが明らかになった。According to the studies of the present inventors, surface-mounted electronic devices have thin (small) external connection terminals in order to achieve high-density packaging. It has become clear that because they are so small, there is a high possibility that unexpected accidents such as short circuits will occur.
更に、面付は実装型の電子装置は外部接続端子の表面積
が小であるから、放熱機能を殆ど果し得す、パワートラ
ンジスタの如き発熱量の大きな電子装置は面付は実装型
のパッケージに成しずらいことも明らかになった。Furthermore, surface-mounted electronic devices have a small surface area for external connection terminals, so they can perform most of their heat dissipation functions.For electronic devices that generate a large amount of heat, such as power transistors, surface-mounted electronic devices have a small surface area for external connection terminals. It also became clear that it was difficult to achieve.
本発明の目的は、実装時における機械的強度の向上と放
熱効果の向上とを図り得る電子装置を提供することにあ
る。An object of the present invention is to provide an electronic device that can improve mechanical strength and heat dissipation effect during mounting.
本発明の上記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうちの代表的なものの概
要を簡単に述べれば、下記の通りである。A brief summary of typical inventions disclosed in this application is as follows.
すなわち、発熱量の大きな半導体チップが導電可能に接
着されて放熱効果を有する外部接続端子の表面積を他の
外部接続端子の表面積より太き（し、更に面付は実装可
能に折り曲げるとともに樹脂からなるパッケージ材が連
結する開口部を上記放熱効果を有する外部接続端子に形
成するものである。In other words, the surface area of the external connection terminal, which has a heat dissipating effect when a semiconductor chip that generates a large amount of heat is conductively bonded, is larger than that of other external connection terminals. The opening to which the package material is connected is formed into the external connection terminal having the above-mentioned heat dissipation effect.
上記した手段によれば、半導体チップから発生した熱は
、表面積大の外部接続端子を介して空中に放熱される。According to the above-described means, heat generated from the semiconductor chip is radiated into the air via the external connection terminals having a large surface area.
更に表面積大であるから半田付は面積が大になり、実装
時の機械的強度が向上するとともに、上記開口部を介し
℃パッケージ材の一体となる量が大になる。依りて、電
子装置の実装時の機械的強度と、放熱効果を向上せしめ
るという本発明の目的を達成することができる。Furthermore, since the surface area is large, soldering requires a large area, which improves mechanical strength during mounting, and increases the amount of temperature package material that is integrated through the opening. Therefore, the object of the present invention, which is to improve the mechanical strength and heat dissipation effect when mounting an electronic device, can be achieved.
〔実施例−１〕
以下、第１図〜第３図を介して本発明を適用した電子装
置の第１実施例を説明する。なお、第１図は樹脂モール
ド前の外部接続端子切断前の電子装置の構造を示す平面
図、第２図は一側面図、第３図は斜視図を示すものであ
る。[Example-1] Hereinafter, a first example of an electronic device to which the present invention is applied will be described with reference to FIGS. 1 to 3. Note that FIG. 1 is a plan view showing the structure of the electronic device before resin molding and before external connection terminals are cut, FIG. 2 is a side view, and FIG. 3 is a perspective view.
第１図に示すように、半導体チップ１上のソース、電極
及びゲート電極は各々が個別の金属細線１０．１０を介
して第１の外部接続端子２，３に接続されている。As shown in FIG. 1, the source, electrode, and gate electrodes on the semiconductor chip 1 are each connected to first external connection terminals 2, 3 via individual thin metal wires 10, 10.
ここで注目すべきは、本発明でいう第２の外部接続端子
４の形状である。外部接続端子４は、樹脂封止体６外部
において連結されており、上記第１の外部接続端子２．
３に対し表面積大の板状であり、その一部に開口部５が
形成されている。外部接続端子４の一部には、半導体チ
ップ１が導電可能に接着されている。半導体チップ１の
底面はドレインとなっているので、外部接続端子４は電
子装置のドレイン電極となるとともに放熱板ともなる。What should be noted here is the shape of the second external connection terminal 4 in the present invention. The external connection terminal 4 is connected to the outside of the resin sealing body 6, and is connected to the first external connection terminal 2.
It has a plate shape with a larger surface area compared to 3, and an opening 5 is formed in a part of the plate. A semiconductor chip 1 is electrically conductively bonded to a part of the external connection terminal 4. Since the bottom surface of the semiconductor chip 1 serves as a drain, the external connection terminal 4 serves as a drain electrode of the electronic device and also serves as a heat sink.
一点鎖線は、エポキシ系樹翰による樹脂モールド後のパ
ッケージ６の外形をしめすものであり、一部は上記開口
部５にかかつている。The one-dot chain line indicates the outer shape of the package 6 after resin molding with epoxy resin, and a part thereof extends over the opening 5.
外部接続端子４の上記形状によると、その横幅ＷＩが外
部接続端子２，３が固定されたときの横幅Ｗ、とほぼ同
一とし、表面積を大きくする。したがりて、動作中の半
導体チップ１から発生した熱は、外部接続端子４￥介し
て効率よく空気中に放熱される。According to the above-described shape of the external connection terminal 4, its width WI is approximately the same as the width W when the external connection terminals 2 and 3 are fixed, thereby increasing the surface area. Therefore, heat generated from the semiconductor chip 1 during operation is efficiently radiated into the air via the external connection terminals 4.
更に機械的強度についてみると、外部接続端子４は形状
大であるから容易に変形しない。そして樹脂封止後の外
部接続端子２，３．４を第１図に点線で示すＸ、Ｙ部分
で切断した状態を第２図および第３図に示すようにパッ
ケージ６がなされた場合、パッケージ６のパッケージ上
方６ａとパッケージ下部６ｂとは、第１図に示す外部接
続端子２．３．４の外周部Ａ、Ｂ更に間隙Ｃ１更に開口
部５において一体になされる。したがって、外部接続端
子２，３．４はモールド樹脂によって強固に挾まれてい
るため電子装置自体の耐湿性が向上されることになる。Furthermore, regarding mechanical strength, since the external connection terminal 4 has a large shape, it is not easily deformed. Then, when the package 6 is made as shown in FIGS. 2 and 3 by cutting the external connection terminals 2, 3.4 after resin sealing at the X and Y portions indicated by dotted lines in FIG. The upper part 6a of the package 6 and the lower part 6b of the package are integrated at the outer circumferences A and B of the external connection terminals 2.3.4, the gap C1, and the opening 5 shown in FIG. Therefore, since the external connection terminals 2, 3.4 are firmly sandwiched between the molded resin, the moisture resistance of the electronic device itself is improved.
ところで、外部接続端子２〜４は、＠２図および第３図
に示すように、パッケージ上部６ａとパッケージ下部６
ｂとの境界付近からパッケージ６外に突出し、ついで下
方に折り曲げられている。By the way, the external connection terminals 2 to 4 are connected to the upper part 6a of the package and the lower part 6a of the package, as shown in @2 and 3.
It protrudes out of the package 6 from near the boundary with b, and is then bent downward.
これは先端部においてプリント基板の回路パターン（何
れも図示せず）に半田付けするためである。This is because the tip portion is to be soldered to the circuit pattern (none of which is shown) on the printed circuit board.
したがりて、外部接続端子４の半田付は面積は、他の外
部接続端子２．３に比較して大きく、両者の接続が強固
になる。この結果、実装時の機械的強度が向上するとと
もに、半田付は不良等の事故を低減することもできる。Therefore, the soldering area of the external connection terminal 4 is larger than that of the other external connection terminals 2.3, and the connection between the two becomes stronger. As a result, mechanical strength during mounting is improved, and accidents such as soldering defects can be reduced.
尚、上記した面付は実装型電子装置はデュアルインライ
ン型ＩＣの外部接続端子を第１図の黒服で示すＸ、Ｙ部
分で切断し形成すると、デュアルインライン型から面付
実装型にパッケージ構造を容易に変更でき、実装の自動
化が達成できる。The above-mentioned surface mounting type electronic device can be formed by cutting the external connection terminals of the dual in-line IC at the X and Y portions shown in black in Figure 1, and the package structure changes from the dual in-line type to the surface mounting type. can be easily modified and automation of implementation can be achieved.
上記した実施例によって得られる効果を下記に示す＠
（１）を子装置の外部接続端子を表面積大の形状になし
、その一部に半導体チップを導電可能に接着することに
より、上記牛４体チップから発生した熱を上記表面積大
の外部接続端子を介して放電するという作用で、電子装
置の放熱効果が向上するという効果が得られる。The effects obtained by the above-mentioned embodiment are shown below. By discharging the heat generated from the chip through the external connection terminals having a large surface area, it is possible to improve the heat dissipation effect of the electronic device.
（２）電子装置の外部接続端子を表面積大の形状になし
、その一端を面付は実装することにより、回路パターン
との半田付は面積が拡大するという作用で、実装時の機
械的強度が向上する、という効果が得られる。(2) By making the external connection terminal of the electronic device into a shape with a large surface area and mounting one end with a surface, the area for soldering with the circuit pattern is expanded, which increases the mechanical strength during mounting. The effect is to improve.
（３）上記（２）により、半田付は不良等の不測の事故
が低減されるので、信頼性が向上する、という効果が得
られる。(3) According to the above (2), unexpected accidents such as soldering defects are reduced, so that reliability is improved.
（４）上記外部接続端子の一部に開口部を形成し、電子
装置のパッケージ材の一部がこの開口部を介して一体に
なされるように構成したことにより、上下パッケージの
結合度が大になるという作用で、電子装置自体の機械的
強度が向上する、という効果が得られる。(4) By forming an opening in a part of the external connection terminal and arranging a part of the packaging material of the electronic device to be integrated through this opening, the degree of coupling between the upper and lower packages is increased. This effect provides the effect of improving the mechanical strength of the electronic device itself.
〔実施例−２〕
次に、第４図および第５図を参照して本発明の第２実施
例を説明する。[Embodiment 2] Next, a second embodiment of the present invention will be described with reference to FIGS. 4 and 5.
なお、本実施例と上記ｗＫ１実施例との相違点は、各外
部接続端子の先端部を折り曲げて、面付は実装を容易に
したことにある。The difference between this embodiment and the wK1 embodiment described above is that the tip of each external connection terminal is bent to facilitate surface mounting.
先ず、第４図に示す構造から述べると、外部接続端子２
．３．４の先端部２ａ、３ａ、４ａが、図示のように互
いに外側方向に折り曲げられている。したがりて、先端
部２ａ〜４ａの下側面、換首すれば回路パターンとの接
触面積が拡大され、この分両者の半田付けが強固になる
。First, to describe the structure shown in FIG. 4, the external connection terminal 2
．． The tip portions 2a, 3a, 4a of 3.4 are bent outward from each other as shown. Therefore, by reversing the lower surfaces of the tips 2a to 4a, the area of contact with the circuit pattern is expanded, and the soldering between them becomes stronger.
第５図は外部接続端子の先端部２ａ〜４ａを互いに内側
方向に折り曲げたものである。この場合も先端ｓ２ａ〜
４ａの下側面の面積が大になり、回路パターンとの半田
付は面積が拡大される。FIG. 5 shows the external connection terminals with their tips 2a to 4a bent inwardly. In this case as well, the tip s2a~
The area of the lower surface of 4a is increased, and the area for soldering with the circuit pattern is expanded.
したがって、本実施例に示した電子装置の構造によれば
、上記第１実施例で述べた効果を奏するうえに、
（５）外部接続端子の先端部を折り曲げ、回路パターン
との接触面積を大にすることにより、実装時の半田付は
不良が低減される、という効果が得られる。Therefore, according to the structure of the electronic device shown in this embodiment, in addition to achieving the effects described in the first embodiment, (5) the tip of the external connection terminal is bent to increase the contact area with the circuit pattern. By doing so, it is possible to reduce the number of soldering defects during mounting.
（６）上記（５）により、実装時の機械的強度がより一
層増大する、という効果が得られる。(6) The above (5) provides the effect that the mechanical strength during mounting is further increased.
〔実施例−３〕
次に、第６図を参照して本発明の第３実施例を説明する
。[Embodiment 3] Next, a third embodiment of the present invention will be described with reference to FIG.
なお、本実施例は上記各実施例で述べた外部接続端子の
構造をスモールアウトライン（以下Ｓ。In this embodiment, the structure of the external connection terminal described in each of the above embodiments is referred to as a small outline (hereinafter referred to as "S").
Ｐ）型ＩＣに適用したものである。尚、ＳＯＰ型ＩＣｋ
！エポキシ系樹脂により形成された長方体のパッケージ
とこのパッケージの長手方向両側面から突出する複数の
外部接続端子からなっている。This is applied to P) type IC. In addition, SOP type ICk
! It consists of a rectangular parallelepiped package made of epoxy resin and a plurality of external connection terminals protruding from both longitudinal sides of the package.
第６図は本発明をこのＳＯＰ型ＩＣＫ適用したものであ
り、このＳＯＰ型ＩＣパッケージ１１は、パッケージ１
２の長手方向の両側面から外部接続端子１３．１４が突
出している。外部接続端子１４は放熱効果を有しており
、上記実施例で述べた外部接続端子４に相当するもので
あり、パッケージ６内において半導体チップが固定され
るタグと連結している。FIG. 6 shows an application of the present invention to this SOP type ICK, and this SOP type IC package 11 is similar to package 1.
External connection terminals 13 and 14 protrude from both longitudinal sides of 2. The external connection terminal 14 has a heat dissipation effect, corresponds to the external connection terminal 4 described in the above embodiment, and is connected to a tag to which a semiconductor chip is fixed within the package 6.
外部接続端子１４は、外部接続端子１３のたとえば２本
分を一体にしたものである。この構造によると、両者の
結合部分があるので、外部接続端子１４０表面積は他の
外部接続端子１３の表面積と比較して２倍以上になる。The external connection terminal 14 is made by integrating, for example, two of the external connection terminals 13. According to this structure, since there is a connecting portion between the two, the surface area of the external connection terminal 140 is more than twice that of the other external connection terminals 13.
また、外部接続端子１３．１４の先端部はそれぞれ外側
方向に折り曲げられているので、回路パターンとの接触
面積が拡大される。Moreover, since the tips of the external connection terminals 13 and 14 are each bent outward, the area of contact with the circuit pattern is expanded.
したがって本実施例に示す電子装置は、上記各実施例で
述べた効果を奏するうえに、
（力 ＳＯＰ型ＩＣの外部接続端子のうち複数の外部接
続端子を一体になし、半導体チップの放熱をおこなわし
めることＫより、ＳＯＰ型ＩＣの放熱効果を向上させる
、という効果が得られる。Therefore, the electronic device shown in this embodiment not only achieves the effects described in each of the above embodiments, but also integrates a plurality of external connection terminals among the external connection terminals of an SOP type IC to dissipate heat from the semiconductor chip. The effect of improving the heat dissipation effect of the SOP type IC can be obtained by using Shimekoto K.
以上に、本発明者によってなされた発明を実施例にもと
づき具体的に説明したが、本発明は上記実施例に限定さ
れるものではな（、その要旨を逸脱しない範囲で種々変
形可能であることはいうまでもない。たとえば、第３実
施例で示した外部接続端子１４は必要に応じて形状を更
に大にしてもよい。Although the invention made by the present inventor has been specifically explained based on examples above, the present invention is not limited to the above examples (and may be modified in various ways without departing from the gist of the invention). Needless to say, for example, the shape of the external connection terminal 14 shown in the third embodiment may be made larger as necessary.
以上の説明では、主として不発明者等によってなされた
発明をその背景となった利用分野であるＭＯＳ）ランジ
スタ、デュアルインライン型ＩＣ等の電子装置に適用し
た場合について説明したが、それに限定されるものでは
なく、他の面付は実施型ＩＣに広く利用することができ
る。In the above explanation, we have mainly explained the case where the invention made by a non-inventor etc. is applied to electronic devices such as MOS transistors, dual in-line ICs, etc., which is the field of application that formed the background of the invention, but the invention is not limited to this. However, other impositions can be widely used in integrated ICs.
本発明は少なくとも、外部接続端子が連結している電子
装置に利用できる。The present invention can be used at least for electronic devices connected to external connection terminals.
本願において開示される発明のうち代表的なものＫよっ
て得られる効果を簡単に説明すれば、下記のとおりであ
る。A brief explanation of the effects obtained by representative invention K among the inventions disclosed in this application is as follows.
すなわち、電子装置の外部接続端子のうち少なくとも半
導体チップに導電可能に接続された外部接続端子を封止
体外部で連結して、形状大として機械的強度を増大せし
めるとともに、表面積を大にして放熱効果を向上せしめ
るように構成したので、ＩＣ，トランジスタの如き電子
装置の実装時の機械的強度と放熱効果とが向上する、と
いう効果が得られる。In other words, at least the external connection terminals of the electronic device that are electrically conductively connected to the semiconductor chip are connected outside the sealing body to increase the mechanical strength by increasing the shape and increasing the surface area to dissipate heat. Since the structure is configured to improve the effect, it is possible to obtain the effect that the mechanical strength and heat dissipation effect are improved when electronic devices such as ICs and transistors are mounted.
第１図〜＠３図は本発明を適用した電子装置の第１実施
例を示すものであり、
第１図は電子装置の構造を示す平面図、第２図は上記電
子装置の外形を示す一側面図、第３図は上記電子装置の
外形を示す斜視図、第４図および第５図は本発明の第２
実施例を示すものであり、
第４図は外部接続端子の折り曲げの一例を示す斜視図、
第５図は外部接続端子の折り曲げの他の例を示す斜視図
、
第６図は本発明の第３実施例を示すＳＯＰ型ＩＣの斜視
図である。
１・・・半導体チップ、２，３，４，１３．１４・・・
外部接続端子、５・・・開口部、６・・・パッケージ、
１１・・・デュアルインライン匿パッケージ。
第 １ 図
第 ２ 図
Ｘ７γ−外系跡【罎輻Ｊ切絣部
第 ４ 図
第 ５ 図
σFigures 1 to 3 show a first embodiment of an electronic device to which the present invention is applied. Figure 1 is a plan view showing the structure of the electronic device, and Figure 2 shows the external shape of the electronic device. One side view, FIG. 3 is a perspective view showing the external shape of the electronic device, and FIGS. 4 and 5 are second views of the electronic device of the present invention.
FIG. 4 is a perspective view showing an example of bending the external connection terminal, FIG. 5 is a perspective view showing another example of bending the external connection terminal, and FIG. 6 is a perspective view showing another example of bending the external connection terminal. FIG. 3 is a perspective view of an SOP type IC showing a third embodiment. 1... semiconductor chip, 2, 3, 4, 13.14...
External connection terminal, 5... opening, 6... package,
11...Dual inline concealed package. Fig. 1 Fig. 2 Fig.
Claims (4)
の外部接続端子と、(2) A first terminal connected to a predetermined terminal of the semiconductor chip.
external connection terminal and
なされるとともに、一部に開口部 が形成され、かつ板状部の一部に導電可能 に接着される上記半導体チップの放熱と外 部接続用端子とを兼ねる第２の外部接続端 子と、(3) Heat dissipation of the semiconductor chip, which is made into a plate shape with a large surface area relative to the first external connection terminal, has an opening formed in a part, and is electrically conductively bonded to a part of the plate part. and a second external connection terminal that also serves as an external connection terminal;
続端子の外周部、ならびに上記第 １および第２の外部接続端子の間に形成さ れる空隙において一体になされるパッケー ジ材と、 を具備し、前記第１，第２の外部接続端子は面付け実装
可能に加工が施されているとともに、前記第２の外部接
続端子はパッケージ材外部で連結していることを特徴と
する電子装置。(4) a packaging material formed integrally with the connection opening, the outer periphery of the first and second external connection terminals, and the gap formed between the first and second external connection terminals; The electronic device is characterized in that the first and second external connection terminals are processed to be surface-mountable, and the second external connection terminal is connected to each other outside the package material. Device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61048398A JPS62206868A (en) | 1986-03-07 | 1986-03-07 | Electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61048398A JPS62206868A (en) | 1986-03-07 | 1986-03-07 | Electronic device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62206868A true JPS62206868A (en) | 1987-09-11 |
Family
ID=12802194
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61048398A Pending JPS62206868A (en) | 1986-03-07 | 1986-03-07 | Electronic device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62206868A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04225268A (en) * | 1990-12-26 | 1992-08-14 | Toshiba Corp | Semiconductor device |
| JPH0629153U (en) * | 1992-09-17 | 1994-04-15 | アイワ株式会社 | Electronic parts |
| US6165818A (en) * | 1997-05-21 | 2000-12-26 | Nec Corporation | Method of manufacturing a semiconductor device with a pair of radiating terminals and a plurality of lead terminals formed from a single lead frame |
| JP2009158794A (en) * | 2007-12-27 | 2009-07-16 | Toyoda Gosei Co Ltd | Light emitting device |
-
1986
- 1986-03-07 JP JP61048398A patent/JPS62206868A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04225268A (en) * | 1990-12-26 | 1992-08-14 | Toshiba Corp | Semiconductor device |
| JPH0629153U (en) * | 1992-09-17 | 1994-04-15 | アイワ株式会社 | Electronic parts |
| US6165818A (en) * | 1997-05-21 | 2000-12-26 | Nec Corporation | Method of manufacturing a semiconductor device with a pair of radiating terminals and a plurality of lead terminals formed from a single lead frame |
| JP2009158794A (en) * | 2007-12-27 | 2009-07-16 | Toyoda Gosei Co Ltd | Light emitting device |
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