JPS6217382B2 - - Google Patents

Info

Publication number
JPS6217382B2
JPS6217382B2 JP54013358A JP1335879A JPS6217382B2 JP S6217382 B2 JPS6217382 B2 JP S6217382B2 JP 54013358 A JP54013358 A JP 54013358A JP 1335879 A JP1335879 A JP 1335879A JP S6217382 B2 JPS6217382 B2 JP S6217382B2
Authority
JP
Japan
Prior art keywords
tab
lead
leads
heat
tips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54013358A
Other languages
Japanese (ja)
Other versions
JPS55107251A (en
Inventor
Susumu Okikawa
Fumihito Inoe
Takehiko Yanagida
Kazuo Shimizu
Keizo Ootsuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1335879A priority Critical patent/JPS55107251A/en
Publication of JPS55107251A publication Critical patent/JPS55107251A/en
Publication of JPS6217382B2 publication Critical patent/JPS6217382B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】 本発明は民生用IC、リニアIC等のレジンモー
ルド型の小型電子部品など、集積回路装置の実装
構造に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a mounting structure of an integrated circuit device such as a resin molded small electronic component such as a consumer IC or a linear IC.

民生用IC、リニアIC等の小信号用IC等のパツ
ケージとしてレジンモールドパツケージが製造コ
ストが安価であることなどから一般に多く採用さ
れている。
Resin molded packages are commonly used as packages for small-signal ICs such as consumer ICs and linear ICs due to their low manufacturing costs.

ここで、従来一般に多用されているレジンモー
ルドパツケージのICの製造方法およびその製造
について第1図および第2図を用いて説明する。
Here, a method for manufacturing an IC in a resin mold package, which has been commonly used in the past, and its manufacturing will be explained with reference to FIGS. 1 and 2.

レジンモールド型半導体装置の組立には鉄―コ
バルト―ニツケル合金などの鉄系材料からなる金
属薄板を精密プレスやエツチングによつてパター
ン化したデユアルインライン形のリードフレーム
が用いられている。このリードフレームは第1図
に示すような構成部分からなつている。すなわ
ち、リードのフレームである外枠1と、この外枠
1の中心部に位置する回路素子2を取り付ける小
片からなるタブ3と、このタブ3を外枠1に連結
する細いタブリード4と、外枠1の各辺の内側か
らタブ3に向かつて延びる複数のリード5と、こ
れらリード5を連結し、モールド時のレジンの流
出を防止する細に連結片からなるダム6とからな
つている。そして、半導体装置の組立にあつて
は、タブ3上に回路素子2を固定した後、この回
路素子2の各電極とこれに対応するリード5の先
端とを細いワイヤ7で接続し、その後、ダム6に
囲まれる鎖線枠内をレジンでモールドするととも
にリード5を切断して外枠1から分離し、不要と
なつたダム6を切断除去する。また、タブリード
4はレジンからなるモールド部8の付け根(チヨ
コレートブレーク4aが施こしてある)で切断除
去される(第2図は完成品を示す。)。
Dual in-line lead frames are used to assemble resin molded semiconductor devices, which are patterned thin metal plates made of iron-based materials such as iron-cobalt-nickel alloys by precision pressing or etching. This lead frame is made up of components as shown in FIG. That is, an outer frame 1 that is the frame of the lead, a tab 3 consisting of a small piece to which the circuit element 2 is attached located at the center of the outer frame 1, a thin tab lead 4 that connects this tab 3 to the outer frame 1, and an outer frame 1. It consists of a plurality of leads 5 extending from the inside of each side of the frame 1 toward the tab 3, and a dam 6 consisting of a thin connecting piece that connects these leads 5 and prevents the resin from flowing out during molding. When assembling the semiconductor device, after fixing the circuit element 2 on the tab 3, each electrode of the circuit element 2 and the tip of the corresponding lead 5 are connected with a thin wire 7, and then, The inside of the chain line frame surrounded by the dam 6 is molded with resin, the leads 5 are cut and separated from the outer frame 1, and the unnecessary dam 6 is cut and removed. Further, the tab lead 4 is cut and removed at the base of the mold part 8 made of resin (where a cross-cut break 4a is applied) (FIG. 2 shows the finished product).

一方、電子部品を組み込む装置の小型化の要請
からそのパツケージの小型化が進められている。
たとえば、28本のリード(外部端子)を有するリ
ニアICが縦40mm、横13mm、高さ4mmであつたも
のが最近では縦横10mm、高さ2mmのものが考えら
れつつある。
On the other hand, due to the demand for miniaturization of devices into which electronic components are installed, the miniaturization of such packages is progressing.
For example, a linear IC with 28 leads (external terminals) that used to be 40 mm long, 13 mm wide, and 4 mm high is now being considered to be 10 mm long, 10 mm wide, and 2 mm high.

他方、リニアICでも高密度実装が進められパ
ツケージ外形の小型化が要請されリニアIC等の
小信号ICでも高集積化が進み、回路素子の発熱
量が多いものが多くなつてきており、小信号IC
でも放熱効果について充分配慮しなければならな
くなつてきているが、上述したような考え方では
小型化が極めて困難である。
On the other hand, high-density packaging is progressing in linear ICs, and there is a demand for smaller package outlines, and small-signal ICs such as linear ICs are also becoming more highly integrated. I C
However, it is becoming necessary to give sufficient consideration to the heat dissipation effect, but miniaturization is extremely difficult with the above-mentioned approach.

すなわち、前述のようにしてパツケージの小型
化をはかつても、パツケージの全表面積は極端に
減少(たとえば、従前の例では1/5に減少す
る)することから、最近のレジンモールド型の小
型パツケージは採用できにくくなつてきていて、
組立が煩瑣ではあるが放熱効果の良好なセラミツ
クパツケージ構造に変更したり、あるいは従来の
大型パツケージを採用しなければならなくなり、
発熱量の比較的多い小信号ICの小型化はむずか
しいのが現状である。
In other words, even though packages have been miniaturized as described above, the total surface area of the package has been drastically reduced (for example, it has been reduced to 1/5 in the previous example). It is becoming difficult to hire
It was necessary to change to a ceramic package structure, which is complicated to assemble but has good heat dissipation, or to adopt a conventional large package structure.
Currently, it is difficult to miniaturize small-signal ICs that generate a relatively large amount of heat.

したがつて、本発明の目的は発熱量の多い小信
号用IC等の電子部品にあつて、低コストでかつ
小型のものでしかも熱的特性の良好なものなどを
提供せんとすることにある。
Therefore, an object of the present invention is to provide electronic components such as small-signal ICs that generate a large amount of heat at low cost, are compact, and have good thermal characteristics. .

このような目的を達成するために本発明の一実
施例は、回路素子すなわち、集積回路ペレツトを
取り付けるタブを支持するタブリードを封止体外
に突出させるとともに、その先端を熱伝導率の大
きい、たとえばセラミツク板のような配線基板に
接続したり、あるいは放熱体に固定するものであ
つて、以下実施例により本発明を説明する。
In order to achieve such an object, an embodiment of the present invention has a tab lead that supports a circuit element, that is, a tab on which an integrated circuit pellet is attached, protrudes outside the sealing body, and its tip is made of a material having high thermal conductivity, for example. The present invention is connected to a wiring board such as a ceramic board or fixed to a heat sink, and the present invention will be explained below with reference to Examples.

第3図は本発明の一実施例によるIC(半導体
装置)を示す。同図において、9はタブ10と連
結しているタブリード、11はタブ10上に取り
付けられた回路素子であるICチツプ、12はリ
ード、13はリード12の内端と回路素子11の
外部電極を繋ぐワイヤである。また、リード12
の外端部を除くタブ10、回路素子11、ワイヤ
13、リード内端部は全体をレジンからなるモー
ルド部(封止体)14で被われている。また、各
リード12は第4図a,bに示すように同一方向
に折り曲げられるとともにその先端部は再度折り
曲げられてフラツトな接合端15に形作られてい
る。さらに、タブリード9もその外端をモールド
部14から突出させている。なお、第3図におけ
るタブリードの外端はモールド部14の側面から
真直横方向に延びている。また、モールド部14
内のタブリード9はモールド縁からタブ10まで
の距離が最も短かくなるようにモールド部14の
側面に対して垂直となる方向に延びている。
FIG. 3 shows an IC (semiconductor device) according to an embodiment of the present invention. In the figure, 9 is a tab lead connected to the tab 10, 11 is an IC chip that is a circuit element mounted on the tab 10, 12 is a lead, and 13 is a connection between the inner end of the lead 12 and the external electrode of the circuit element 11. It is a connecting wire. Also, lead 12
The tab 10, the circuit element 11, the wire 13, and the inner end of the lead, except for the outer end thereof, are entirely covered with a molded part (sealing body) 14 made of resin. Further, each lead 12 is bent in the same direction as shown in FIGS. 4a and 4b, and its tip is bent again to form a flat joint end 15. Furthermore, the tab lead 9 also has its outer end protruding from the mold part 14. Note that the outer end of the tab lead in FIG. 3 extends straight from the side surface of the molded portion 14 in the lateral direction. In addition, the mold part 14
The inner tab lead 9 extends in a direction perpendicular to the side surface of the mold part 14 so that the distance from the mold edge to the tab 10 is the shortest.

つぎに、第4図a,bを参考にして前記ICの
実装構造について説明する。同図aはIC16を
セラミツク基板17に取り付ける際の状態を示す
ものであつて、リード12の外端はセラミツク基
板17の図示しない配線層に半田(図示せず)を
介して固定される。また、セラミツクのような熱
伝導率のよい基板17に取り付ける際には、タブ
リード9の外端は下方に折り曲げられて基板17
に半田(図示せず)を介して固定される。
Next, the mounting structure of the IC will be explained with reference to FIGS. 4a and 4b. FIG. 1A shows a state in which the IC 16 is attached to a ceramic substrate 17, and the outer ends of the leads 12 are fixed to a wiring layer (not shown) of the ceramic substrate 17 via solder (not shown). Further, when attaching to a substrate 17 having good thermal conductivity such as ceramic, the outer end of the tab lead 9 is bent downward and the tab lead 9 is bent downward.
It is fixed to via solder (not shown).

また、同図bで示すように、IC16をガラス
エポキシのように熱伝導率の低い基板18に取り
付ける際には、放熱性を高めるために特別な手段
を講じ、タブリード9はその外端部をモールド部
14の上方に折り曲げ、熱伝導率の良好な放熱板
19(たとえば銅、アルミニウム等からなる板あ
るいは放熱フイン)に半田(図示せず)を介して
固定される。
In addition, as shown in FIG. It is bent above the molded part 14 and fixed to a heat sink 19 having good thermal conductivity (for example, a plate made of copper, aluminum, etc. or a heat sink fin) via solder (not shown).

このように、発熱源となる回路素子11を支持
するタブリード9の外端は熱伝導率が高い放熱板
の役割を果すセラミツク基板17や放熱板19に
連結されるため、熱はタブリード9を介して放熱
板から順次放熱される。また、タブリードの長さ
(経路)は短かいため、伝熱経路も短かくなり放
熱効果も高い。この実装構造、すなわち、タブリ
ード2本がセラミツク板に固定される本実施例は
タブリードがセラミツク板に接触しない場合に較
べて遥かに熱抵抗が低くなる(第7図参照)。す
なわち、パツケージ単体ではモールド部が小型に
なつたこともあつて熱抵抗はたとえば216℃/W
と大きいが、セラミツク基板のように熱伝導率の
良い実装基板に取り付けた状態では小型パツケー
ジの方が大型パツケージよりも熱抵抗が小さくな
る。この場合、リードフレームは銅で作られてい
る。なお、ガラスエポキシのように熱伝導率の低
い基板では熱抵抗が大きくて使用できないのは第
7図のグラフでも明らかであることから第4図b
のようにタブリードを銅等の放熱板に固定する必
要がある。
In this way, the outer end of the tab lead 9 that supports the circuit element 11 that is a heat source is connected to the ceramic substrate 17 and the heat sink 19 that serve as heat sinks with high thermal conductivity, so that heat is transferred through the tab lead 9. The heat is radiated sequentially from the heat sink. Furthermore, since the length (path) of the tab lead is short, the heat transfer path is also short and the heat dissipation effect is high. This mounting structure, that is, this embodiment in which two tab leads are fixed to the ceramic plate, has a much lower thermal resistance than the case where the tab leads do not contact the ceramic plate (see FIG. 7). In other words, the thermal resistance of the package itself is, for example, 216°C/W, partly because the mold part has become smaller.
However, when attached to a mounting board with good thermal conductivity such as a ceramic board, a small package has a lower thermal resistance than a large package. In this case, the lead frame is made of copper. Note that it is clear from the graph in Figure 7 that a substrate with low thermal conductivity such as glass epoxy cannot be used due to its large thermal resistance, so Figure 4b
It is necessary to fix the tab lead to a heat sink made of copper or the like, as shown in the figure below.

したがつて、本実施例のようにすればパツケー
ジ(モールド部)が10mm□以下に小型化されても
放熱特性は良好となることから、比較的熱を発生
する民生用ICやリニアICなどの小型化可能とな
る。
Therefore, if this example is used, the heat dissipation characteristics will be good even if the package (mold part) is downsized to 10 mm or less, so it is suitable for consumer ICs, linear ICs, etc. that generate relatively heat. It becomes possible to downsize.

なお、本発明は前記実施例に限定されない。ま
た、リードフレームの材質を銅のような熱伝導率
が高いものを用いればさらに放熱効果が増大す
る。
Note that the present invention is not limited to the above embodiments. Furthermore, if a material with high thermal conductivity such as copper is used for the lead frame, the heat dissipation effect will be further increased.

また、第5図に示すように、リード12および
タブリード9の外端を直接セラミツク基板17に
接触させるようにして半田20で固定する構造を
採用すれば、取付面積が狭くなる。また、モール
ド部14の外縁からリード12およびタブリード
9の屈曲部までの距離lをできるだけ短かくし、
リード12およびタブリード9の高さHも低くす
ることによつて伝熱経路も短かくなるのでさらに
放熱特性が向上する。
Furthermore, as shown in FIG. 5, if a structure is adopted in which the outer ends of the leads 12 and tab leads 9 are brought into direct contact with the ceramic substrate 17 and fixed with solder 20, the mounting area becomes narrower. In addition, the distance l from the outer edge of the mold part 14 to the bending part of the lead 12 and tab lead 9 is made as short as possible,
By reducing the height H of the leads 12 and tab leads 9, the heat transfer path is also shortened, and the heat dissipation characteristics are further improved.

また、第6図a,bに示すようにモールド部1
4から突出するタブリード9の幅を広くしたり、
第6図c,dに示すようにタブリード9の本数を
多くすることによつて伝熱(放熱)効果を増大さ
せるようにしてもよい。
Moreover, as shown in FIGS. 6a and 6b, the mold part 1
Wider the tab lead 9 protruding from 4,
As shown in FIGS. 6c and 6d, the heat transfer (heat radiation) effect may be increased by increasing the number of tab leads 9.

以上のように、本発明によれば、比較的発熱量
の多い小信号ICであつても小型化を図ることが
できる。
As described above, according to the present invention, even a small signal IC that generates a relatively large amount of heat can be miniaturized.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のリードフレームによるICの組
立例を示す平面図、第2図は同じくICの正面
図、第3図は本発明の一実施例によるICの平面
図、第4図a,bは同じく実装構造を示す正面
図、第5図は他の実装構造を示す一部断面正面
図、第6図a〜dは本発明の一実施例に用いるリ
ードフレームの一部を示す平面図、第7図は基板
熱伝導率と熱抵抗との関係を示すグラフである。 9…タブリード、10…タブ、11…回路素
子、12…リード、13…ワイヤ、14…モール
ド部、15…接合端、16…IC、17…セラミ
ツク基板、18…プリント基板、19…放熱板、
20…半田。
Fig. 1 is a plan view showing an example of assembling an IC using a conventional lead frame, Fig. 2 is a front view of the IC, Fig. 3 is a plan view of an IC according to an embodiment of the present invention, and Figs. 4 a and b. 5 is a partially sectional front view showing another mounting structure, and FIGS. 6 a to 6 d are plan views showing a part of a lead frame used in an embodiment of the present invention. FIG. 7 is a graph showing the relationship between substrate thermal conductivity and thermal resistance. 9...Tab lead, 10...Tab, 11...Circuit element, 12...Lead, 13...Wire, 14...Mold part, 15...Joining end, 16...IC, 17...Ceramic board, 18...Printed circuit board, 19...Radiation plate,
20...Solder.

Claims (1)

【特許請求の範囲】 1 (a) タブと、このタブに連接し、互いに反対
方向に延びる一対のリードと、タブ近傍にその
一端がのぞみ、他端が四方向に延びる複数の他
のリード群とをもつリード部材と、 (b) 前記タブ上に固定されたチツプと、 (c) 前記チツプ、タブ、タブに連接するリードお
よび複数の他のリード群の一部を封止するほぼ
正方形のレジン封止体とを有し、前記タブに連
接するリードの一部を前記レジン封止体の外に
位置せしめてなる電子部品を配線基板に実装し
たときの実装構造であつて、前記タブに連接す
るリードの先端は前記複数の他のリード群のリ
ード先端とは反対方向に折り曲げられて放熱板
に接続され、前記複数の他のリード群のリード
先端は配線基板に設けられた導体層に接続され
てなる電子部品の実装構造。
[Claims] 1 (a) A tab, a pair of leads connected to the tab and extending in opposite directions, and a group of other leads with one end extending in the vicinity of the tab and the other end extending in four directions. (b) a chip fixed on the tab; (c) a substantially square lead member that seals the chip, the tab, the lead connected to the tab, and a portion of a plurality of other lead groups; A mounting structure when an electronic component is mounted on a wiring board, the electronic component having a resin sealing body and having a part of the lead connected to the tab located outside the resin sealing body, The tips of the connected leads are bent in the opposite direction to the lead tips of the plurality of other lead groups and connected to the heat sink, and the lead tips of the plurality of other lead groups are connected to the conductor layer provided on the wiring board. Mounting structure of connected electronic components.
JP1335879A 1979-02-09 1979-02-09 Electronic part and its packaging construction Granted JPS55107251A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1335879A JPS55107251A (en) 1979-02-09 1979-02-09 Electronic part and its packaging construction

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1335879A JPS55107251A (en) 1979-02-09 1979-02-09 Electronic part and its packaging construction

Publications (2)

Publication Number Publication Date
JPS55107251A JPS55107251A (en) 1980-08-16
JPS6217382B2 true JPS6217382B2 (en) 1987-04-17

Family

ID=11830868

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1335879A Granted JPS55107251A (en) 1979-02-09 1979-02-09 Electronic part and its packaging construction

Country Status (1)

Country Link
JP (1) JPS55107251A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0773122B2 (en) * 1983-12-27 1995-08-02 株式会社東芝 Sealed semiconductor device
JPH0714021B2 (en) * 1983-12-27 1995-02-15 株式会社東芝 Resin-sealed semiconductor device
US4862246A (en) * 1984-09-26 1989-08-29 Hitachi, Ltd. Semiconductor device lead frame with etched through holes
JPH02260450A (en) * 1989-03-30 1990-10-23 Mitsubishi Electric Corp Semiconductor device and its mounting

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4421066Y1 (en) * 1966-07-20 1969-09-08
JPS4964373A (en) * 1972-06-23 1974-06-21
JPS5145977A (en) * 1974-10-17 1976-04-19 Nippon Electric Co JUSHIFUSHIGATAHANDOTAISOCHI

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4421066Y1 (en) * 1966-07-20 1969-09-08
JPS4964373A (en) * 1972-06-23 1974-06-21
JPS5145977A (en) * 1974-10-17 1976-04-19 Nippon Electric Co JUSHIFUSHIGATAHANDOTAISOCHI

Also Published As

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