JPS61168926A - Resin substrate - Google Patents
Resin substrateInfo
- Publication number
- JPS61168926A JPS61168926A JP60009013A JP901385A JPS61168926A JP S61168926 A JPS61168926 A JP S61168926A JP 60009013 A JP60009013 A JP 60009013A JP 901385 A JP901385 A JP 901385A JP S61168926 A JPS61168926 A JP S61168926A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- resin substrate
- lead wires
- substrate
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structure Of Printed Boards (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は樹脂基板に関し、特に、半導体装置の実装に好
適な樹脂基板に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a resin substrate, and particularly to a resin substrate suitable for mounting semiconductor devices.
半導体素子の実装にセラミック基板が広く使用されてい
る。特に、半導体装置に信頼性が重視されるもの罠つい
てはセラミック基板によって〜・る。Ceramic substrates are widely used for mounting semiconductor devices. In particular, ceramic substrates are used for semiconductor devices where reliability is important.
セラミック基板を使用した半導体パッケージにいわゆる
ビングリッドプレイタイプのパッケージがある。これは
、セラミック基板の裏面から垂直方向く多数のビンを立
設したもので、セラミック基板が高価であること、ビン
を立設する工程を要するなどその構造上（製法上）極め
℃高価なものにつぎ、さらＫ、セラミック基板上圧搭載
された半導体素子と上記ビンとをワイヤボンディングに
より電気的に接続するため罠は、当該ビンから。There is a so-called bin lid play type package as a semiconductor package using a ceramic substrate. This is a product in which a large number of bottles are set up vertically from the back side of a ceramic substrate, which is extremely expensive due to its structure (manufacturing method), as the ceramic substrate is expensive and the process of setting up the bottles upright is required. Next, in order to electrically connect the semiconductor element mounted on the ceramic substrate with the above-mentioned bottle by wire bonding, a trap is removed from the above-mentioned bottle.
導体配線層を、セラミック基板中に、Ｉ！＃に設げねば
ならなかった。A conductor wiring layer is placed in a ceramic substrate, I! It had to be set in #.
一方、セラミックタイプの半導体バクケージの一つとし
℃パッドグリッドアレイタイプのパッケージがある。こ
れは基板底面にパッドと称されるメタライズ層を設け、
半田付けによる実装基板へ平面付けするタイプのもので
あるが、このものも前記ピングリットアレイタイプのも
のと同様にその構造上（製法上）極めて高価であり、か
つ、ワイヤボンディングするためにバッドから導体配線
層を設ける必要があった。On the other hand, there is a ℃ pad grid array type package as one type of ceramic type semiconductor package. This is done by providing a metallized layer called a pad on the bottom of the substrate.
This is a type that is flat-attached to a mounting board by soldering, but like the pin-grid array type mentioned above, this type is also extremely expensive due to its structure (manufacturing method), and it requires wire bonding from the pad. It was necessary to provide a conductor wiring layer.
本発明の目的は、かかる従来技術の有する欠点を解消し
、その構造上も製法上も安価なものとすることができ、
かつ、殊更に、導体配線層を設ける必要のない樹脂基板
を提供すること罠ある。The purpose of the present invention is to eliminate the drawbacks of the prior art, and to make it inexpensive in terms of structure and manufacturing method.
In addition, it is particularly desirable to provide a resin substrate that does not require a conductor wiring layer.
本発明の他の目的は、ピングリットアレイのごとく、殊
更にビンを立設する必要のない、樹脂基板を提供するこ
とを目的とする。Another object of the present invention is to provide a resin substrate that does not require any vertical arrangement of bottles, such as in a pin grid array.
本発明のさらに他の目的は、熱放散の良好な樹脂基板を
提供することにある。Still another object of the present invention is to provide a resin substrate with good heat dissipation.
本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.
本願に？いて開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。For the main purpose? A brief overview of typical inventions disclosed in the patent is as follows.
すなわち、本発明は板状の樹脂体中に適宜のピッチ、配
列で任意の太さのリードワイヤを垂直方向に埋込むこと
罠より、殊更に、ビンを立設する必要がなく、また、殊
更にワイヤボンディングのために導体配線層を設ける必
要がなく、その構造上、製法上も安価なものとなり、さ
らに、樹脂中に金属製のリードワイヤが埋込まれている
ので放熱特性も良く、信頼性の向上を図ることができる
。That is, the present invention eliminates the need for vertically embedding lead wires of any thickness at appropriate pitches and arrangements in a plate-shaped resin body, and particularly eliminates the need for vertically erecting bins. There is no need to provide a conductor wiring layer for wire bonding, making the structure and manufacturing method cheaper.Furthermore, since the metal lead wire is embedded in the resin, it has good heat dissipation characteristics and is reliable. It is possible to improve sexual performance.
次に、本発明の実施例を図面に基づいて説明する。 Next, embodiments of the present invention will be described based on the drawings.
第１図は本発明の樹脂基板の一例を示す斜視図。FIG. 1 is a perspective view showing an example of a resin substrate of the present invention.
第２図は第１図１−１線に沿う断面の一例図、第３図は
第２図■−■線に沿う断面の一例図、第４図は本発明樹
脂基板の製法の一例を示す説明図、第５図は本発明の樹
脂基板を用いた半導体装置の一例断面図である。Fig. 2 is an example of a cross section taken along the line 1-1 in Fig. 1, Fig. 3 is an example of a cross section taken along the line ■-■ in Fig. 2, and Fig. 4 is an example of the manufacturing method of the resin substrate of the present invention. The explanatory diagram, FIG. 5, is a cross-sectional view of an example of a semiconductor device using the resin substrate of the present invention.
これら図に示すよう罠、樹脂体１中に、リードワイヤ２
を適宜のピッチ、配列で埋込みする。As shown in these figures, the trap has a lead wire 2 inside the resin body 1.
Embed with appropriate pitch and arrangement.
樹脂体ｌは、熱可塑性合成樹脂や熱硬化性合成樹脂など
により構成され１例えばエポキシ樹脂。The resin body 1 is made of thermoplastic synthetic resin, thermosetting synthetic resin, etc. 1, for example, epoxy resin.
ガラスエポキシ樹脂により構成される。Constructed from glass epoxy resin.
リードワイヤ２は、例えばワイヤボンディングに使用さ
れているＡｆ線やリードフレーム材料とし１使用され又
いるコバール合金（Ｆｅ−Ｎｉ系合金）ＪＰ銅又は銅系
合金により構成される。The lead wire 2 is made of, for example, Af wire used in wire bonding, Kovar alloy (Fe-Ni alloy) JP copper, or copper alloy used as a lead frame material.
リードワイヤ２は適宜の太さのものを使用する。The lead wire 2 used has an appropriate thickness.
均一の太さのものであっ工もよいし、各リードのワイヤ
２・・・の各太さを適宜変えてもよい。The wires 2 may have a uniform thickness, or the thickness of the wires 2 of each lead may be changed as appropriate.
樹脂体ｌ中にリードワイヤ２が埋込まれた樹脂基板３は
、各種の方法により成形でき、例えば任意の外形、任意
の厚さを有する樹脂体１に穴を穿設し、当該穴内にリー
ドワイヤ２を固着させること罠より得ることができるし
、また、複数本のリードワイヤ２な型中罠立設しておぎ
、当該型内に樹脂を流し込み、硬化させることにより得
ることができるが、第４図に示すような多心ケーブルの
合成樹脂くよる押出し被覆方法を採用するとよい。The resin substrate 3 in which the lead wires 2 are embedded in the resin body 1 can be molded by various methods. For example, a hole having an arbitrary external shape and an arbitrary thickness is bored in the resin body 1, and the leads are inserted into the hole. It can be obtained by fixing the wire 2 in a trap, or it can be obtained by setting up a trap in a mold with a plurality of lead wires 2, pouring resin into the mold, and curing it. It is preferable to adopt an extrusion coating method using synthetic resin for multi-core cables as shown in FIG.
例えば、押出機のクロスへラドダイ４に矢標５方向から
、リードワイヤ２を供給し、ホッパー６から、矢標７で
示すよう罠、樹脂体１を構成する樹脂を供給し、樹脂体
１中にリードワイヤ２が埋込みされたものを矢標８力向
に押出し、当該埋込物を、適宜の長さに切断することに
より、第３図や第２図に示す断面の樹脂基板３を得るこ
とができる。For example, the lead wire 2 is supplied to the cross of the extruder from the arrow 5 direction to the rad die 4, and the resin constituting the resin body 1 is supplied from the hopper 6 as shown by the arrow 7. A resin substrate 3 having a cross section shown in FIGS. 3 and 2 is obtained by extruding the lead wire 2 embedded therein in the direction of arrow 8 and cutting the embedded object into an appropriate length. be able to.
この樹脂基板３に、第５図に示すように、接着剤９によ
り、半導体素子１０を搭載し、該素子ｌＯのパッド（図
示せずンと樹脂基板３のリードワイヤ２の一端部とをコ
ネクタワイヤ１１によりワイヤボンディングし、樹脂基
板３上に接着剤１２によりキャップ１３を取付けると第
５図に示すような半導体装置１４が得られ、リードワイ
ヤ２の他端部な、半田１５により、プリント配線基板な
どの実装基板１５に平面性は実装する。As shown in FIG. 5, a semiconductor element 10 is mounted on this resin substrate 3 using an adhesive 9, and a pad (not shown) of the element 10 is connected to one end of the lead wire 2 of the resin substrate 3 using a connector. Wire bonding is performed using the wire 11, and a cap 13 is attached onto the resin substrate 3 using an adhesive 12 to obtain a semiconductor device 14 as shown in FIG. The flatness is mounted on a mounting board 15 such as a board.
コネクタワイヤ１１には、例えばＡｊ２細線やＡｕ細線
を使用することができる。For the connector wire 11, for example, Aj2 thin wire or Au thin wire can be used.
接着剤９は例え螺Ａｇペーストより構成される。The adhesive 9 is made of a screw Ag paste, for example.
半導体素子（半導体チップ）１０は、例えばシリコン単
結晶基板から成り、周知の技術によってこのチップ内に
は多数の回路素子が形成され、１つの回路機能が与えら
れている。回路素子の具体例は１例えばＭＯＳトランジ
スタから成り、これらの回路素子によって、例えばメモ
リや論理回路の回路機能が形成されている。A semiconductor element (semiconductor chip) 10 is made of, for example, a silicon single crystal substrate, and a large number of circuit elements are formed within this chip using well-known techniques to provide one circuit function. A specific example of a circuit element is, for example, a MOS transistor, and these circuit elements form a circuit function such as a memory or a logic circuit.
接着剤１２は例えばガラス材料より構成される。The adhesive 12 is made of, for example, a glass material.
キャップ１３は、例えば、セラミックや金属により構成
される。The cap 13 is made of ceramic or metal, for example.
（１１本発明によれば、板状の樹脂体中にリードワイヤ
が埋込みされているので、ピンクリッドアレイのごとく
ピンを立設する必要がない。(11) According to the present invention, since the lead wires are embedded in the plate-shaped resin body, there is no need to provide pins upright like in a pin grid array.
（２１本発明によれば、セラミック基板のごとく何層に
もセラミックグリーンシートを積層し、焼結し、各シー
トに導体配線層を設けるような手のかかる製法を経なく
℃もよく、押出成形などにより簡単に作れ、また、樹脂
にリードワイヤを埋込んでいるだけなので、極め℃安価
な基板を提供でき。(21 According to the present invention, ceramic green sheets are laminated in many layers like a ceramic substrate, sintered, and a conductor wiring layer is provided on each sheet. It is easy to make, and since the lead wires are simply embedded in resin, it is possible to provide an extremely inexpensive board.
半導体装置も安価なものを提供できた。We were also able to provide inexpensive semiconductor devices.
（３１本発明によれば、従来のセラミックパッケージで
は、基板上部のコネクタワイヤと基板裏面のピンとを電
気的に接続するために、導体配線層を殊更に設は曵いた
が、本発明ではリードワイヤに直接コネクタワイヤをボ
ンディングでき、その際、リードワイヤの材質を適当に
選択することにより。(31 According to the present invention, in the conventional ceramic package, a conductor wiring layer was not particularly provided in order to electrically connect the connector wire on the top of the board and the pin on the back side of the board, but in the present invention, the lead wire Connector wires can be bonded directly to the lead wire by selecting an appropriate material for the lead wire.
例えばＣｕ系材料とすることにより、ポンディング性向
上のためのメッキなどを省略できる。For example, by using a Cu-based material, plating to improve bonding properties can be omitted.
＋４７ 本発明ではリードワイヤの材質を適当に選択
することにより、樹脂との熱膨張係数差をなりシ。+47 In the present invention, by appropriately selecting the material of the lead wire, the difference in thermal expansion coefficient with the resin can be minimized.
樹脂をマツチングした樹脂基板を得ることができた。A resin substrate with matched resin could be obtained.
（５１本発明によれば、樹脂中に適宜のピッチ、配列で
リードワイヤを多数理め込んであるので、熱の放散が良
く、半導体素子から生ずる熱を当該リードワイヤを介し
て放熱することができ、さらに、実装基板への放熱する
ことができる。(51 According to the present invention, since a large number of lead wires are embedded in the resin at an appropriate pitch and arrangement, heat dissipation is good, and the heat generated from the semiconductor element can be dissipated through the lead wires. Furthermore, heat can be radiated to the mounting board.
このリードワイヤは導通（ワイヤボンディング）をとる
部分の外罠、多数特に半導体素子の下側に多数配設する
ことにより、より一層放熱特性が良くなり、信頼性の向
上に□寄与することができる。By arranging a large number of these lead wires outside of the part where conduction (wire bonding) is established, especially on the underside of the semiconductor element, the heat dissipation characteristics are further improved, which can contribute to improved reliability. .
（６１本発明によれば先の実施例にも示すごとく、その
構造上も製法上も簡易なものとすることができ、コスト
を著しく低減できた。(61) According to the present invention, as shown in the previous embodiment, the structure and manufacturing method can be simplified, and the cost can be significantly reduced.
以上本発明によってなされた発明を実施例にもとづき具
体的に説明したが、本発明は上記実施側圧限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもない。Although the invention made by the present invention has been specifically explained above based on examples, it goes without saying that the present invention is not limited to the above-mentioned implementation side pressure, and can be modified in various ways without departing from the gist thereof. .
例えば、リードビンの高さについて樹脂の上面や下面と
一致させる。あるいはこれら面よりも低くしてもよ（、
さらには、これら面から突出させてもよい。特に、下面
より突出することにより、牛田付は実装の際のメニスカ
スを形成することができる利点がある。For example, the height of the lead bin is made to match the top and bottom surfaces of the resin. Or you can make it lower than these surfaces (,
Furthermore, it may be made to protrude from these surfaces. In particular, by protruding from the lower surface, the Ushida attachment has the advantage of forming a meniscus during mounting.
本発明の樹脂基板は、基板としてセラミック基板などく
代って使用でき、前述したビングリッドアレイパッケー
ジやパッドグリッドアレイパッケージの他Ｋ、各種パッ
ケージの基板とし工区範囲に使用できる。The resin substrate of the present invention can be used as a substrate in place of a ceramic substrate, and can be used as a substrate for various packages such as the above-mentioned bin grid array package and pad grid array package in a range of construction areas.
特に、安価で、小型化、高密度化、高信頼性を意図する
分野に好適に使用でき、半導体装置の他各種電子部品、
装置の分野にも適用できる。In particular, it can be used suitably in fields where low cost, miniaturization, high density, and high reliability are intended, and it can be used for semiconductor devices and various other electronic components.
It can also be applied to the field of equipment.
第１図は本発明の実施例を示す斜視図。
第２図は第１図１−１線に沿う一例断面図。
第３図は第２図■−■線に沿う一例断面図。
第４図は本発明樹脂基板の製法の説明図、第５図は本発
明による樹脂基板の応用例の一例を示す断面図である。
１・・・樹脂体、２・・・リードワイヤ、３・・・樹脂
基板。
４・・・ダイ、５・・・矢標方向、６・・・ホッパー、
７・・・矢標方向、８・・・矢標方向、９・・・接着剤
、１０・・・半導体素子、１１・・・コネクタワイヤ、
１２・・・接着剤。
１３・・・キャップ、１４・・・半導体装置、１５・・
・半田。
１６・・・実装基板。
代理人弁理士 小 川 勝 男 ゛第 １
図
第 ４ 図
第 ５ 図FIG. 1 is a perspective view showing an embodiment of the present invention. FIG. 2 is an example cross-sectional view taken along the line 1-1 in FIG. 1. FIG. 3 is an example cross-sectional view taken along the line ■-■ in FIG. 2. FIG. 4 is an explanatory diagram of a method for manufacturing a resin substrate according to the present invention, and FIG. 5 is a sectional view showing an example of an application of the resin substrate according to the present invention. DESCRIPTION OF SYMBOLS 1...Resin body, 2...Lead wire, 3...Resin board. 4...Die, 5...Arrow direction, 6...Hopper,
7... Arrow direction, 8... Arrow direction, 9... Adhesive, 10... Semiconductor element, 11... Connector wire,
12...Adhesive. 13... Cap, 14... Semiconductor device, 15...
·solder. 16... Mounting board. Representative Patent Attorney Katsuo Ogawa ゛No. 1
Figure 4 Figure 5
Claims (1)
のリードワイヤを埋込んで成ることを特徴とする樹脂基
板。 ２、特許請求の範囲第１項記載の樹脂基板が、リードワ
イヤを複数本埋込んだ樹脂体を切断して成るものから成
ることを特徴とする特許請求の範囲第１項記載の樹脂基
板。[Scope of Claims] 1. A resin substrate characterized in that lead wires of arbitrary thickness are embedded in a plate-shaped resin body at an appropriate pitch and arrangement. 2. The resin substrate according to claim 1, wherein the resin substrate according to claim 1 is made by cutting a resin body in which a plurality of lead wires are embedded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60009013A JPS61168926A (en) | 1985-01-23 | 1985-01-23 | Resin substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60009013A JPS61168926A (en) | 1985-01-23 | 1985-01-23 | Resin substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61168926A true JPS61168926A (en) | 1986-07-30 |
Family
ID=11708765
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60009013A Pending JPS61168926A (en) | 1985-01-23 | 1985-01-23 | Resin substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61168926A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5067007A (en) * | 1988-06-13 | 1991-11-19 | Hitachi, Ltd. | Semiconductor device having leads for mounting to a surface of a printed circuit board |
| US5347162A (en) * | 1989-08-28 | 1994-09-13 | Lsi Logic Corporation | Preformed planar structures employing embedded conductors |
| US5489804A (en) * | 1989-08-28 | 1996-02-06 | Lsi Logic Corporation | Flexible preformed planar structures for interposing between a chip and a substrate |
| US5504035A (en) * | 1989-08-28 | 1996-04-02 | Lsi Logic Corporation | Process for solder ball interconnecting a semiconductor device to a substrate using a noble metal foil embedded interposer substrate |
| US5770889A (en) * | 1995-12-29 | 1998-06-23 | Lsi Logic Corporation | Systems having advanced pre-formed planar structures |
| US5834799A (en) * | 1989-08-28 | 1998-11-10 | Lsi Logic | Optically transmissive preformed planar structures |
-
1985
- 1985-01-23 JP JP60009013A patent/JPS61168926A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5067007A (en) * | 1988-06-13 | 1991-11-19 | Hitachi, Ltd. | Semiconductor device having leads for mounting to a surface of a printed circuit board |
| US5347162A (en) * | 1989-08-28 | 1994-09-13 | Lsi Logic Corporation | Preformed planar structures employing embedded conductors |
| US5410805A (en) * | 1989-08-28 | 1995-05-02 | Lsi Logic Corporation | Method and apparatus for isolation of flux materials in "flip-chip" manufacturing |
| US5489804A (en) * | 1989-08-28 | 1996-02-06 | Lsi Logic Corporation | Flexible preformed planar structures for interposing between a chip and a substrate |
| US5504035A (en) * | 1989-08-28 | 1996-04-02 | Lsi Logic Corporation | Process for solder ball interconnecting a semiconductor device to a substrate using a noble metal foil embedded interposer substrate |
| US5569963A (en) * | 1989-08-28 | 1996-10-29 | Lsi Logic Corporation | Preformed planar structures for semiconductor device assemblies |
| US5834799A (en) * | 1989-08-28 | 1998-11-10 | Lsi Logic | Optically transmissive preformed planar structures |
| US5770889A (en) * | 1995-12-29 | 1998-06-23 | Lsi Logic Corporation | Systems having advanced pre-formed planar structures |
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