JPH07147359A - Surface mounting type semiconductor device - Google Patents
Surface mounting type semiconductor deviceInfo
- Publication number
- JPH07147359A JPH07147359A JP5295720A JP29572093A JPH07147359A JP H07147359 A JPH07147359 A JP H07147359A JP 5295720 A JP5295720 A JP 5295720A JP 29572093 A JP29572093 A JP 29572093A JP H07147359 A JPH07147359 A JP H07147359A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- resin
- section
- semiconductor device
- thin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、より小型化し且つ端子
間短絡の危惧を防止した表面実装型の半導体装置に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface mount type semiconductor device which is further miniaturized and which prevents a fear of a short circuit between terminals.
【０００２】[0002]
【従来の技術】軽薄短小化を実現する１つの手段とし
て、プリント基板の導電パタ−ンにリードを対向接着す
るために樹脂から導出したリードをＺ字型にフォ−ミン
グした表面実装型の半導体パッケージが製造されてい
る。図３は、従来実用化されている表面実装型のパッケ
−ジを示す断面図（Ａ）と裏面図（Ｂ）である。ダイボ
ンドされた半導体チップ（１）とリード（２）とをワイ
ヤ（３）で接続した後半導体チップ（１）を樹脂（４）
でモ−ルドし、樹脂（４）から導出されたリード（２）
を樹脂の裏面と一直線状になるようにＺ字型に折り曲げ
たものである（例えば、特願平３−２４９６９５号）。2. Description of the Related Art As one means for realizing lightness, thinness, shortness and size, a surface-mounting type semiconductor in which leads derived from a resin for facing and adhering the leads to a conductive pattern of a printed circuit board are formed into a Z-shape. The package is being manufactured. FIG. 3 is a cross-sectional view (A) and a back view (B) showing a surface-mounted package that has been put into practical use in the past. After connecting the die-bonded semiconductor chip (1) and the lead (2) with a wire (3), the semiconductor chip (1) is resin (4).
Molded in, lead (2) derived from resin (4)
Is bent into a Z shape so as to be in line with the back surface of the resin (for example, Japanese Patent Application No. 3-249695).
【０００３】部品の実装密度の向上を目的として、この
ようなパッケージにすら更なる小型化が望まれている。
そこで、図４の断面図（Ａ）と裏面図（Ｂ）に示すよう
に、リード（２）の曲げ部分（５）を樹脂（４）の内部
に取り込んだもの、図５の断面図（Ａ）と裏面図（Ｂ）
に示すように、リード（２）の裏面を樹脂（４）表面に
露出するようにしてリード（２）の部分をなくしたも
の、が考えられている。図４、図５の構造は、リード
（２）先端の半田接着部分が樹脂（４）から離れていな
いので、その分プリント基板の導電パターンの高密度化
を図ることができる。また、図５の構造は図３、図４の
ものに比べて、リード（２）に曲げ部分（５）を形成し
ないので、加工精度を向上でき、その分小型化が可能と
なる。For the purpose of improving the mounting density of parts, further miniaturization of such a package is desired.
Therefore, as shown in the sectional view (A) of FIG. 4 and the rear view (B), the bent portion (5) of the lead (2) is taken inside the resin (4), and the sectional view (A) of FIG. ) And back view (B)
As shown in FIG. 2, it is considered that the back surface of the lead (2) is exposed on the surface of the resin (4) so that the lead (2) portion is eliminated. In the structures of FIGS. 4 and 5, since the solder bonding portion at the tip of the lead (2) is not separated from the resin (4), it is possible to increase the density of the conductive pattern of the printed circuit board accordingly. Further, the structure of FIG. 5 does not have the bent portion (5) formed on the lead (2) as compared with the structure of FIGS.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、図５の
構造は、樹脂（４）の裏面にリード（２）の裏面が露出
するので、リード（２）間の離間距離が小さく、しかも
同一平面を形成するので、半田実装時の半田の過剰な広
がりなどにより端子間の短絡事故が発生する危惧があ
る。However, in the structure shown in FIG. 5, since the back surface of the lead (2) is exposed on the back surface of the resin (4), the distance between the leads (2) is small, and the same plane is provided. Since it is formed, there is a concern that a short circuit between terminals may occur due to excessive spread of solder during solder mounting.
【０００５】[0005]
【課題を解決するための手段】本発明は上記従来の欠点
に鑑み成されたもので、リードに曲げ部分を作らず、し
かも露出しているリード間の距離を大にできる、小型化
したパッケージを提供することを目的とし、リードを厚
肉部と薄肉部とで構成するとともに薄肉部を樹脂内部に
封止、厚肉部を樹脂外部に導出して、樹脂表面に露出す
るリード表面の端子間距離を拡大したことを骨子とする
ものである。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks of the prior art, and it is a miniaturized package that does not form a bent portion in the leads and can increase the distance between exposed leads. In order to provide a lead, the lead is composed of a thick part and a thin part, the thin part is sealed inside the resin, the thick part is led out to the resin, and the lead surface terminal exposed on the resin surface is provided. The main idea is to increase the distance.
【０００６】[0006]
【作用】本発明によれば、リード（２）が途中から薄肉
部になって樹脂内部に封止されるので、樹脂（４）表面
におけるリード（２）間の距離を拡大できる。しかも、
リード（２）に曲げ加工を施さないので、加工精度を向
上できる。According to the present invention, since the lead (2) becomes a thin portion from the middle and is sealed inside the resin, the distance between the leads (2) on the surface of the resin (4) can be increased. Moreover,
Since the lead (2) is not bent, the working accuracy can be improved.
【０００７】[0007]
【実施例】以下に本発明の一実施例を説明する。図１は
本発明の第１の実施例を示す（Ａ）断面図と（Ｂ）裏面
図である。半導体チップ（１）はトランジスタチップ、
ダイオードチップ等であり、リードフレームのタブまた
はアイランドと称される部分にダイボンドされ、半導体
チップ（１）の表面に形成された電極とリード（２）と
がワイヤ（３）でワイヤボンドされている。リード
（２）は板厚が部分的に異なる異形材から打ち抜き加工
により製造されたもので、その結果リード（２）には厚
肉部（６）と薄肉部（７）とを有する。厚肉部（６）の
板厚は０．５ｍｍ程度、薄肉部（７）の板厚は０．２ｍ
ｍ程度である。EXAMPLE An example of the present invention will be described below. FIG. 1 is a sectional view (A) and a back view (B) showing a first embodiment of the present invention. The semiconductor chip (1) is a transistor chip,
A diode chip or the like, which is die-bonded to a portion called a tab or an island of a lead frame, and an electrode formed on the surface of the semiconductor chip (1) and a lead (2) are wire-bonded with a wire (3). . The lead (2) is manufactured by punching from a profile material having a partially different plate thickness, and as a result, the lead (2) has a thick portion (6) and a thin portion (7). The thick part (6) has a thickness of about 0.5 mm, and the thin part (7) has a thickness of 0.2 m.
It is about m.
【０００８】リード（２）は曲げ部分を持たず、平板状
態のままで封止されている。リード（２）の厚肉部
（６）は樹脂（４）の外部に導出されて外部接続用端子
となる。厚肉部（６）の裏面は樹脂（４）の表面と同一
平面を構成するように露出している。リード（２）はパ
ッケ−ジの内部において途中から薄肉部（７）となり、
薄肉部（７）は樹脂（４）の内部に封止されている。途
中から肉厚が薄くなった部分には樹脂（４）が存在する
ので、リード（２）の露出表面は薄肉部（７）を設けた
分だけ少なく（短く）なる。The lead (2) has no bent portion and is sealed in a flat plate state. The thick portion (6) of the lead (2) is led out of the resin (4) to serve as an external connection terminal. The back surface of the thick portion (6) is exposed so as to be flush with the front surface of the resin (4). The lead (2) becomes a thin portion (7) in the middle of the package,
The thin portion (7) is sealed inside the resin (4). Since the resin (4) is present in the portion where the wall thickness is reduced from the middle, the exposed surface of the lead (2) is reduced (shortened) by the provision of the thin wall portion (7).
【０００９】各リード（２）間の距離が最も狭くなる部
分は、薄肉部（７）で構成する。これは、リードフレー
ム製造の打ち抜き加工に要する抜きしろが、板厚に単純
に比例するため、該抜きしろを最小にするためである。
このようなパッケージの小型化は、概ね以下の制限事項
でその限界が決まる。 （ａ）搭載する半導体チップ（１）のチップサイズ （ｂ）ダイボンドの位置決め精度を見込んだアイランド
部の大きさ （ｃ）リードフレ−ムの加工精度 （ｄ）リード（２）間の抜きしろ （ｅ）ワイヤボンドのボンディングエリアに要する面積 これらに加えて、樹脂（４）からのリード（２）の抜
け、剥がれを防止できるだけの両者の接触面積、耐湿性
を保つだけの樹脂（４）の厚みとリード（２）のパスの
長さ、等が考慮されることになる。The portion where the distance between the leads (2) is the shortest is constituted by the thin portion (7). This is because the cutting margin required for the punching process for manufacturing the lead frame is simply proportional to the plate thickness, and thus the cutting margin is minimized.
The miniaturization of such a package is generally limited by the following restrictions. (A) Chip size of semiconductor chip (1) to be mounted (b) Size of island part in view of positioning accuracy of die bond (c) Processing accuracy of lead frame (d) Space between leads (2) (e) ) Area required for bonding area of wire bond In addition to these, the contact area of both that can prevent the lead (2) from coming off and peeling from the resin (4), and the thickness of the resin (4) sufficient to keep moisture resistance The length of the path of the lead (2), etc. will be taken into consideration.
【００１０】上記本発明のパッケ−ジは、リード（１）
が平板状態のままで曲げ加工が施されないので、曲げに
伴う加工精度の劣化がない。よって小型化の制限事項
（ｃ）が改善され、しかも組み立て工程を簡素化でき
る。また、リード（２）間の最も狭い部分は薄肉部
（７）で構成するようにしたので、加工の抜きしろを最
小の値にできる。よって制限事項（ｄ）を最小値に保て
る。さらに、リード（２）を厚肉部（６）と薄肉部
（７）とに形成したので、樹脂（４）との接触面積が増
大し、パスも長く成るので、リード（２）の接着強度と
耐湿性の点で大型化することを防止できる。これらによ
って、一層小型化されたパッケージを実現することがで
きる。The package of the present invention has the leads (1).
Since the plate is in a flat plate state and is not bent, the processing accuracy does not deteriorate due to bending. Therefore, the restriction (c) for downsizing is improved, and the assembly process can be simplified. Further, since the narrowest portion between the leads (2) is constituted by the thin portion (7), the margin for machining can be minimized. Therefore, the restriction item (d) can be kept at the minimum value. Further, since the lead (2) is formed in the thick portion (6) and the thin portion (7), the contact area with the resin (4) increases and the path also becomes longer, so the adhesive strength of the lead (2) is increased. With respect to the moisture resistance, it can be prevented from increasing in size. With these, it is possible to realize a further downsized package.
【００１１】さらに本発明のパッケージは、パッケージ
の裏面側に露出するリード（２）が薄肉部（７）を設け
た分小さく（短く）なるので、各リード（２）間の離間
距離を増大できる。このパッケージは、プリント基板の
表面に描画された導電パターンの表面にリード（２）の
裏面側を対向接着することにより実装されるもので、前
記リード（２）間の距離が増大することによって、半田
の過剰拡大等による短絡事故を防止できるものである。
図２に本発明の第２の実施例を示した。表面実装型であ
るとはいえ、多少の発熱を伴うパワー素子を搭載する用
途が現実に存在する。本実施例はかかる要求に対応する
場合の構成であり、半導体チップ（１）を搭載するタブ
部（８）までを厚肉部（６）で構成したものである。タ
ブ部（８）は熱容量を増大したヒ−トシンクとしての役
割を果たし、樹脂（４）から露出させた部分を導電パタ
ーンに密着させて放熱効果を高めるように実装される。
本実施例はタブ部（８）のリード（２）の薄肉部（７）
が短くなるものの、以外のリード（２）の薄肉部（７）
によって端子間距離の拡大が図られている。Further, in the package of the present invention, the lead (2) exposed on the back surface side of the package is made smaller (shorter) by the provision of the thin portion (7), so that the distance between the leads (2) can be increased. . This package is mounted by adhering the back side of the lead (2) to the surface of the conductive pattern drawn on the surface of the printed circuit board so that the distance between the leads (2) increases. It is possible to prevent a short circuit accident due to excessive expansion of solder.
FIG. 2 shows a second embodiment of the present invention. Even though it is a surface mount type, there is actually an application to mount a power element that generates some heat. The present embodiment is a configuration in the case of meeting such a requirement, in which the tab portion (8) on which the semiconductor chip (1) is mounted is constituted by the thick portion (6). The tab portion (8) plays a role as a heat sink having an increased heat capacity, and is mounted so that the portion exposed from the resin (4) is brought into close contact with the conductive pattern to enhance the heat radiation effect.
In this embodiment, the thin portion (7) of the lead (2) of the tab portion (8) is used.
Although it is short, except for the thin part (7) of the lead (2)
The distance between the terminals has been expanded by.
【００１２】尚、上記実施例は３端子のパッケージにつ
いてのみ説明してきたが、 これ以外にも４端子、６端
子のものも同様に実施できる。さらにタブ部（８）を２
個設けたものでも同様に実施できるものである。Although the above embodiment has described only the three-terminal package, other packages having four terminals and six terminals can be similarly implemented. 2 tabs (8)
The same can be done with the one provided.
【００１３】[0013]
【発明の効果】以上に説明したとおり、本発明によれ
ば、リード（２）に薄肉部（７）を設けることにより、
パッケージの小型化を実現すると同時に、端子間距離を
増大して、実装時の短絡事故を防止できるという利点を
有する。As described above, according to the present invention, by providing the lead (2) with the thin portion (7),
This has an advantage that the package can be downsized and at the same time the distance between terminals can be increased to prevent a short circuit accident during mounting.
【図１】本発明の第１の実施例を説明するための（Ａ）
断面図、（Ｂ）裏面図である。FIG. 1A is a view for explaining the first embodiment of the present invention.
It is a sectional view and a (B) back view.
【図２】本発明の第２の実施例を説明するための（Ａ）
断面図、（Ｂ）裏面図である。FIG. 2A is a view for explaining the second embodiment of the present invention.
It is a sectional view and a (B) back view.
【図３】第１の従来例を説明するための（Ａ）断面図、
（Ｂ）裏面図である。FIG. 3 is a sectional view (A) for explaining a first conventional example;
(B) It is a rear view.
【図４】第２の従来例を説明するための（Ａ）断面図、
（Ｂ）裏面図である。FIG. 4 is a sectional view (A) for explaining a second conventional example;
(B) It is a rear view.
【図５】第３の従来例を説明するための（Ａ）断面図、
（Ｂ）裏面図である。FIG. 5 is a sectional view (A) for explaining a third conventional example;
(B) It is a rear view.
Claims (2)
て樹脂モ−ルドした表面実装型半導体装置において、 リ−ドが厚肉部と薄肉部とからなり、 前記厚肉部は前記樹脂の内部から外部に導出されて外部
接続端子となり、且つ裏面が前記樹脂の表面と同一平面
を構成するように露出し、 前記厚肉部に連続する薄肉部が樹脂内部に封止されて、
前記厚肉部の露出表面が終端していることを特徴とする
表面実装型半導体装置。1. A surface mount semiconductor device in which a semiconductor chip is mounted on a lead frame and molded by resin, wherein the lead is composed of a thick portion and a thin portion, and the thick portion is formed from the inside of the resin. It is led out to the outside to be an external connection terminal, and the back surface is exposed so as to form the same plane as the front surface of the resin, and a thin portion continuous with the thick portion is sealed inside the resin,
A surface-mounted semiconductor device, wherein the exposed surface of the thick portion terminates.
リードとが、前記薄肉部でもっとも接近していることを
特徴とする請求項１記載の表面実装型半導体装置。2. The surface mount semiconductor device according to claim 1, wherein the portion on which the semiconductor chip is mounted and the lead are closest to each other in the thin portion.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5295720A JP2902918B2 (en) | 1993-11-25 | 1993-11-25 | Surface mount type semiconductor device |
| KR1019940030373A KR950015728A (en) | 1993-11-25 | 1994-11-22 | Surface Mount Semiconductor Devices |
| KR1019940030737A KR100208635B1 (en) | 1993-11-25 | 1994-11-22 | Surface mounted type semiconductor package |
| US08/344,424 US5521429A (en) | 1993-11-25 | 1994-11-23 | Surface-mount flat package semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5295720A JP2902918B2 (en) | 1993-11-25 | 1993-11-25 | Surface mount type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07147359A true JPH07147359A (en) | 1995-06-06 |
| JP2902918B2 JP2902918B2 (en) | 1999-06-07 |
Family
ID=17824294
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5295720A Expired - Lifetime JP2902918B2 (en) | 1993-11-25 | 1993-11-25 | Surface mount type semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP2902918B2 (en) |
| KR (2) | KR950015728A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002208664A (en) * | 2001-01-12 | 2002-07-26 | Rohm Co Ltd | Method for manufacturing lead frame and semiconductor device |
| JP2005277434A (en) * | 2005-05-09 | 2005-10-06 | Renesas Technology Corp | Semiconductor device |
| JP2007318175A (en) * | 2007-08-10 | 2007-12-06 | Renesas Technology Corp | Method for manufacturing semiconductor device |
| JP2008517482A (en) * | 2004-10-18 | 2008-05-22 | チップパック，インク． | Multi-chip lead frame package |
| JP2011023736A (en) * | 2010-09-13 | 2011-02-03 | Renesas Electronics Corp | Semiconductor device |
| JP2011101065A (en) * | 2011-02-24 | 2011-05-19 | Rohm Co Ltd | Semiconductor device |
| WO2022195939A1 (en) * | 2021-03-18 | 2022-09-22 | 株式会社村田製作所 | Electronic component and electronic device |
-
1993
- 1993-11-25 JP JP5295720A patent/JP2902918B2/en not_active Expired - Lifetime
-
1994
- 1994-11-22 KR KR1019940030373A patent/KR950015728A/en not_active Application Discontinuation
- 1994-11-22 KR KR1019940030737A patent/KR100208635B1/en not_active IP Right Cessation
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002208664A (en) * | 2001-01-12 | 2002-07-26 | Rohm Co Ltd | Method for manufacturing lead frame and semiconductor device |
| JP4574868B2 (en) * | 2001-01-12 | 2010-11-04 | ローム株式会社 | Semiconductor device |
| JP2008517482A (en) * | 2004-10-18 | 2008-05-22 | チップパック，インク． | Multi-chip lead frame package |
| JP2005277434A (en) * | 2005-05-09 | 2005-10-06 | Renesas Technology Corp | Semiconductor device |
| JP2007318175A (en) * | 2007-08-10 | 2007-12-06 | Renesas Technology Corp | Method for manufacturing semiconductor device |
| JP2011023736A (en) * | 2010-09-13 | 2011-02-03 | Renesas Electronics Corp | Semiconductor device |
| JP2011101065A (en) * | 2011-02-24 | 2011-05-19 | Rohm Co Ltd | Semiconductor device |
| WO2022195939A1 (en) * | 2021-03-18 | 2022-09-22 | 株式会社村田製作所 | Electronic component and electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2902918B2 (en) | 1999-06-07 |
| KR100208635B1 (en) | 1999-07-15 |
| KR950015728A (en) | 1995-06-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR950012921B1 (en) | Plastic mold semiconductor device | |
| JP3230348B2 (en) | Resin-sealed semiconductor device and method of manufacturing the same | |
| US5800958A (en) | Electrically enhanced power quad flat pack arrangement | |
| US5172214A (en) | Leadless semiconductor device and method for making the same | |
| EP1143514A2 (en) | Resin-sealed power semiconductor device including substrate with all electronic components for control circuit mounted thereon | |
| US6753599B2 (en) | Semiconductor package and mounting structure on substrate thereof and stack structure thereof | |
| JPH07147359A (en) | Surface mounting type semiconductor device | |
| JP2902919B2 (en) | Surface mount type semiconductor device | |
| US5326932A (en) | Semiconductor package | |
| JPH05291467A (en) | Lead frame and semiconductor device | |
| JPH08186212A (en) | Resin sealed electronic component and lead frame | |
| JP2533012B2 (en) | Surface mount semiconductor device | |
| JP2524482B2 (en) | QFP structure semiconductor device | |
| JPH11297917A (en) | Semiconductor device and its manufacture | |
| JP2533011B2 (en) | Surface mount semiconductor device | |
| JP2000349222A (en) | Lead frame and semiconductor package | |
| JP2538407B2 (en) | Surface mount semiconductor device | |
| KR100291511B1 (en) | Multi-chip package | |
| JPS6329413B2 (en) | ||
| JPS6217382B2 (en) | ||
| JPH0529539A (en) | Multi-chip module | |
| KR20010107549A (en) | Multilayer lead frame and semiconductor device using the same | |
| KR100567045B1 (en) | A package | |
| KR100369501B1 (en) | Semiconductor Package | |
| JPH0320067B2 (en) |