JPS62169450A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS62169450A JPS62169450A JP61010089A JP1008986A JPS62169450A JP S62169450 A JPS62169450 A JP S62169450A JP 61010089 A JP61010089 A JP 61010089A JP 1008986 A JP1008986 A JP 1008986A JP S62169450 A JPS62169450 A JP S62169450A
- Authority
- JP
- Japan
- Prior art keywords
- stem
- semiconductor device
- package
- exposed
- plastic package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 71
- 238000000034 method Methods 0.000 abstract description 6
- 229910052751 metal Inorganic materials 0.000 abstract description 3
- 239000002184 metal Substances 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 14
- 230000017525 heat dissipation Effects 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 5
- 239000004020 conductor Substances 0.000 description 3
- 238000001816 cooling Methods 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000002826 coolant Substances 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000005357 flat glass Substances 0.000 description 1
- 239000004519 grease Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 230000000191 radiation effect Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
- H01L23/4334—Auxiliary members in encapsulations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体装置技術、さらにはプラスチックパ
ッケージで封止された多ビン型の半導体装置に適用して
有効な技術に関するもので、たとえば、表面実装型の多
ビン半導体集積回路装置に適用して有効な技術に関する
もので、たとえば、表面実装型の多ピン半導体集積回路
装置ｉｔＫ利用して有効な技術に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor device technology, and further to technology that is effective when applied to multi-bin type semiconductor devices sealed in plastic packages. The present invention relates to a technique that is effective when applied to a surface-mounted multi-bin semiconductor integrated circuit device, for example, a technique that is effective when applied to a surface-mounted multi-pin semiconductor integrated circuit device itK.
一般に、半導体装置ｖｔｆ′ｉ、所定の回路機能が形成
された半導体チップがパッケージに封止された状態に形
成され、この状態でもってプリント配線基板などに実装
される。この場合、そのパッケージのタイプとしては、
プラスチックタイプ、セラミックタイプ、金属缶タイプ
などがある。しかし、一般の民生用などでは、量産性に
適した安価なグラスチックタイプのものが多く使用され
ている。Generally, a semiconductor device vtf'i, a semiconductor chip on which a predetermined circuit function is formed, is formed in a sealed state in a package, and in this state is mounted on a printed wiring board or the like. In this case, the package type is
There are plastic types, ceramic types, and metal can types. However, for general consumer use, inexpensive glass types that are suitable for mass production are often used.
このグラスチックタイプのパッケージで封止された半導
体装置は、友とえば、日経マグロウヒル社発行「別冊
マイクロデバイセス４１９８４年６月１１日発行１４８
〜１５９頁（解説：グラスチツクは小型と表面実装へ、
セラミックは高速多ビンに）に記載されているように、
表面実装用に作られることが最近になって多くなってき
た。Semiconductor devices sealed in this glass-type package are sold in a special edition published by Nikkei McGraw-Hill.
Microdevices 4 Published June 11, 1984 148
~Page 159 (Explanation: Glass chips move towards small size and surface mounting,
Ceramic is fast multi-bin) as stated in
Lately, more and more devices have been made for surface mounting.
一方、最近のパワー系リニアＩＣ（半導体集積回路装り
などには、パワー素子とともに複雑かつ高度な回路機能
をモノリシック化したものが現れてきた。このようなＩ
Ｃは、従前のパワー素子に比べて、非常に多くのリード
端子ビンが必要となってくる。On the other hand, in recent power linear ICs (semiconductor integrated circuits, etc.), monolithic devices have appeared that have complex and advanced circuit functions as well as power elements.
C requires a significantly larger number of lead terminal pins than conventional power devices.
ここで、本発明者は、たとえば複雑かつ高度な回路機能
を備えたパワー系ＩＣを、プラスチックパッケージによ
って表面実装可能な形状に構成することについて検討し
た。以下は、公知とされた技術ではないが、本発明者に
よって検討された技術であり、その概要は次のとおりで
ある。Here, the present inventor has considered, for example, configuring a power system IC with complex and advanced circuit functions into a shape that can be surface mounted using a plastic package. Although the following is not a publicly known technique, it is a technique studied by the present inventor, and its outline is as follows.
第１２図（ａ）（ｂ）は本発明者によって検討され九半
導体装置ｌの構成例を示す。同図（ａ）は上側から見た
平面状態を、（ｂ）は（ａ）のＢ−Ｂ部分の断面状態を
示す。FIGS. 12(a) and 12(b) show an example of the configuration of a nine-semiconductor device 1 studied by the present inventor. 3(a) shows a planar state viewed from above, and FIG. 2(b) shows a cross-sectional state taken along the line BB in FIG. 3(a).
同図に示す半導体装置１は、複雑かつ高度な回路機能を
備えたパワー系ＩＪ ＝７ＩＣを表面実装用に形成した
ものであって、パワー素子とともに多数の回路素子が集
積形成された半導体チップ１が扁平なプラスチックパッ
ケージ２内にモールド封止されている。これとともに、
そのプラスチックパッケージ２の西側力からそれぞれ多
数のリード端子３が導出されている。パッケージ２の底
面と各リード端子３の先端位置はほぼ同一高さに揃えら
れている。これにより、同図（ｂ）に示すように、プリ
ント配線基板４に直接面付けできるように、つまり表面
実装できるようになりている。同図（ｂ）において、５
はハンダ付は部分、６は接着剤などＫよる接着部分をそ
れぞれ示す。A semiconductor device 1 shown in the figure is a power system IJ=7IC with complex and advanced circuit functions formed for surface mounting, and a semiconductor chip 1 in which a large number of circuit elements are integrated together with a power element. is molded and sealed inside a flat plastic package 2. Along with this,
A large number of lead terminals 3 are led out from each side of the plastic package 2. The bottom surface of the package 2 and the tip positions of the lead terminals 3 are approximately at the same height. This allows direct mounting on the printed wiring board 4, that is, surface mounting, as shown in FIG. 4(b). In the same figure (b), 5
6 indicates a soldered part, and 6 indicates a part bonded with K, such as an adhesive.
しかしながら、上述した技術には、次のような問題点の
あることが本発明者によってあきらかとされた。However, the inventors have found that the above-mentioned technique has the following problems.
すなわち、上述したような半導体装置では５表面実装の
効果をあげるためのパッケージ２の小型化と、回路機能
の高度化に伴う多ビン化の両方を両立させるために、そ
の多数のリード端子３はどうしてもパッケージ２の西側
力に振り分けて導出させなければならなくなる。このた
め、たとえば第１３図に示す半導体装置１のような構造
、すなわち半導体チップ７が固定されているステム９の
一部をパッケージ２の側方へ露出させて放熱効果を高め
るといった構造を探ることができなくなってしまい、こ
れによって十分な放熱効果が得られなくなってしまう、
という問題点を生じることが本発明者によってあきらか
とされた。That is, in the semiconductor device described above, in order to achieve both the miniaturization of the package 2 to improve the effect of surface mounting and the increase in the number of bins due to the sophistication of circuit functions, the large number of lead terminals 3 are Inevitably, it will be necessary to allocate it to the Western power of Package 2 and derive it. For this reason, for example, a structure such as the semiconductor device 1 shown in FIG. 13, in which a part of the stem 9 to which the semiconductor chip 7 is fixed is exposed to the side of the package 2 to enhance the heat dissipation effect is being explored. As a result, sufficient heat dissipation effect cannot be obtained.
The inventor has found that this problem arises.
本発明の目的は、表面実装に適した形状および大きさを
保ちつつ、プラスチックパッケージで封止された多ビン
の半導体装置の放熱効果を向上させることができるよう
にし、これによって、たとえば複雑かつ高度な回路機能
が内蔵されたパワー系ＩＪ ニアＩＣも表面実装に適し
た形状に形成できるようにする、という技術を提供する
ものである。An object of the present invention is to improve the heat dissipation effect of a multi-bin semiconductor device sealed in a plastic package while maintaining a shape and size suitable for surface mounting. The present invention provides a technology that enables power system IJ near ICs with built-in circuit functions to be formed into shapes suitable for surface mounting.
本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおシである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、ステムに固定された半導体チップのリード端
子をグラスチックパッケージの西側力に振シ分けて導出
させるとともに、そのステムの一部をパッケージの下面
あるいは上面から部分的に露出させるようにしたもので
ある。In other words, the lead terminals of the semiconductor chip fixed to the stem are distributed to the west side of the plastic package and led out, and part of the stem is partially exposed from the bottom or top of the package. be.
上記した手段によれば、回路機能の高度化に伴う多ビン
化と表面実装に適合させるための小型化とを両立させつ
つ、プラスチックパッケージで封止された多ピンの半導
体装置の放熱効果を向上させることができるようになる
。これによって、たとえば複雑かつ高度な回路機能が内
蔵されたパワー系リニアＩＣも表面実装に適した形状に
形成できるようにする、という目的が達成される。According to the above-mentioned means, the heat dissipation effect of a multi-pin semiconductor device sealed in a plastic package is improved while achieving both the increase in the number of bins due to the advancement of circuit functions and the miniaturization for adapting to surface mounting. You will be able to do so. This achieves the purpose of, for example, making it possible to form a power system linear IC with a built-in complex and advanced circuit function into a shape suitable for surface mounting.
以下、本発明の好適な実施例を図面に基づいて説明する
。Hereinafter, preferred embodiments of the present invention will be described based on the drawings.
なお、各図中、同一符号は同一あるいは相当部分を示す
。In each figure, the same reference numerals indicate the same or corresponding parts.
第１図および第２図はこの発明による技術が適用された
半導体装置の一実施例を示す。この場合、第１図は実装
状態にある半導体装置の断面図を１第２図は非実装状態
にある半導体装置の斜視図をそれぞれ示す。1 and 2 show an embodiment of a semiconductor device to which the technology according to the present invention is applied. In this case, FIG. 1 shows a sectional view of the semiconductor device in a mounted state, and FIG. 2 shows a perspective view of the semiconductor device in an unmounted state.
同図に示す半導体装置１は多ピン型のパワー系リニアＩ
Ｃとして構成され、その半導体チップ７は表面実装に適
合させるために扁平なグラスチックパッケージ２によっ
てモールド封止されている。A semiconductor device 1 shown in the figure is a multi-pin type power system linear I
The semiconductor chip 7 is mold-sealed with a flat glass package 2 in order to be suitable for surface mounting.
ここで、半導体チップ７は、第１図に示すように、パッ
ケージ２内にて金属ステム７の上に載置・固定されてい
る。このステム９に固定された半導体チップ７は、ポン
ディングワイヤ８によって多数のリード端子３に接続さ
れている。この多数のリード端子３は、第２図に示すよ
うに、ノくツケージ２の四方の側面へ略等本数ずつ振り
分けられて導出させられている。これとともに、第１図
および第２図に示すように、上記ステム９の下側部分が
プラスチックパッケージ２の下面側に露出させられてい
る。さらに、そのステム９の下側露出面は扁平に形成さ
れ、かつこの露出面と上記リード端子３の先端位置が略
等高に揃えられている。Here, the semiconductor chip 7 is placed and fixed on the metal stem 7 within the package 2, as shown in FIG. The semiconductor chip 7 fixed to the stem 9 is connected to a large number of lead terminals 3 by bonding wires 8. As shown in FIG. 2, this large number of lead terminals 3 are distributed and led out in approximately equal numbers to the four sides of the socket cage 2. At the same time, as shown in FIGS. 1 and 2, the lower portion of the stem 9 is exposed on the lower surface side of the plastic package 2. Furthermore, the lower exposed surface of the stem 9 is formed flat, and this exposed surface and the tip position of the lead terminal 3 are aligned at approximately the same height.
上述し九半導体装＃１は、第１図に示すように、その端
子リード３およびステム９の下側露出面がそれぞれプリ
ント配線基板４の導体ランド１０面に直接ハンダ付けさ
れることにより表面実装される。５はそのハンダ付は部
分を示す。この場合、ステム９の下側露出面には、あら
かじめ銀ペーストなどを塗付してハンダ付けがしやすい
ようにしておくとよい。また、ステム９とプラスチック
パッケージ２との界面から水分などが侵入しないように
するために、そのステム９のパッケージ２で覆われる部
分には、あらかじめ適当な２イニング処理を施しておく
ことが望ましい。As shown in FIG. 1, the above-described semiconductor device #1 is surface mounted by directly soldering the lower exposed surfaces of the terminal leads 3 and stem 9 to the conductor land 10 surface of the printed wiring board 4. be done. 5 indicates the soldered part. In this case, it is preferable to apply silver paste or the like to the lower exposed surface of the stem 9 in advance to facilitate soldering. Further, in order to prevent moisture from entering through the interface between the stem 9 and the plastic package 2, it is desirable to apply an appropriate two-inning treatment to the portion of the stem 9 covered by the package 2 in advance.
以上のように構成され次半導体装置１では、半導体チッ
プ７からの発熱が、プラスチックパッケージ２に遮られ
ることなく、ステム９からプリント配線基板４へ効率良
く逃げることができる。これにより、回路機能の複雑化
および高度化に伴う多ピン化と表面実装に適合させるた
めの小型化とを両立させつつ、プラスチックパッケージ
２で封止され之多ビンの半導体装置１の放熱効果を向上
させることができるようになる。In the semiconductor device 1 configured as described above, heat generated from the semiconductor chip 7 can efficiently escape from the stem 9 to the printed wiring board 4 without being blocked by the plastic package 2. As a result, the heat dissipation effect of the multi-bin semiconductor device 1 sealed with the plastic package 2 can be improved while simultaneously increasing the number of pins due to the increasing complexity and sophistication of circuit functions and miniaturizing it to suit surface mounting. be able to improve.
第３図および第４図はこの発明の第２実施例を示す。第
３図はその第２実施例の半導体装置１を裏返し次状態を
、第４図はその実装状態における断面状態をそれぞれ示
す。3 and 4 show a second embodiment of the invention. FIG. 3 shows the semiconductor device 1 of the second embodiment after being turned over, and FIG. 4 shows the cross-sectional state of the semiconductor device 1 in its mounted state.
この第２実施例の半導体装置１では、ステム９の露出部
分にネジ穴１１が形成されている。このネジ穴１１にポ
ルト１２をプリント配線基板４ごしに螺入させることに
より、プリント配線基板４への取υ付は状態を機械的に
確実にする仁とができる。これとともに、そのネジ穴１
１に螺入されたボルト１２が一種の放熱体としても機能
することにより、放熱効果が一層向上させられるように
なる。ステム９と基板４０間には、熱伝導性を高めるた
めのシリコーングリース１３を塗っておくとよい。In the semiconductor device 1 of this second embodiment, a screw hole 11 is formed in the exposed portion of the stem 9. By screwing the port 12 into the screw hole 11 through the printed wiring board 4, the mounting on the printed wiring board 4 can be ensured mechanically. Along with this, the screw hole 1
Since the bolt 12 screwed into 1 also functions as a kind of heat radiator, the heat radiation effect can be further improved. It is preferable to apply silicone grease 13 between the stem 9 and the substrate 40 to improve thermal conductivity.
第５図および第６図はこの発明の第３実施例を示す。第
５図はその第３実施例の半導体装置１を裏返した状態を
、第６図はその実装状態における断面状態をそれぞれ示
す。5 and 6 show a third embodiment of the invention. FIG. 5 shows a state in which the semiconductor device 1 of the third embodiment is turned over, and FIG. 6 shows a cross-sectional state in its mounted state.
この第３実施例の半導体装ｆ１では、ステム９の露出部
分にボルト部１４が一体に突設されている。このボルト
部１４とナラ）１５でプリント配線基板４を挾み込むこ
とにより、半導体装置１″ｌ！ニブリント配線基板４に
機械的に確実に取り付けることができる。これとともに
、そのボルト部１４とナツト１５が良好な放熱体として
も機能することＫより、一層すぐれた放熱効果が得られ
るようになる。In the semiconductor device f1 of the third embodiment, a bolt portion 14 is integrally provided in an exposed portion of the stem 9 in a protruding manner. By sandwiching the printed wiring board 4 between the bolt part 14 and the nut 15, the semiconductor device 1'' can be mechanically and reliably attached to the printed wiring board 4. At the same time, the bolt part 14 and nut 15 also functions as a good heat dissipation body, so that an even better heat dissipation effect can be obtained.
第７図および第８図はこの発明の第４実施例を示す。第
７図はその第４実施例の半導体装置１を裏返した状態を
、第８図はその実装状態における断面状態をそれぞれ示
す。7 and 8 show a fourth embodiment of the invention. FIG. 7 shows a state where the semiconductor device 1 of the fourth embodiment is turned over, and FIG. 8 shows a cross-sectional state of the semiconductor device 1 in its mounted state.
この第４実施例の半導体装置１では、ステア４９の両端
が下方へ直角に折り曲げられ、この折り曲げ部分がプラ
スチックパッケージ２の下方へ突出して露出させられて
いる。そして、その下端がプリント配線基板４の導体ラ
ンド１ｏにハンダ付けされている。In the semiconductor device 1 of this fourth embodiment, both ends of the steer 49 are bent downward at right angles, and the bent portions protrude below the plastic package 2 and are exposed. The lower end thereof is soldered to the conductor land 1o of the printed wiring board 4.
第９図および第１０図はこの発明の第５実施例を示す。9 and 10 show a fifth embodiment of the invention.
第９図はその第５実施例の半導体装置１を裏返した状態
を、第１０図はその実装状態における断面状態をそれぞ
れ示す。この第５実施例の半導体装置１では、ステム９
の露出部分に多数の冷却フィン部が襞状に一体形成され
ている。この第５実施例の半導体装置１は、第１０図に
示すように、そのステム９の露出部分がプリント配線基
板４に穿設された窓孔１６内に嵌入させられた状態で実
装される。FIG. 9 shows a state where the semiconductor device 1 of the fifth embodiment is turned over, and FIG. 10 shows a cross-sectional state of the semiconductor device 1 in its mounted state. In the semiconductor device 1 of this fifth embodiment, the stem 9
A large number of cooling fins are integrally formed in the exposed portion of the cooling fin in the form of folds. The semiconductor device 1 of the fifth embodiment is mounted with the exposed portion of the stem 9 fitted into a window hole 16 formed in the printed wiring board 4, as shown in FIG.
第１１図はこの発明の第６実施例を示す。同図はその第
６実施例の半導体装置１の実装状態における断面状態を
示す。この第６実施例の半導体装置１では、ステム９が
プラスチックパッケージ２の上面側に露出させられてい
て、この露出部分に襞状の冷却フィン部が一体に形成さ
れている。FIG. 11 shows a sixth embodiment of the invention. This figure shows a cross-sectional state of the semiconductor device 1 of the sixth embodiment in a mounted state. In the semiconductor device 1 of this sixth embodiment, the stem 9 is exposed on the upper surface side of the plastic package 2, and a pleated cooling fin portion is integrally formed in this exposed portion.
以上の第２〜第６実施例の半導体装置１も、前述した作
用効果、すなわち半導体チッ７″７からの発熱が、プラ
スチックパッケージ２に遮られることなく、ステム９か
らプリント配線基板４へ効率良く逃げることができ、こ
れにより、回路機能の複雑化および高度化に伴う多ビン
化と表面実装に適合させるための小型化とを両立させつ
つ、プラスチックパッケージ２で封止された多ピンの半
導体装置１の放熱効果を向上させることができる。The semiconductor device 1 of the second to sixth embodiments described above also has the above-mentioned effect, that is, the heat generated from the semiconductor chip 7''7 is efficiently transferred from the stem 9 to the printed wiring board 4 without being blocked by the plastic package 2. As a result, a multi-pin semiconductor device sealed in a plastic package 2 can be realized while achieving both the increase in the number of bins due to the increasing complexity and sophistication of circuit functions and the miniaturization required for surface mounting. The heat dissipation effect of No. 1 can be improved.
以上、本発明者によってなされた発明を実施例にもとづ
き具体的に説明したが、本発明は上記実施例に限定され
るものではなく、その要旨を逸脱しない範囲で種々変更
可能であることはいうまでもない。たとえば、上記ステ
ム９ｔ−中空構造にして、その中空内部に冷却媒体液を
封入することにより一種のヒートバイブを形成させるよ
うにしてもよい。Above, the invention made by the present inventor has been specifically explained based on the examples, but it should be noted that the present invention is not limited to the above examples and can be modified in various ways without departing from the gist thereof. Not even. For example, the stem 9t may have a hollow structure, and a type of heat vibe may be formed by sealing a cooling medium liquid inside the hollow.
以上の説明では主として本発明者によってなされた発明
をその背景となっ九利用分野である多ビンのパワー系リ
ニアＩＣに適用した場合について説明しｆｃが、それに
限定されるものではなく、たとえば、消費電力の大きな
ＥＣＬ（エミッタ結合論理）が形成すれた高速論理半導
体集積回路装置などにも適用できる。少なくとも、プラ
スチックパッケージタイプで多ピンかつ表面実装用に適
合させるといり条件のものには適用できる。The above explanation mainly describes the case where the invention made by the present inventor is applied to a multi-bin power linear IC, which is the background of the invention and its field of application. It can also be applied to high-speed logic semiconductor integrated circuit devices in which ECL (emitter coupled logic) with high power is formed. At least, it can be applied to plastic package types with a large number of pins and suitable for surface mounting.
本ＭＫ、おいて開示される発明のうち代表的なものによ
って得られる効果を簡単に説明すれば、下記のとおりで
ある。A brief explanation of the effects obtained by typical inventions disclosed in this MK is as follows.
すなわち、ステムに固定された半導体チップのリード端
子をプラスチックパッケージの西側方に振シ分けて導出
させるとともに、そのステムの一部をパッケージの下面
あるいは上面から部分的に露出させるようにしたことに
より、回路機能の高度化に伴う多ビン化と表面実装に適
合させるための小型化とを両立させつつ、プラスチック
パッケージで封止された多ビンの半導体装置の放熱効果
を向上させることができるようになる、という効果が得
られる。That is, the lead terminals of the semiconductor chip fixed to the stem are distributed to the west side of the plastic package and led out, and a part of the stem is partially exposed from the bottom or top of the package. It will be possible to improve the heat dissipation effect of multi-bin semiconductor devices sealed in plastic packages, while also achieving both the increase in the number of bins due to the advancement of circuit functions and miniaturization to suit surface mounting. This effect can be obtained.
第１図はこの発明による技術が適用された半導体装置の
実装状態での断面状態を示す図、第２図は第１図に示し
た半導体装置を裏返し７−示す斜視図、
第３図はこの発明の第２実施例による半導体装置の裏側
を示す斜視図、
第４図はこの発明の第２実施例による半導体装置の実装
状態での断面状態を示す図。
第５図はこの発明の第３実施例による半導体装置の裏側
を示す斜視図、
第６図はこの発明の第３実施例による半導体装置の実装
状態での断面状態を示す図、
第７図はこの発明の第４実施例【よる半導体装置の裏側
を示す斜視図、
第８図はこの発明の第４実施例による半導体装置の実装
状態での断面状態を示す図、
第９図はこの発明の第５実施例による半導体装置の裏側
を示す斜視図、
第１０図はこの発明の第５実施例による半導体装置の実
装状態での断面状態を示す図、第１１図はこの発明の第
６実施例による半導体装置の実装状態での断面状態を示
す図、第１２図（ａ）（ｂ）はこの発明に先立って検討
された表面実装型かつプラスチックパッケージ型で多ピ
ン型の半導体装置の平面状態および断面状態を示す図、
第１３図は従来の表面実装型パワー系す＝アＩＣの構成
を示す平面図である。
１・・・表面実装型で多ビンの半導体装置、２・・・プ
ラスチックパッケージ％ ３・・・リード端子、４・・
・プリント配線基板、５・・・ハンダ付は部分、７・・
・半導体チップ、８・・・ボンディングワ・・ｆヤー、
９・・・ステム、１０・・・プリント配線基板の導体ラ
ンド。
代理人 弁理士 小 川 勝 男゛ 、ゝ・、 ′
″
第 １ 図
第 ２ 図
（１・′
第 ３ 図
第 ４ 図
策 ５ 図
第９図
９．５′
、／、７
・ｊ
第１０図
第 １１ 図FIG. 1 is a cross-sectional view of a mounted semiconductor device to which the technology of the present invention is applied, FIG. 2 is a perspective view of the semiconductor device shown in FIG. FIG. 4 is a perspective view showing the back side of a semiconductor device according to a second embodiment of the invention. FIG. 4 is a diagram showing a cross-sectional state of the semiconductor device in a mounted state according to a second embodiment of the invention. FIG. 5 is a perspective view showing the back side of a semiconductor device according to a third embodiment of the present invention, FIG. 6 is a cross-sectional view showing a mounted state of the semiconductor device according to a third embodiment of the present invention, and FIG. FIG. 8 is a perspective view showing the back side of a semiconductor device according to a fourth embodiment of the present invention; FIG. 8 is a cross-sectional view of the semiconductor device according to a fourth embodiment of the present invention in a mounted state; FIG. A perspective view showing the back side of a semiconductor device according to a fifth embodiment; FIG. 10 is a cross-sectional view of the semiconductor device according to a fifth embodiment of the present invention in a mounted state; FIG. 11 is a sixth embodiment of the present invention. Figures 12(a) and 12(b) show the planar state and cross-sectional state of a surface-mounted, plastic packaged, multi-pin semiconductor device that was studied prior to the present invention. FIG. 13 is a plan view showing the configuration of a conventional surface-mounted power system IC. 1...Surface mount type multi-bin semiconductor device, 2...Plastic package% 3...Lead terminal, 4...
・Printed wiring board, 5...soldered part, 7...
・Semiconductor chip, 8... bonding wire...
9... Stem, 10... Conductor land of printed wiring board. Agent: Patent Attorney Katsutoshi Ogawa゛,ゝ・,′
'' Figure 1 Figure 2 (1・' Figure 3 Figure 4 Scheme 5 Figure 9 Figure 9.5', /, 7 ・j Figure 10 Figure 11
Claims (1)
ックパッケージによって封止された多ピンの半導体装置
であって、上記半導体チップに接続するリード端子が上
記パッケージの四方の側面へ振り分けられて導出させら
れるとともに、上記ステムの一部がプラスチックパッケ
ージの下面あるいは上面に露出させられたことを特徴と
する半導体装置。 ２、上記ステムの一部がプラスチックパッケージの下面
に露出させられるとともに、この露出面が扁平に形成さ
れ、かつこの露出面と上記リード端子の先端位置が略等
高に揃えられていることを特徴とする特許請求の範囲第
１項記載の半導体装置。[Claims] 1. A multi-pin semiconductor device in which a semiconductor chip fixed to a stem is sealed in a flat plastic package, wherein lead terminals connected to the semiconductor chip are provided on four sides of the package. A semiconductor device characterized in that the stem is distributed and led out, and a portion of the stem is exposed on the lower surface or the upper surface of a plastic package. 2. A portion of the stem is exposed on the bottom surface of the plastic package, the exposed surface is formed flat, and the exposed surface and the tip of the lead terminal are aligned at approximately the same height. A semiconductor device according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61010089A JPS62169450A (en) | 1986-01-22 | 1986-01-22 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61010089A JPS62169450A (en) | 1986-01-22 | 1986-01-22 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62169450A true JPS62169450A (en) | 1987-07-25 |
Family
ID=11740606
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61010089A Pending JPS62169450A (en) | 1986-01-22 | 1986-01-22 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62169450A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0539095A3 (en) * | 1991-10-23 | 1994-02-16 | Fujitsu Ltd | |
| FR2724054A1 (en) * | 1994-06-09 | 1996-03-01 | Samsung Electronics Co Ltd | SEMICONDUCTOR PACKAGE MOUNTING STRUCTURE |
| EP0711104A1 (en) * | 1994-11-01 | 1996-05-08 | Mitsubishi Denki Kabushiki Kaisha | Packaged semiconductor, semiconductor device made therewith and method for making same |
| US7245004B2 (en) | 2003-05-20 | 2007-07-17 | Rohm Co., Ltd. | Semiconductor device |
-
1986
- 1986-01-22 JP JP61010089A patent/JPS62169450A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0539095A3 (en) * | 1991-10-23 | 1994-02-16 | Fujitsu Ltd | |
| US5444025A (en) * | 1991-10-23 | 1995-08-22 | Fujitsu Limited | Process for encapsulating a semiconductor package having a heat sink using a jig |
| US5659200A (en) * | 1991-10-23 | 1997-08-19 | Fujitsu, Ltd. | Semiconductor device having radiator structure |
| FR2724054A1 (en) * | 1994-06-09 | 1996-03-01 | Samsung Electronics Co Ltd | SEMICONDUCTOR PACKAGE MOUNTING STRUCTURE |
| EP0711104A1 (en) * | 1994-11-01 | 1996-05-08 | Mitsubishi Denki Kabushiki Kaisha | Packaged semiconductor, semiconductor device made therewith and method for making same |
| KR100237912B1 (en) * | 1994-11-01 | 2000-01-15 | 기타오카 다카시 | Packaged semiconductor, semiconductor device made therewith and method for making same |
| US7245004B2 (en) | 2003-05-20 | 2007-07-17 | Rohm Co., Ltd. | Semiconductor device |
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