JP2003124240A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2003124240A JP2003124240A JP2001314895A JP2001314895A JP2003124240A JP 2003124240 A JP2003124240 A JP 2003124240A JP 2001314895 A JP2001314895 A JP 2001314895A JP 2001314895 A JP2001314895 A JP 2001314895A JP 2003124240 A JP2003124240 A JP 2003124240A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- semiconductor
- resin
- semiconductor device
- wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明は、半導体装置の製造
方法に関するものであり、特に実装面積を小さくする半
導体装置の電極形成方法に係わるものである。
【０００２】
【従来の技術】従来の半導体装置の製造方法は、図３の
製造工程図および図４の各工程仕掛かり状態図に示すよ
うに、半導体基板に電極２を有する半導体ウェーハ１を
ダイシングカットして個々の半導体チップに分離する工
程、次に前記半導体チップをリードフレーム６にダイボ
ンドする工程、次に前記半導体チップ上の電極２とリー
ドフレーム６のリード部を金ワイヤー７でワイヤーボン
ドする工程、次に前記半導体チップ部とワイヤーボンド
部を樹脂４で封止する工程、次に前記リードの樹脂部４
から出た外部リード部をリードめっきする工程、次に前
記リード部を加工しカットして個々の半導体装置に分離
する工程、次に前記半導体装置を検査し且つテーピング
する工程とからなる半導体装置の製造方法であった。
【０００３】
【発明が解決しようとする課題】このような従来の半導
体装置の製造方法では、リードフレーム、ボンディング
ワイヤーの他インターポーザー・キャリアなど使用され
るパーツ点数が多い構成の半導体装置になってしまうの
で、製造工程も必然的に長くなって従って製造コスト高
となり、また小型化の実現にも限界があった。そしてま
た、このような半導体装置が使用されるユーザ側での回
路基板実装後には、機械的ストレスの回避や信頼性確保
の為に、樹脂によるアンダーフィルなどの保護が必要で
あるという手数の掛かる問題もあった。
【０００４】一方、昨今の半導体装置においては、益々
一層小型化と高信頼性が要求されていて、上述したよう
な問題のない半導体装置が切望されているのである。
【０００５】そこで、本発明が解決しようとする課題
は、使用パーツ点数が多くならず、また、ユーザでの実
装後樹脂によるアンダーフィルなど必要のないパッケー
ジ構成からなる半導体装置の製造方法を提案することに
ある。
【０００６】
【課題を解決するための手段】この課題を解決するため
に本発明は、同一面上に全ての電極を有する半導体ウェ
ーハを研磨して溝を形成する工程、次に前記電極および
溝を樹脂で封止する工程、次に前記樹脂封止部を研磨し
て前記電極の表面平坦部を露出させる工程、次に前記露
出電極面上に下面電極を形成する工程、次に前記溝およ
び下面電極が形成されたウエーハをダイシングカットし
て個々の半導体チップに分離する工程、次に前記半導体
チップを検査し且つテーピングする工程とからなる半導
体装置の製造方法である。
【０００７】このため、このようにして完成する半導体
装置は、溝により樹脂が半導体を覆う構造となり、半導
体チップの側面における半導体の露出を極力削減する作
用がある。
【０００８】
【発明の実施の形態】以下、本発明の実施の形態につい
て、図１及び図２を用いて詳しく説明する。
【０００９】（実施の形態１）図１は、本発明による一
実施の形態を示す半導体装置の製造工程図である。
【００１０】図２は、上記製造工程図の各工程での仕掛
かり状態を、ウェーハ中の一半導体素子の拡大断面図で
もって示したものであり、符号は各工程共通で、１は半
導体ウェーハ、２は電極、３は溝、４は樹脂、５は下面
電極である。
【００１１】図１の製造工程の各工程を図２の仕掛かり
断面図と共に詳しく説明すると、図２（ａ）の断面図
は、図１の「電極形成済みウェーハ」工程の説明図であ
って、直径４ｉｎ、厚み４００μｍのＳｉ半導体基板１
の片面上に、全ての電極２が形成されていて、多数個の
半導体素子からなるウェーハの中の一個の半導体素子を
示している。
【００１２】電極２のサイズは、２００μｍ×１５０μ
ｍ、電極の形成方法は真空蒸着法を用いて形成したが、
めっき法やワイヤーバンピングなどを用いてもよい。
【００１３】次に、図２（ｂ）の断面図は、図１の「溝
形成」工程の説明図であって、前記電極形成済みウェー
ハに、化学的研磨方法で各半導体素子の間に深さ約５０
μｍ、幅１５０μｍの溝３を形成する工程である。
【００１４】ここで、化学的研磨方法は薬品やガスによ
るエッチング法を採用したが、機械的研磨方法でダイシ
ングカット法を採用してもよい。
【００１５】次に、図２（ｃ）の断面図は、図１の「樹
脂封止」工程の説明図であって、前記溝３形成済みウェ
ーハの全面を樹脂４で封止する工程である。樹脂材質は
エポキシ樹脂、樹脂封止厚みは電極２厚みより大きく１
００μｍであって、封止方法は金型を用いたトランスフ
ァモールドや液状樹脂による印刷法によるものである。
【００１６】次に、図２（ｄ）の断面図は、図１の「樹
脂研磨」工程の説明図であって、前記樹脂封止済みウェ
ーハの樹脂表面をグラインダによる機械的研磨方法で研
磨して、電極２の表面平坦部を露出させた状態である。
【００１７】次に、図２（ｅ）の断面図は、図１の「下
面電極形成」工程であって、前記平坦露出電極上に下面
電極５を形成するもので、形成方法はめっき方法を採用
したが、ディップ方法でもよい。
【００１８】次に、図１の「ダイシングカット」工程
は、前記下面電極形成済みウェーハを各半導体素子１個
１個に分離する工程である。カット方法はダイヤモンド
ブレードダイシングで、カット分離された半導体素子チ
ップの大きさは、横１．０ｍｍ×縦０．５ｍｍ×厚み
０．４ｍｍである。
【００１９】そして最後の、図１の「検査／テーピン
グ」工程は、前記半導体素子チップが１個１個検査され
ながら同時にテーピング包装される工程である。
【００２０】このようにして製造される半導体チップ
は、従来の半導体パッケージに使用されるリードフレー
ム、ワイヤーの他インターポーザー・キャリアなどを一
切使用せずにパッケージが構成されるので、使用パーツ
点数が少ないパッケージ構成になり、低コスト化と小型
化を実現できる。
【００２１】また、このような半導体チップは、ユーザ
側でプリント基板に表面実装される際、図５に断面図で
示したようなインターポーザー８を介して基板１０には
んだ付け後樹脂によるアンダーフィル９を施して補強し
ている現状を、図６に断面図で示したようにインターポ
ーザーもアンダーフィルも必要ない状態の実装方法に改
善できるので、本チップを使用する部品実装メーカーに
とって作業能率が大きくアップでき、コスト低減を実現
できる。
【００２２】なお、以上の説明ではダイオードの２端子
で構成したものを示したが、その他の半導体装置につい
ても同様に実施可能である。
【００２３】
【発明の効果】以上のように本発明の半導体装置の製造
方法によれば、同一面上に全電極を有する半導体ウェー
ハに、溝を形成した後、樹脂封止を行い、その後電極の
平坦部を露出させ、この電極上に下面電極を形成し、そ
の後ダイシングカットにより個々に分離、検査およびテ
ーピングを行い半導体素子を製造し半導体装置を形成す
る製造方法であるから、従来の半導体パッケージに使用
されるリードフレーム、ワイヤーの他インターポーザー
・キャリアなどを一切使用せずにパッケージが構成でき
ると共に、下面に下面電極のみが露出する構造の為、ユ
ーザでの実装後、樹脂によるアンダーフィルなどが不要
になるなど、メーカー、ユーザー両方にとって大変有利
な効果をもたらす発明である。Description: BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming an electrode of a semiconductor device which reduces a mounting area. 2. Description of the Related Art A conventional method for manufacturing a semiconductor device is to dice a semiconductor wafer 1 having an electrode 2 on a semiconductor substrate, as shown in a manufacturing process diagram of FIG. A step of cutting and separating into individual semiconductor chips, then a step of die-bonding the semiconductor chip to a lead frame 6, and then wire bonding the electrodes 2 on the semiconductor chip and the leads of the lead frame 6 with gold wires 7. A step of sealing the semiconductor chip portion and the wire bond portion with a resin 4;
A step of lead plating an external lead portion coming out of the semiconductor device, then a step of processing and cutting the lead portion to separate the semiconductor device into individual semiconductor devices, and a step of inspecting and taping the semiconductor device. It was a manufacturing method. [0003] In such a conventional method for manufacturing a semiconductor device, a semiconductor device having a large number of parts used, such as a lead frame, a bonding wire, and an interposer carrier, is obtained. As a result, the manufacturing process is inevitably lengthened, so that the manufacturing cost is increased, and there is a limit in realizing miniaturization. In addition, after mounting the circuit board on the user side in which such a semiconductor device is used, it is troublesome to protect the resin from underfill or the like in order to avoid mechanical stress and secure reliability. There were also problems. On the other hand, in recent semiconductor devices, further miniaturization and higher reliability have been demanded, and a semiconductor device which does not have the above-mentioned problems has been eagerly desired. Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device having a package structure in which the number of parts used does not increase and the user does not need to underfill with resin after mounting. It is in. SUMMARY OF THE INVENTION In order to solve this problem, the present invention provides a method of forming a groove by polishing a semiconductor wafer having all electrodes on the same surface, and then forming the electrode and the groove. A step of exposing a flat surface portion of the electrode by polishing the resin sealing portion, then a step of forming a lower surface electrode on the exposed electrode surface, then the groove and A method for manufacturing a semiconductor device, comprising: a step of dicing and cutting a wafer on which a lower electrode is formed to separate the wafer into individual semiconductor chips; and a step of inspecting and taping the semiconductor chips. For this reason, the semiconductor device completed in this way has a structure in which the resin covers the semiconductor with the groove, and has an effect of minimizing the exposure of the semiconductor on the side surface of the semiconductor chip. An embodiment of the present invention will be described below in detail with reference to FIGS. 1 and 2. (First Embodiment) FIG. 1 is a manufacturing process diagram of a semiconductor device according to an embodiment of the present invention. FIG. 2 shows an in-process state in each step of the above-mentioned manufacturing process diagram in an enlarged cross-sectional view of one semiconductor element in the wafer. 2 is an electrode, 3 is a groove, 4 is a resin, and 5 is a lower surface electrode. Each step of the manufacturing process shown in FIG. 1 will be described in detail with reference to the in-process cross-sectional view of FIG. 2. The cross-sectional view of FIG. Semiconductor substrate 1 having a diameter of 4 inches and a thickness of 400 μm
All the electrodes 2 are formed on one surface of the wafer, and one semiconductor element in a wafer composed of a large number of semiconductor elements is shown. The size of the electrode 2 is 200 μm × 150 μm.
m, the electrode was formed using a vacuum deposition method,
A plating method, wire bumping, or the like may be used. FIG. 2B is a sectional view of the "groove forming" step shown in FIG. 1. The wafer having the electrodes formed thereon is deeply interposed between the semiconductor elements by a chemical polishing method. About 50
In this step, a groove 3 having a width of 150 μm is formed. Here, the chemical polishing method is an etching method using a chemical or a gas, but a dicing cut method may be used as a mechanical polishing method. Next, the cross-sectional view of FIG. 2C is an explanatory view of the “resin sealing” step of FIG. 1 and is a step of sealing the entire surface of the wafer having the groove 3 formed therein with the resin 4. . Resin material is epoxy resin, resin sealing thickness is larger than electrode 2 thickness 1
The sealing method is a transfer mold using a mold or a printing method using a liquid resin. FIG. 2D is a cross-sectional view of the "resin polishing" step shown in FIG. 1. The resin surface of the resin-sealed wafer is polished by a mechanical polishing method using a grinder. Thus, a flat surface portion of the electrode 2 is exposed. Next, the cross-sectional view of FIG. 2 (e) shows the "lower electrode forming" step of FIG. 1, in which the lower electrode 5 is formed on the flat exposed electrode. Although adopted, a dip method may be used. Next, the "dicing cut" step of FIG. 1 is a step of separating the wafer on which the lower electrode has been formed into individual semiconductor elements. The cutting method is diamond blade dicing, and the size of the semiconductor element chip cut and separated is 1.0 mm wide × 0.5 mm long × 0.4 mm thick. Finally, the "inspection / taping" step of FIG. 1 is a step in which the semiconductor element chips are inspected one by one and simultaneously taped and packaged. The semiconductor chip manufactured in this way is packaged without using any interposer carrier other than the lead frame and wires used in the conventional semiconductor package. The package configuration is small, so that cost reduction and miniaturization can be realized. When such a semiconductor chip is surface-mounted on a printed circuit board on the user side, the semiconductor chip is soldered to the board 10 via an interposer 8 as shown in the sectional view of FIG. As shown in the cross-sectional view of FIG. 6, the current situation of reinforcement by applying 9 can be improved to a mounting method that does not require an interposer or an underfill. The cost can be greatly increased and the cost can be reduced. Although the above description has been made with reference to a configuration including two terminals of a diode, the present invention can be similarly applied to other semiconductor devices. As described above, according to the method of manufacturing a semiconductor device of the present invention, after a groove is formed in a semiconductor wafer having all electrodes on the same surface, resin sealing is performed, and then the electrode is formed. Is a manufacturing method in which a lower surface electrode is formed on this electrode, and then separated, inspected and taped individually by dicing cut to manufacture a semiconductor element to form a semiconductor device. The package can be configured without using any interposer / carrier other than the lead frame and wire used for the device, and the structure where only the lower electrode is exposed on the lower surface allows for underfill with resin after mounting by the user. This is an invention that has a very advantageous effect for both manufacturers and users, such as eliminating the need for.
【図面の簡単な説明】
【図１】本発明の一実施の形態による半導体装置の製造
工程図
【図２】（ａ）は、「電極形成済みウェーハ」工程での
仕掛かり状態でウェーハの中の一半導体素子の断面図
（ｂ）は、「溝形成」工程での仕掛かり状態で、同様に
一半導体素子の断面図
（ｃ）は、「樹脂封止」工程での仕掛かり状態で、同様
一素子の断面図
（ｄ）は、「樹脂研磨」工程での仕掛かり状態で、同様
一素子の断面図
（ｅ）は、「下面電極形成」工程での仕掛かり状態で、
一素子の断面図
【図３】従来における半導体装置の製造工程図
【図４】（ａ）は、「ダイシングカット」工程の仕掛か
り状態で、ウェーハからカットされた一半導体素子の断
面図
（ｂ）は、「ダイボンド」工程の仕掛かり状態で、同様
に一素子の断面図
（ｃ）は、「ワイヤーボンド」工程の仕掛かり状態で、
同様一素子の断面図
（ｄ）は、「樹脂封止」工程の仕掛かり状態で、同様一
半導体素子の断面図
【図５】インターポーザーを介して基板にはんだ付け後
アンダーフィルを施して補強している現状断面図
【図６】インターポーザーもアンダーフィルも必要ない
本発明半導体装置使用の実装断面図
【符号の説明】
１ 半導体ウェーハ
２ 電極
３ 溝
４ 樹脂
５ 下面電極BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a view showing a manufacturing process of a semiconductor device according to an embodiment of the present invention. FIG. 2 (a) shows an in-process wafer in an “electrode-formed wafer” process. A cross-sectional view (b) of one semiconductor element is a state in progress in a “groove formation” step, and a cross-sectional view (c) of one semiconductor element is a state in progress in a “resin sealing” step. Similarly, a cross-sectional view (d) of one element is a state in progress in a “resin polishing” process, and a cross-sectional view (e) of the same element is a state in progress in a “formation of lower electrode” step.
FIG. 3A is a cross-sectional view of one semiconductor element cut from a wafer in a state in which a “dicing cut” process is in progress, and FIG. ) Is the state in process of the “die bonding” step, and similarly, the cross-sectional view of one element is the state in progress of the “wire bonding” step.
Similarly, the cross-sectional view (d) of one element is a cross-sectional view of the same semiconductor element in a state of the "resin sealing" process in progress. [FIG. 5] Reinforcement by soldering to a substrate via an interposer and then underfilling [FIG. 6] Mounting cross-sectional view using the semiconductor device of the present invention which does not require an interposer or underfill [Description of reference numerals] 1 Semiconductor wafer 2 Electrode 3 Groove 4 Resin 5 Lower electrode
Claims (1)
ーハを研磨して溝を形成する工程、次に前記電極および
溝を樹脂で封止する工程、次に前記樹脂封止部を研磨し
て前記電極の表面平坦部を露出させる工程、次に前記露
出電極面上に下面電極を形成する工程、次に前記溝およ
び下面電極が形成されたウエーハをダイシングカットし
て個々の半導体チップに分離する工程、次に前記半導体
チップを検査し且つテーピングする工程とからなること
を特徴とする半導体装置の製造方法。Claims: 1. A step of forming a groove by polishing a semiconductor wafer having all electrodes on the same surface, a step of sealing the electrode and the groove with a resin, and a step of sealing the resin with the resin. Polishing a sealing portion to expose a flat surface of the electrode, then forming a lower surface electrode on the exposed electrode surface, and then dicing and cutting the wafer on which the groove and the lower surface electrode are formed. A method of manufacturing a semiconductor device, comprising: a step of separating the semiconductor chips into individual semiconductor chips; and a step of inspecting and taping the semiconductor chips.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001314895A JP2003124240A (en) | 2001-10-12 | 2001-10-12 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001314895A JP2003124240A (en) | 2001-10-12 | 2001-10-12 | Method for manufacturing semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2003124240A true JP2003124240A (en) | 2003-04-25 |
Family
ID=19133141
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001314895A Pending JP2003124240A (en) | 2001-10-12 | 2001-10-12 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2003124240A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100419981C (en) * | 2004-05-28 | 2008-09-17 | 株式会社迪斯科 | Processing method for forming electrode on plate-shape article |
-
2001
- 2001-10-12 JP JP2001314895A patent/JP2003124240A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100419981C (en) * | 2004-05-28 | 2008-09-17 | 株式会社迪斯科 | Processing method for forming electrode on plate-shape article |
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