JPS594146A - Package for semiconductor device - Google Patents

Package for semiconductor device

Info

Publication number
JPS594146A
JPS594146A JP11325482A JP11325482A JPS594146A JP S594146 A JPS594146 A JP S594146A JP 11325482 A JP11325482 A JP 11325482A JP 11325482 A JP11325482 A JP 11325482A JP S594146 A JPS594146 A JP S594146A
Authority
JP
Japan
Prior art keywords
base
dielectric substrate
strip line
metallized film
dielectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11325482A
Other languages
Japanese (ja)
Other versions
JPH0340951B2 (en
Inventor
Norio Hidaka
日高 紀雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11325482A priority Critical patent/JPS594146A/en
Publication of JPS594146A publication Critical patent/JPS594146A/en
Publication of JPH0340951B2 publication Critical patent/JPH0340951B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/66High-frequency adaptations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Waveguides (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To enable to prevent the production of a parasitic capacity by placing a dielectric substrate and an electric terminal base on the same plane, thereby eliminating the stepwise diffeence of both. CONSTITUTION:An electric terminal 4 has a dielectric base 4A which has the same thickness as a dielectric substrate 3, and a electric piece 4B which is integrated with the base 4A provided in the vicinity of the laminated part 67 of a metallized film of the base 4A, and placed fixedly on the same surface as the surface, to which the substrate 3 is secured. The substrate 3 and the terminal 4 are provided on the same surface of a metal base 1, and since there is no stepwise difference therebetween, no parasitic capacity is produced. Accordingly, it can exhibit excellent high frequency characteristics even in the frequency equal to or higher than Ku band.

Description

【発明の詳細な説明】 発明の技術分野 本発明は、擬似同軸線路及びストリップ線路を有し、超
高周波帯で使用するのに好適な半導体装(1) 開用パッケージに関する。
DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a semiconductor device (1) that has a pseudo-coaxial line and a strip line and is suitable for use in an ultra-high frequency band.

近年、GaAs−FET等の半導体素子及びこれ等を用
いた超小型、高性能のマイクロ波増幅回路等が実現され
、それと同時にそれ等素子、回路等を収容するパッケー
ジも開発されている。そして、該パッケージの内部寸法
は6x6x2 (■l〕と極めて小型であり、また、適
応周波数はKu帯にまで及ぶ高性能なものである。
In recent years, semiconductor devices such as GaAs-FETs and ultra-small, high-performance microwave amplifier circuits using these devices have been realized, and at the same time, packages that accommodate these devices, circuits, etc. have also been developed. The internal dimensions of the package are extremely small, 6x6x2 (■l), and the applicable frequency is high-performance, extending to the Ku band.

第1図は従来例の要部切断斜面図、第2図は要部正面図
、第3図は要部切断側面図であり、■は銅製基台、2は
銅製フレーム、3はサファイア板4は電気端子、41よ
電気端子4を構成するアルミナ基体、4Bは電気端子4
を構成するアルミナ駒体5はメタライズ膜のラミネート
部分、6.7はストリップ線路、8はサファイア板上に
形成されたストリップ線路、9はストリップ線路7とス
トリップ線路9とを結ぶ金のリボン、10は段差をそれ
ぞれ示している。
Fig. 1 is a cut-away slope view of the main part of the conventional example, Fig. 2 is a front view of the main part, and Fig. 3 is a cut-away side view of the main part. is an electrical terminal, 41 is an alumina base forming the electrical terminal 4, and 4B is an electrical terminal 4.
The alumina piece body 5 constituting the is a laminated part of a metallized film, 6.7 is a strip line, 8 is a strip line formed on a sapphire plate, 9 is a gold ribbon connecting the strip line 7 and the strip line 9, 10 indicates each level difference.

このパッケージに於けるサファイア板3は厚さ0.3 
 (n)であって、その上表面には増幅回路の(2) 50〔Ω〕ストリップ線路8が形成されている。
The thickness of the sapphire plate 3 in this package is 0.3
(n), on the upper surface of which a (2) 50 [Ω] strip line 8 of an amplifier circuit is formed.

また、電気端子41,1、厚さ0.6〔量目〕、長さ1
〔酊〕の基体心に低抵抗率のタングステン・ベース1を
用いてメタライズ膜のパターンを形成し、その」−に厚
さ0.6  (mm) 、長さ0.5  Cx劇〕の駒
体旧(をラミネーi・し、メタライズ膜に於けるラミネ
ートされていない部分に金鍍金して50 CΩ〕のスI
・リップ線路6,7を形成し、全体の側周にはメタライ
ズ膜を形成したものである。そして、この電気端子4は
基台1及びフレーム2に形成された穴若しくは切欠きに
嵌挿され、前記側周に形成されたメタライズ膜を介して
固着される。この構成に依り、電気端子4に於ける基体
4Aと駒体4Bとがラミネートされた部分でば周囲が基
台1及びフレーム2で囲まれた状態となっていて、基台
1及びフレーム2を外導体、メタライズ膜のラミネート
部分5を内導体、基体4A及び駒体4Bを誘電体とする
擬似同軸線路と見ることができる。しかも、その擬似同
軸線路の両外方にはスI−IJツブ線路6゜7が連なる
構成となっている。
Also, electric terminal 41,1, thickness 0.6 [weight], length 1
A pattern of metallized film is formed using a low resistivity tungsten base 1 on the base center of the [drink], and a piece body with a thickness of 0.6 (mm) and a length of 0.5 Cx is formed on the base. Laminate the old metallized film and plate the non-laminated parts of the metallized film with gold to a resistance of 50 CΩ.
- Lip lines 6 and 7 are formed, and a metallized film is formed on the entire side periphery. The electrical terminal 4 is fitted into a hole or notch formed in the base 1 and the frame 2, and is fixed via a metallized film formed on the side periphery. With this configuration, the portion of the electrical terminal 4 where the base body 4A and the piece body 4B are laminated is surrounded by the base 1 and the frame 2. It can be seen as a pseudo-coaxial line in which the outer conductor and the laminated portion 5 of the metallized film are the inner conductor, and the base body 4A and the bridge body 4B are the dielectric bodies. In addition, the pseudo-coaxial line has a configuration in which a series of I-IJ tubular lines 6.7 are connected on both sides of the pseudo-coaxial line.

(3) サファイア板3と電気端子4の基体4八とは厚さが相違
しているが、基台1を切削して適切な段差10を形成し
であるので、サファイア板3と電気端子4とを配設した
場合にはサファイア板3と基体4への各上表面ば同一面
をなし、従って、ストリップ線路7とストリップ線17
Nとをリボンって結合することは容易である。
(3) Although the thickness of the sapphire plate 3 and the base 48 of the electric terminal 4 are different, since the base 1 is cut to form an appropriate step 10, the sapphire plate 3 and the base 48 of the electric terminal 4 are different in thickness. When the upper surfaces of the sapphire plate 3 and the substrate 4 are arranged on the same surface, the strip line 7 and the strip line 17 are disposed on the same surface.
It is easy to combine N with a ribbon.

このパッケージは、I(ui4′までの周波数に於いて
は、挿入損失、電[1:定在波比は極めて少なく、その
特性は優秀である。
This package has excellent characteristics, with extremely low insertion loss and electric [1:standing wave ratio] at frequencies up to I(ui4').

しかしながら、それもKI+帯迄であって、それを越え
る周波数になると、前記段差IOの部分で発生する電界
の乱れが無視できなくなり、第4図に見られるように、
50〔Ω〕ストリップ線路11に寄4ト容量12が挿入
されたことになり、前記段差10の部分で電力の反射及
び電力のmi失が起きる。
However, this is up to the KI+ band, and when the frequency exceeds this, the disturbance of the electric field generated at the step IO cannot be ignored, and as shown in Fig. 4,
This means that a bias capacitor 12 is inserted into the 50 [Ω] strip line 11, and power reflection and power loss occur at the step 10.

電気端子4の基体4AはFET等の半導体素子に用いら
れる規格品パッケージのそれにオ【らい0.6〔11〕
の厚さとし、また、サファイア板3も電気的な要請及び
規格品であるところから厚さ0.3(4) 〔1戴〕のものを使用している。
The base 4A of the electrical terminal 4 has a radius of 0.6 [11] that is equivalent to that of a standard package used for semiconductor elements such as FETs.
Furthermore, the sapphire plate 3 has a thickness of 0.3 (4) [1 dia] due to electrical requirements and is a standard product.

発明の目的 本発明は、前記段差に起因する寄生容量の発生を防11
ニジて、Ku帯以」−の周波数に於いても電力の反射及
び電力のtH失を生じないパッケージを櫂供しようとす
るものである。
Purpose of the Invention The present invention provides a method for preventing the generation of parasitic capacitance due to the step difference.
In addition, the present invention attempts to provide a package that does not cause power reflection or power loss even at frequencies above the Ku band.

発明の実施例 第5図及び第6図は本発明一実施例の要部切断側面図及
び要OR切断正面図であり、第1図乃至第3図に関して
説明した部分と同部分は同記号で指示しである。
Embodiment of the Invention FIGS. 5 and 6 are a cross-sectional side view and an OR-cut front view of an embodiment of the present invention, and the same parts as those explained with respect to FIGS. 1 to 3 are designated by the same symbols. It is an instruction.

本実施例では、電気端子4に於ける基体4への厚さが→
Jファイア板3のそれと同一であり、従って、第3図に
見られる如き基台1の段差10は不要であるから、第4
図に見られる寄生容し12が発生する余地はない。
In this embodiment, the thickness of the electrical terminal 4 to the base 4 is →
Since it is the same as that of the J-fire plate 3, and therefore the step 10 of the base 1 as seen in FIG. 3 is unnecessary, the fourth
There is no room for the parasitic cavities 12 seen in the figure to occur.

基体4への厚さをサファイア板3のそれと同じく0.3
〔■禦〕とすると、擬似同軸線路を構成する関係ト、駒
体4Bの厚さも0.3  〔+n)としなければならな
い。駒体413が薄くなることは、パッケージと(5) して基体心から十の高さが低くなることであり、これは
パッケージを複数個連結する際に有用である。即ち、そ
の場合は電気端子4同志が対向するようにパッケージを
並列させて衝合し、ストリップ線1736.6の間をボ
ンディングすることになるが、そのようにすると、パッ
ケージに於けるフレーム2,2の間隔は僅か0. 5 
(mi)であるから、そこにボンディングの為の治具を
挿入することは容易な作業ではない。従って、前記のよ
うに、基体4^から上の高さが低くなることはボンディ
ング作業を極めて容易にする。
The thickness of the substrate 4 is 0.3, which is the same as that of the sapphire plate 3.
[■], the thickness of the related piece 4B constituting the pseudo-coaxial line must also be 0.3 [+n]. When the piece 413 becomes thinner, the height of the package (5) from the base center becomes lower, which is useful when connecting a plurality of packages. That is, in that case, the packages are arranged in parallel and abutted so that the electrical terminals 4 face each other, and bonding is performed between the strip wires 1736.6. The interval between 2 is only 0. 5
(mi), it is not an easy task to insert a jig for bonding there. Therefore, as described above, the reduced height above the base 4^ greatly facilitates the bonding operation.

ところで、電気端子4に於ける[偏量軸線路及びストリ
ップ線路6,7の特性インピーダンスは、メタライズ膜
のラミネート部分5 (内導体)の幅とストリップ線路
6.7の幅と基体4A及び駒体4Bの幅に依存する。
By the way, the characteristic impedance of the eccentric axis line and the strip line 6, 7 at the electric terminal 4 is determined by the width of the laminated portion 5 (inner conductor) of the metallized film, the width of the strip line 6.7, the base body 4A, and the bridge body. It depends on the width of 4B.

今、基体4^、駒体4Bの厚さが0.3  (mm)で
あるとすると、50〔Ω〕の特性インピーダンスとする
には、メタライズ膜のラミネート部分5の幅は約0.1
5(mt)及びストリップ線路6,7の幅は約(6) 0.2  (m+i)程度である。しかしながら、それ
等の幅を狭くするとマイクロ波の電力t1失は大になる
から無条件に狭くすることはできない。常用の装置では
、ラミネート部分5の幅として0.2  (m■〕、ス
トリップ線路6.7の幅として0.25(mm)は欲し
いところである。そのようにして、なお且つ、50〔Ω
〕の特性インピーダンスを維持するには、基体4A及び
駒体4nの幅を大にしなければならず、その為、本実施
例では、第6図に表されているように正面から見ると長
方形をなしている。
Now, assuming that the thickness of the base body 4^ and the piece body 4B is 0.3 (mm), the width of the laminated portion 5 of the metallized film is approximately 0.1 mm in order to obtain a characteristic impedance of 50 [Ω].
5 (mt) and the width of the strip lines 6 and 7 is approximately (6) 0.2 (m+i). However, if these widths are narrowed, the loss of microwave power t1 increases, so they cannot be made narrower unconditionally. In a commonly used device, the width of the laminate portion 5 should be 0.2 (m), and the width of the strip line 6.7 should be 0.25 (mm).
] In order to maintain the characteristic impedance of I am doing it.

発明の効果 本発明パッケージでは、金属フレームを有し目。Effect of the invention The package of the present invention has a metal frame and an eye.

つ少なくとも表面にストリップ線路が設けられた誘電体
基板を収容固着した金属基台と、表面に擬似同軸線路の
内導体となるメタライズ膜のラミネート部分及び該ラミ
ネート部分の両端から延在するストリップ線路が形成さ
れ且つ前記誘電体基板と同じ厚さを有する誘電体基体と
その基体に於ける前記メタライズ膜のラミネート部分近
傍に設けられ前記基体と一体化された誘電体駒体とを有
しく7) 前記誘電体基板が固着されている面上同一面に載置固着
されている電気端子とを備えている構造になっているの
で、前記誘電体基板と前記電気端子の基体とは金属基台
の同一面上にあり、その間に段差は存在しないから寄生
容量は発生しない。従って、Ku帯以ヒの周波数でも優
れた高周波特性を示し、超高周波リニア集積回路装置用
のみならず、超高速ディジタル集積回路装置用としても
有効である。そして、電気端子に於&Jる基体が薄くな
ったことに起因して、駒体も薄くなるので、パソゲージ
として、基体から上の高さが低くなり、パ・7ケージを
複数量連結する際の作業が容易となるんI果もある。
A metal base that houses and fixes a dielectric substrate having at least a strip line on its surface, a laminate part of a metallized film that becomes the inner conductor of the pseudo-coaxial line on the surface, and a strip line extending from both ends of the laminate part. 7) The dielectric body has a dielectric base formed and has the same thickness as the dielectric substrate, and a dielectric piece provided in the vicinity of the laminated portion of the metallized film on the base and integrated with the base 7). Since the structure is such that the electrical terminals are placed and fixed on the same surface on which the dielectric substrate is fixed, the dielectric substrate and the base of the electrical terminals are on the same surface of the metal base. Since it is on a plane and there is no step between them, no parasitic capacitance occurs. Therefore, it exhibits excellent high frequency characteristics even at frequencies below the Ku band, and is effective not only for ultrahigh frequency linear integrated circuit devices but also for ultrahigh speed digital integrated circuit devices. As the base that connects the electrical terminals becomes thinner, the piece also becomes thinner, so the height above the base becomes lower as a PASO gauge, making it difficult to connect multiple PA-7 cages. It also has the effect of making the work easier.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来例の要部切断斜面図、第2図は要部正面図
、第3図は要部切断側面図、第4図ぼ等価回路図、第5
図は本発明一実施例の要部切断側面図、第6図は同じく
要部切断正面図である。 図に於いて、1は銅製基台、2ば銅製フレーム、3はサ
ップイア板、4は電気端子、4Aは電気端子(8) 4を構成するアルミナ基体、4Bは電気端子4を構成す
るアルミナ駒体、5はメタライズ膜のラミネート部分、
6.7はストリップ線路、8はサップイア板」−に形成
されたストリップ線路、9はストリップ線路7とストリ
ップ線路9とを結ぶ金のリボンである。 特許出願人   冨士道株式会社 代理人弁理士  工具 久五部 (外3名) (9) 第  1  図 第2図 第3図
Fig. 1 is a cut-away slope view of the main part of the conventional example, Fig. 2 is a front view of the main part, Fig. 3 is a cut-away side view of the main part, Fig. 4 is an equivalent circuit diagram, and Fig. 5 is a cut-away side view of the main part.
The figure is a cutaway side view of the main part of an embodiment of the present invention, and FIG. 6 is a cutaway front view of the main part. In the figure, 1 is a copper base, 2 is a copper frame, 3 is a supia board, 4 is an electrical terminal, 4A is an alumina base that makes up the electrical terminal (8) 4, and 4B is an alumina piece that makes up the electrical terminal 4. body, 5 is the laminated part of the metallized film,
6.7 is a strip line, 8 is a strip line formed on a Sapphire board, and 9 is a gold ribbon connecting the strip line 7 and the strip line 9. Patent applicant Fujido Co., Ltd. Agent Patent attorney Tools Kugobe (3 others) (9) Figure 1 Figure 2 Figure 3

Claims (1)

【特許請求の範囲】[Claims] 金属フレームを有し且つ少なくとも表面にストリップ線
路が設けられた誘電体基板を収容固着した金属基台と、
表面に擬似同軸線路の内導体となるメタライズ膜のラミ
ネート部分及び該ラミネート部分の両端から延在するス
トリップ線路が形成され且つ前記誘電体基板と同じ厚さ
を有する誘電体基体とその基体に於ける前記メタライズ
膜のラミネート部分近傍に設けられ前記基体と一体化さ
れた誘電体駒体とを有し前記誘電体基板が固着されてい
る面と同一面に載置固着されている電気端子とを備えて
なることを特徴とする半導体装置用パンケージ。
a metal base having a metal frame and housing and fixing a dielectric substrate having at least a strip line on its surface;
A dielectric substrate having a laminated portion of a metallized film serving as an inner conductor of a pseudo-coaxial line on its surface and a strip line extending from both ends of the laminated portion and having the same thickness as the dielectric substrate; A dielectric piece body provided near the laminated portion of the metallized film and integrated with the base body, and an electric terminal placed and fixed on the same surface as the surface to which the dielectric substrate is fixed. A pancage for semiconductor devices characterized by the following features:
JP11325482A 1982-06-30 1982-06-30 Package for semiconductor device Granted JPS594146A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11325482A JPS594146A (en) 1982-06-30 1982-06-30 Package for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11325482A JPS594146A (en) 1982-06-30 1982-06-30 Package for semiconductor device

Publications (2)

Publication Number Publication Date
JPS594146A true JPS594146A (en) 1984-01-10
JPH0340951B2 JPH0340951B2 (en) 1991-06-20

Family

ID=14607483

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11325482A Granted JPS594146A (en) 1982-06-30 1982-06-30 Package for semiconductor device

Country Status (1)

Country Link
JP (1) JPS594146A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04126709U (en) * 1991-05-10 1992-11-18 日本スピンドル製造株式会社 Air filter mounting structure

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101491513B1 (en) * 2014-07-07 2015-02-09 문지훈 Pavement maintenance units

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04126709U (en) * 1991-05-10 1992-11-18 日本スピンドル製造株式会社 Air filter mounting structure

Also Published As

Publication number Publication date
JPH0340951B2 (en) 1991-06-20

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