JP2004349550A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device for easily and efficiently forming a semiconductor chip made into a thin layer, where a trench is formed, from a wafer, and the semiconductor device manufactured by the manufacturing method. <P>SOLUTION: Dry etching for forming the trench on the surface on a semiconductor element forming side of the wafer 1 and dry etching for making the entire back surface of the wafer 1 into the thin layer are simultaneously performed in the same atmosphere. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a step of separating a wafer on which a plurality of semiconductor elements are formed into individual semiconductor chips having a predetermined thickness and forming wiring connection trenches in the semiconductor chip.
[0002]
[Prior art]
A semiconductor device is formed by using a known technique such as diffusion, photolithography, etching, CVD, or PVD to form a semiconductor element on a semiconductor wafer (usually referred to as a first half step). It can be broadly divided into a step of cutting the semiconductor chip into pieces, dividing the chip, and connecting a lead frame, TAB, or the like to the semiconductor chip to form a package (usually called a latter half step).
In order to reduce the manufacturing cost of semiconductor devices, in the first half of the process, the size of semiconductor elements is reduced and the diameter of wafers is increased to improve the number of semiconductor chips per wafer. In the latter half of the process, bare chip mounting without the use of a mold and improvement in mounting density is performed.
[0003]
In recent years, with the speeding up of logic devices and the miniaturization of electronic devices, system-in-package (SIP) technology for mounting a plurality of semiconductor chips in one package has been spreading. In particular, it is said that it is more advantageous in terms of coping with high speed than a conventional individual package for each chip or a system-on-chip (SOC) in which a plurality of chip functions are integrated into one chip. It is also advantageous for shortening the device design / prototyping period and improving the yield in the first half of the process by reducing the size of the semiconductor chip, and is attracting much attention.
[0004]
In the latter half of the conventional process, individual semiconductor chips were obtained by grinding the back surface of the wafer with a grindstone and thinning (mechanical polishing) to a predetermined thickness, and cutting and dividing by dicing. .
However, with the increase in the diameter of the wafer and the thinning of the semiconductor chips, when the above-described thinning / dividing method is used, chipping due to micro cracks generated on the ground surface and chipping due to dicing are likely to occur, resulting in a decrease in bending strength. It was connected. Further, the distance between semiconductor chips for dicing (scribe line width) cannot be reduced.
[0005]
To solve these problems, a resist pattern is provided on the wafer surface and dry etching is performed to form a trench for chip division or chip connection (for example, see Patent Document 1). 2. Description of the Related Art There is known a method of thinning a layer to a predetermined thickness by etching (for example, see Patent Documents 2, 3, and 4).
[0006]
[Patent Document 1]
JP 2002-25948 A [Patent Document 2]
JP 2001-257186 A [Patent Document 3]
JP 2001-257247 A [Patent Document 4]
JP 2001-257248 A
[Problems to be solved by the invention]
However, in the method of Patent Document 1, it is necessary to mechanically polish the back surface of the wafer for chip division and thinning, and the bending strength due to chipping is still likely to decrease.
Further, in the methods of Patent Documents 2, 3, and 4, the bending strength is still likely to be reduced due to chipping by mechanical polishing. In addition, a back grinding tape needs to be attached to the front surface of the wafer during mechanical polishing, and a dicing tape needs to be attached to the back surface of the wafer during dicing. Further, between the steps of dry etching, mechanical polishing, and dicing, the wafer needs to be transferred between vacuum and atmosphere, and the wafer is easily cracked during the transfer.
[0008]
One of the main objects of the present invention is to provide a method of manufacturing a semiconductor device for easily and efficiently forming a thinned and trenched semiconductor chip from a wafer, and a method of manufacturing a semiconductor device manufactured by the method. The purpose is to provide.
[0009]
[Means for Solving the Problems]
Thus, according to the present invention, the dry etching for forming the chip dividing trench and / or the wiring connecting trench on the surface of the semiconductor element formation side of the wafer is the same as the dry etching for thinning the entire back surface of the wafer. A method of manufacturing a semiconductor device is provided that is performed simultaneously in an atmosphere.
[0010]
Here, in the present invention, examples of the semiconductor device include a semiconductor device such as a transistor, a diode, a capacitor, a resistor, a wiring, and an inductor, or a chip-shaped semiconductor device in which a circuit in which these semiconductor devices are combined is formed.
In the present invention, the trench on the wafer surface formed by dry etching is at least one of a chip dividing trench, a wiring connecting trench, and a capacitor forming trench, and two or more of these various trenches are used. You may make it form simultaneously.
[0011]
According to the present invention, the number of semiconductor chips per wafer can be improved by reducing the interval (scribe line width) between regions corresponding to a plurality of chips before division on the wafer surface, and chipping by mechanical polishing or dicing can be prevented. And yield can be improved. Further, it is possible to simultaneously form a wiring connection trench and a capacitor formation trench at the same time as the individualization and thinning of the semiconductor chip, thereby improving the production efficiency of the semiconductor device. That is, high-density and high-performance semiconductor chip mounting by thinning and laminating semiconductor chips can be realized with high productivity.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
In the method for manufacturing a semiconductor device according to the present invention, a desired semiconductor element, an electrode, and the like are formed in a plurality of chip-equivalent regions on a wafer surface by a known semiconductor first half process, and a passivation film is formed in a region other than the electrode. Can be. Before the subsequent dry etching, a resist film is formed on the surfaces of the electrodes and the passivation film by using a known photolithography technique, and a position for forming a chip dividing trench on the surface of the resist film and a wiring connection. The resist opening may be formed in at least one of the position where the trench for forming the capacitor and the position where the trench for forming the capacitor is formed.
[0013]
In the present invention, when at least a chip dividing trench is selected as a trench to be formed by dry etching, (1) the dry etching can be divided for each semiconductor chip by penetrating the wafer with the chip dividing trench. Alternatively, (2) the dry etching can be completed when the formation of the chip dividing trenches has a predetermined thickness up to the back surface of the wafer.
In the case of the above (1), the chip dividing step can be performed simultaneously with the dry etching. On the other hand, in the case of the above (2), after the dry etching, the wafer can be divided for each semiconductor chip along the chip dividing trench when necessary.
In the case of forming the wiring connection trench at the same time in the cases (1) and (2), it is preferable that the wiring connection trench is dry-etched so as to penetrate the wafer. In other words, in (1), the process ends when both the wiring connection trench and the chip division trench have penetrated the wafer, and in (2), the wiring connection trench has penetrated the wafer, and the chip division trench has the back surface of the wafer. Set the ratio of the width of each resist opening to form the trench for chip division, the trench for wiring connection, etc., the various setting conditions of dry etching, etc. to the optimum values so that the process ends when the predetermined thickness is left. It is desirable to do.
[0014]
In the present invention, examples of the dry etching include plasma etching, vapor phase etching, reactive ion etching, sputter etching, ion beam etching, and the like, and are not particularly limited. Preferred dry etching is selected depending on conditions such as the processing accuracy of the trench. For example, in a silicon wafer, dry etching using SF ₆ , CF ₄ , C ₂ F ₆ , C ₃ F ₈ , Cl _2, or the like as an etching gas as an F-based gas or a CL-based gas can be employed.
[0015]
In the present invention, in the case of the above (2), it is preferable to perform the following (1), (2), (3), (4), and (5).
(1) It is preferable that the width of the wiring connection trench is set wider than the width of the chip division trench. In other words, in dry etching, there is a problem that ions applied to silicon processing cannot enter the narrow gap of the resist opening (microloading effect). At the time when the connection trench 7 is penetrated by the microloading effect, the division is performed. If the trench 6 is also penetrated, the strength of the entire wafer is significantly reduced, and handling is hindered. Therefore, specifically, the width of the resist opening for forming the wiring connection trench is set to be wider than the width of the resist opening for forming the chip dividing trench, so that the connection trench 7 is penetrated. At this point, the dividing trench 6 can be prevented from penetrating, whereby the strength of the entire wafer can be maintained to some extent and the handling can be prevented.
[0016]
(2) The substrate cross-sectional area of the center line of the chip dividing trench after the etching is completed is set to be sufficiently larger than the substrate cross-sectional area of the center line of the connection trench. In this way, the connection trenches can be reliably and easily split along the chip splitting trenches without splitting, thereby preventing defective splitting.
[0017]
(3) The wiring connection trench is preferably formed substantially line-symmetrically with the chip division trench interposed therebetween. Here, the wiring connection trench and / or the chip division trench are formed in a groove shape extending on substantially the same straight line, and the bottomed cylindrical hole is formed on the substantially same straight line in a perforated shape. The above-mentioned “substantially line symmetric” includes the case where the wiring connection trenches and / or the chip division trenches have the bottomed cylindrical holes arranged in a perforation as a line. The case is also included.
When the wiring connection trench is not formed substantially line-symmetrically with the chip dividing trench interposed therebetween, at the time of chip division, a force may be applied to the connection trench closer to the chip dividing trench to cause a crack. Therefore, by adopting a substantially line-symmetrical arrangement, it is possible to concentrate the force on the chip dividing trench and prevent the division failure. In addition, as the trench for chip division, a plurality of bottomed cylindrical holes may be arranged in parallel in a perforated shape in addition to a general straight (linear) groove. The shape of the bottomed cylindrical hole may be circular, triangular, square, etc., and in the case of a shape having corners such as triangle, square, etc., by arranging the respective corners of the plurality of holes on the same straight line. It is easy to concentrate the forces at the time of division on the same straight line.
[0018]
{Circle around (4)} The chip dividing trenches are preferably arranged on substantially the same straight line and patterned from the end face to the end face of the wafer. By doing so, when chip division is performed from the state of the wafer, the entire surface from the end face to the end face can be easily divided, and the efficiency of chip division can be increased.
[0019]
{Circle around (5)} The chip dividing trench is preferably formed along a direction in which the cleavage of the wafer is easy. For example, in the case of a silicon wafer, since the easy cleavage direction is the [100] direction of the crystal plane orientation, the chip dividing trench is formed along the [100] direction, and a plurality of chip dividing trenches are formed in the [100] direction. It is preferable to arrange in parallel to the direction. In this way, the wafer can be easily divided into chips by preventing division failure.
[0020]
In the present invention, it is preferable to wet-etch the back surface of each semiconductor chip after the dry etching of (1), or it is preferable to wet-etch the back surface of the wafer after the dry etching of (2). By this wet etching, a crystal defect layer generated on the back surface of the wafer at the time of dry etching can be removed, and the bending strength at the time of mounting can be secured. In this wet etching, for example, in the case of a silicon wafer, a mixed solution of hydrofluoric acid and nitric acid can be suitably used.
[0021]
According to another aspect, the present invention can provide a semiconductor device manufactured by a method for manufacturing a semiconductor device and suitable for high-density and high-performance semiconductor chip mounting.
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0022]
[Embodiment 1]
FIG. 1 is a process explanatory view illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention, and FIG. 2 is a plan view of FIG.
[0023]
When manufacturing the semiconductor device of the present invention, as shown in FIG. 1 (a), transistors by known semiconductor half-step process thickness T ₁ is the chip corresponding region of the silicon wafer 1 of the surface of 625 .mu.m, a diode circuit or the like The formed active region 2 and the Al pad 3 as an electrode are formed. Then, as shown in FIG. 1B, a 1 μm-thick passivation film 4 is formed in a region other than the Al pad 3 by a known technique.
[0024]
Next, as shown in FIG. 1 (b), the surface of the Al pad 3 and the passivation film 4, by a known photolithography technique, the thickness T ₂ to form a resist film 5 of 25 [mu] m, tip splitting trench The resist openings 5a and 5b are opened at positions where the wiring connection trenches are to be formed. At this time, the resist opening portion 5a, in a lattice pattern between the chips corresponding region, and the opening width W ₁ is formed as a 5 [mu] m. The resist opening portion 5b is formed in plural at predetermined intervals along the outer periphery of the chip corresponding region, the shape is circular, the opening width (diameter) W ₂ is 10 [mu] m.
[0025]
Next, as shown in FIG. 1C, the front and back surfaces of the wafer 1 are simultaneously etched using a known silicon dry etching technique. The gas pressure is 0.001 to 1 Torr, and the gas type is SF ₆ , CF ₄ , C ₂ F ₆ , C ₃ F ₈ , O ₂ , and Cl ₂ . In the silicon dry etching, the reactive ions 8 form a chip dividing trench 6 and a wiring connecting trench 7 on the front surface of the wafer 1, and at the same time, etch the entire back surface.
[0026]
With the progress of the dry etching, as shown in FIGS. 1C and 1D, the chip dividing trench 6 penetrates and is divided into individual semiconductor chips 9, and the wiring connecting trench 7 penetrates. the thickness _{T 3} is dry etching completed upon reaching a 120 [mu] m.
[0027]
Next, as shown in FIG. 1E, the resist film 5 is peeled off using ashing of a known technique, and a crystal defect layer on the back surface of the chip 9 generated by dry etching is removed by wet etching. For this wet etching, a mixed solution of hydrofluoric acid and nitric acid is used.
[0028]
Through the above steps, an individual semiconductor chip 9 having a plurality of wiring connection trenches 7 having a width (diameter) W _{2 of} 10 μm and a thickness T ₃ reduced to 120 μm is formed.
[0029]
[Embodiment 2]
FIG. 3 is a view for explaining a method of manufacturing a semiconductor device according to the second embodiment of the present invention, and is a plan view showing a main part of a wafer surface at the end of dry etching, and FIG. FIG. 5 is a view for explaining the shape, dimensions and arrangement of each trench formed at the end of dry etching. FIG. 5 is a view for explaining the definition of the aspect ratio. FIG. 6 is an example of the aspect ratio dependence of the silicon dry etching rate. FIG. 7 is a graph showing an example of the etching time dependency of the etching amount when the front and back surfaces of the wafer are simultaneously dry-etched. 3 to 5, the same components as those in the first embodiment are denoted by the same reference numerals.
[0030]
In manufacturing the semiconductor device according to the second embodiment, a circular resist opening 15b is formed at a position where a wiring connection trench 17 is to be formed in a resist pattern formation process prior to dry etching. A plurality of circular resist openings 15a are perforated at positions where the holes 16 are to be formed. In this case, the plurality of resist openings 15b are arranged line-symmetrically with respect to the plurality of resist openings 15a arranged substantially in the same line.
[0031]
In the dry etching, the front surface and the back surface of the wafer 1 are simultaneously etched. However, as shown in FIG. 4A, the wiring connection trench 17 penetrates the wafer 1 and the chip dividing trench 16 ends when leaving a predetermined thickness T ₄ to the back surface. In this case, the gas pressure and gas type of the dry etching can be the same as those in the first embodiment. Thereafter, the resist film 15 is removed by conventionally known ashing, and the wafer 1 is divided into each chip unit by a conventionally known method (for example, a force is applied from the end face of the wafer along the chip dividing trench).
[0032]
By the way, as shown in FIGS. 5 and 6, the aspect ratio generally increases as dry etching proceeds, and as the aspect ratio increases, the dry etching rate decreases. This is because a problem (microloading effect) occurs that ions applied to silicon processing cannot enter the narrow gap of the resist opening. That is, as the trench is formed deeper, the etching efficiency decreases. Therefore, before the chip dividing trench penetrates the wafer, the resist opening for forming the wiring connecting trench is smaller than the width of the resist opening at the chip dividing trench forming position so that the wiring connecting trench can penetrate the wafer. It must be somewhat larger than the width of the part.
[0033]
Therefore, in the second embodiment, and the width W ₃ of the resist opening portion 15a of the chip division trench forming position on 5 [mu] m, 50 [mu] m width W ₄ of the resist opening portion 15b of the wiring connecting the trench forming position than this by setting larger the wiring connection trench 17 penetrates the wafer 1, so that it reaches at that time to a position where the chip dividing trench 16 leaves a predetermined thickness T ₄ to the back surface of the wafer 1 (FIG. 4).
[0034]
FIG. 7 is a graph showing the etching time dependency of the etching amount when the front and back surfaces of the wafer are simultaneously dry-etched in the second embodiment. As shown in FIG. 7, in dry etching according to the second embodiment, since the entire back surface of the wafer is etched, the etching rate is constant. When the wiring connection trench 17 has penetrated to the back surface, the etching is completed. The thickness of the silicon wafer before dry etching is 625 μm. After completion of the dry etching, the thickness _{T 5} is 300μm of the wafer 1 obtained by removing the resist film 15 by ashing, the width _{W 3} of the chip dividing trench 16 is 10 [mu] m, the depth _{D 1} of the dividing trench 16 is 185μm , the width _{W 4} of the interconnection trenches 7 is 50 [mu] m (see FIG. 4).
[0035]
As a first condition of the wafer 1 thus obtained, as shown in FIG. 4B, the relationship between the width L _st of the chip dividing trench 16 and the width L _ct of the connection trench 17 is as described above. To
L _st <L _ct
It is necessary to be. This is because the division trench 16 is not penetrated when the connection trench 17 is penetrated by the microloading effect. This is because if the chip dividing trench 16 completely penetrates, the strength of the entire wafer 1 is significantly reduced, which hinders handling. In the second embodiment,
L _ct = 50 [μm]
L _st = 10 [μm]
And
As a second condition, the substrate cross-sectional area of the center line P ₁ of the chip dividing trench 16 after etching is complete, there must be enough larger than the substrate cross-sectional area of the center line P ₂ of the connection trench 17. That is,
_{m (L st × T 4 +} S st × T 5) << n (S ct × T 5)
L _st : width T ₄ of the dividing trench 16: residual film at the bottom of the dividing trench S _st : interval of the dividing trench T ₅ : remaining thickness of the wafer S _ct : interval of the connecting trench In this case, each of m and n is one side of one chip. The number of division trenches per connection and the number of connection trenches. This is because the connection trench 17 must be split along the chip splitting trench 16 without splitting. In the case of Embodiment 2,
L _st = 10 [μm]
T ₄ = 115 [μm]
S _st = 5 [μm]
T ₅ = 300 [μm]
S _ct = 250 [μm]
m = 1000, n = 50 (chip 10 mm on one side)
m (L _st × T ₄ + S _st × T ₅ ) = 2650000
_{n (S ct × T 5)} = 3750000
It becomes.
As a third condition, the connection trench 17 (center line P ₂ ) needs to be arranged symmetrically with respect to the center line P ₁ of the chip division trench 16. This is to prevent a force from being applied to the connection trench 17 when the chip is divided unless the line is symmetric.
As a fourth condition, it is necessary that the plurality of chip dividing trenches 16 aligned on the same straight line (center line P ₁ ) be patterned from the end face to the end face of the wafer 1. This is because, in order to divide the chips from the state of the wafer, it is necessary to easily divide the entire surface from the end face to the end face.
As a fifth condition, the chip dividing trench 16 needs to be formed along a direction in which the cleavage of the wafer 1 is easy. For example, in the case of a silicon wafer, since the easy cleavage direction is the [100] direction of the crystal plane orientation, the chip dividing trench is formed along the [100] direction, and a plurality of chip dividing trenches are formed in the [100] direction. It is necessary to arrange in parallel to the direction.
[0036]
[Embodiment 3]
FIG. 8 shows an example in which the method of the present invention is applied. In this case, the semiconductor chip 29 is connected via the bumps 20 on the silicon wafer 1 in the state of FIG. Next, as in the first and second embodiments, a resist film 25 is formed by photolithography, and resist openings 25a and 25b are opened at positions where a chip dividing trench and a wiring connecting trench are to be formed. . Thereafter, dry etching is simultaneously performed on the front and back surfaces of the wafer 1 to form chip dividing trenches 26 and wiring connection trenches 27 on the front surface of the wafer 1 by reactive ions 28, and at the same time, the entire back surface is thinned. . This makes it possible to efficiently manufacture individualized, thinned, and stacked semiconductor chips from a wafer in which the semiconductor chips 29 are collectively connected at the wafer level.
[0037]
[Embodiment 4]
FIG. 9 shows another example to which the method of the present invention is applied. In this case, resist opening portions 35a and 35b are formed at positions where the chip dividing trench 36 and the connecting trench 37 are formed in the resist film 35, and a resist opening 35c is provided at a position where the capacitor forming trench 31 is formed. Thereafter, as in the first and second embodiments, the front surface and the back surface of the wafer 1 are simultaneously dry-etched, and the chip dividing trench 26, the wiring connection trench 27, and the capacitor are formed on the surface of the wafer 1 by reactive ions 38. A forming trench 31 is formed, and at the same time, the entire back surface is thinned. Thus, a deep trench used for forming a capacitor can be formed at the same time when the wafer is singulated and thinned.
[0038]
[Other embodiments]
In the second embodiment, the case where the plurality of chip dividing trenches are formed as a plurality of bottomed cylindrical holes on the same straight line is exemplified, but the chip dividing trench is formed in one groove shape. May be formed. Also in this case, it is preferable that the first to fifth conditions described above be satisfied in order to accurately and easily perform chip division without causing chip division failure.
[0039]
【The invention's effect】
According to the present invention, the number of semiconductor chips per wafer can be improved by reducing the interval (scribe line width) between regions corresponding to a plurality of chips before division on the wafer surface, and chipping by mechanical polishing or dicing can be prevented. And yield can be improved. Further, it is possible to simultaneously form a wiring connection trench and a capacitor formation trench at the same time as the individualization and thinning of the semiconductor chip, thereby improving the production efficiency of the semiconductor device. That is, high-density and high-performance semiconductor chip mounting by thinning and laminating semiconductor chips can be realized with high productivity.
[Brief description of the drawings]
FIG. 1 is a process explanatory view illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a plan view of FIG. 1 (c).
FIG. 3 is a diagram illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention, and is a plan view illustrating a main part of a wafer surface at the end of dry etching.
FIG. 4 is a diagram illustrating the shape, dimensions, and arrangement of each trench formed at the end of dry etching according to the second embodiment.
FIG. 5 is a diagram illustrating the definition of an aspect ratio.
FIG. 6 is a graph showing an example of an aspect ratio dependency of a silicon dry etching rate.
FIG. 7 is a graph showing an example of the etching time dependency of the etching amount when the front and back surfaces of a wafer are dry-etched simultaneously.
8 is a cross-sectional view showing an example to which the method of the present invention is applied. FIG. 9 is a cross-sectional view showing another example to which the method of the present invention is applied.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Wafer 2 Active area 3 Al pad 4 Passivation film 5, 15, 25, 35 Resist film 5a, 15a, 25a, 35a Resist opening (position for forming chip dividing trench)
5b, 15b, 25b, 35b Resist opening (formation position of wiring connection trench)
35c resist opening (formation position of trench for forming capacitor)
6, 16, 26, 36 Chip utilization trenches 7, 17, 27, 37 Wiring connection trench 31 Capacitor formation trench

Claims (13)

A method of manufacturing a semiconductor device, wherein dry etching for forming a trench on a surface of a wafer on a side where a semiconductor element is formed and dry etching for thinning the entire back surface of the wafer are simultaneously performed in the same atmosphere. 2. The method according to claim 1, wherein the trench is at least one of a chip dividing trench, a wiring connecting trench, and a capacitor forming trench. 3. The method according to claim 2, wherein the wiring connection trench penetrates the wafer by dry etching. 4. The method of manufacturing a semiconductor device according to claim 2, wherein the dry etching divides the semiconductor chip into individual semiconductor chips by penetrating the wafer with the chip dividing trench. Dry etching is completed when the formation of the trench for chip division leaves a predetermined thickness up to the back surface of the wafer,
4. The method of manufacturing a semiconductor device according to claim 2, wherein after the dry etching, the wafer is divided into semiconductor chips along the chip dividing trench. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the width of the wiring connection trench is set wider than the width of the chip division trench. 7. The method of manufacturing a semiconductor device according to claim 5, wherein the wiring connection trench is formed symmetrically with respect to the chip dividing trench. The method of manufacturing a semiconductor device according to claim 5, wherein the chip dividing trenches are arranged on substantially the same straight line and are patterned from an end face to an end face of the wafer. The method of manufacturing a semiconductor device according to claim 5, wherein the chip dividing trench is formed along a direction in which cleavage of the wafer is easy. The method for manufacturing a semiconductor device according to claim 2, wherein after the dry etching, the back surface of each semiconductor chip or the back surface of the wafer is wet-etched. The method for manufacturing a semiconductor device according to claim 10, wherein the wet etching uses a mixed solution of hydrofluoric acid and nitric acid. Prior to dry etching, a resist film is formed on the surface of the wafer by photolithography, and a position for forming a chip dividing trench, a position for forming a wiring connection trench, and a capacitor forming trench on the surface of the resist film. The method of manufacturing a semiconductor device according to claim 1, wherein a resist opening is formed in at least one of positions where the resist opening is formed. A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 3.

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