CN112530813A - Temporary bonding method - Google Patents
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- CN112530813A CN112530813A CN202011383320.1A CN202011383320A CN112530813A CN 112530813 A CN112530813 A CN 112530813A CN 202011383320 A CN202011383320 A CN 202011383320A CN 112530813 A CN112530813 A CN 112530813A
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- 238000000034 method Methods 0.000 title claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 239000011241 protective layer Substances 0.000 claims abstract description 13
- 238000001179 sorption measurement Methods 0.000 claims description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 238000001039 wet etching Methods 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 239000004642 Polyimide Substances 0.000 claims description 3
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 claims description 3
- 229920001721 polyimide Polymers 0.000 claims description 3
- 239000000463 material Substances 0.000 abstract description 25
- 230000008646 thermal stress Effects 0.000 abstract description 5
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 230000010354 integration Effects 0.000 description 9
- 239000003292 glue Substances 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Micromachines (AREA)
Abstract
The disclosure relates to a temporary bonding method, which belongs to the technical field of semiconductors, and can save material cost, reduce bonding time and avoid thermal stress. A temporary bonding method comprising: forming a first type of sub-nested structure of a nested structure on a substrate, wherein the nested structure comprises the first type of sub-nested structure and a second type of sub-nested structure that are capable of nesting with each other; preparing various patterns and devices in the area of the substrate where the first type sub-nested structure is not formed; forming a protective layer on the first type sub-nested structure and the patterns and devices; forming the second type sub-nesting structure on a carrier plate for temporary bonding; and nesting and interlocking the first type sub-nested structure with the second type sub-nested structure.
Description
Technical Field
The present disclosure relates to the field of semiconductor technology, and in particular, to a temporary bonding method.
Background
To improve the performance and integration of integrated circuits, the integration of chips in three dimensions has been started. At present, polymer materials such as temporary bonding glue and the like are mostly adopted for temporary bonding, and the methods are mostly heating, laser, chemical reaction and the like. The temporary bonding method has the disadvantages of high material cost, high stress, long bonding time and the like.
Disclosure of Invention
The purpose of the disclosure is to provide a temporary bonding method, which can save material cost, reduce bonding time and has no thermal stress.
According to a first embodiment of the present disclosure, there is provided a temporary bonding method including: forming a first type of sub-nested structure of a nested structure on a substrate, wherein the nested structure comprises the first type of sub-nested structure and a second type of sub-nested structure that are capable of nesting with each other; preparing various patterns and devices in the area of the substrate where the first type sub-nested structure is not formed; forming a protective layer on the first type sub-nested structure and the patterns and devices; forming the second type sub-nesting structure on a carrier plate for temporary bonding; and nesting and interlocking the first type sub-nested structure with the second type sub-nested structure.
Optionally, the first type of sub-nested structure that forms a nested structure on a substrate includes: forming a hard mask on the substrate; and carrying out photoetching and wet etching on the substrate on which the hard mask is formed to obtain the first type sub-nested structure.
Optionally, in a case that the first type sub-nesting structure or the second type sub-nesting structure is a groove structure, the cross section of the groove structure is an inverted trapezoid, a triangle or a right-angle, and the opening of the groove structure is a hexagon, a pentagon, a square, a triangle or a circle.
Optionally, in a case that the first type sub-nesting structure or the second type sub-nesting structure is a groove structure, a depth of the groove structure is greater than 20 micrometers.
Optionally, the material of the protective layer is silicon dioxide, silicon nitride, polyimide or benzocyclobutene.
Optionally, the protective layer has a thickness greater than 100 nanometers.
Optionally, the forming the second type sub-nesting structure on the carrier plate for temporary bonding includes: forming a hard mask on the carrier plate; and photoetching and wet etching are carried out on the carrier plate with the hard mask formed, so as to obtain the second type sub-nested structure.
Optionally, the method further comprises: debonding the substrate from the carrier after fabricating a finished backside structure or backside device on the backside of the substrate after the nested interlocking.
Optionally, the debonding the substrate from the carrier includes: and respectively adsorbing the substrate and the carrier plate by utilizing an adsorption mode, and bonding the substrate and the carrier plate under the action of an adsorption external force.
Optionally, the adsorption manner is at least one of vacuum adsorption, magnetic adsorption and capillary force adsorption.
The technical scheme of the disclosure has the following advantages: (1) the temporary bonding of the substrate and the carrier plate is realized by forming structures capable of being nested with each other on the substrate and the carrier plate, so that a polymer or a metal does not need to be additionally used as a temporary bonding glue material, and the material cost is saved; (2) because the materials of the mutually nested structures (namely the materials of the substrate and the carrier plate) are the same, the problem of thermal stress caused by mismatching of the thermal expansion coefficients of the materials does not exist, and the integration reliability is improved; (3) because the temporary bonding glue material is not used during temporary bonding, heating, exposure, chemical reaction and other operations are not needed during bonding removal, and the bonding removal time is greatly reduced. In general, the temporary bonding method according to the embodiments of the present disclosure is suitable for wafer level/chip-to-wafer/chip-to-chip temporary bonding, and the types of bonded chips are not limited, and in addition, the development of three-dimensional integration, especially heterogeneous integration where there are multiple materials and interfaces, can be greatly facilitated.
Additional features and advantages of the disclosure will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure without limiting the disclosure. In the drawings:
fig. 1 is a flow chart of a temporary bonding method according to one embodiment of the present disclosure.
Fig. 2a-2i show schematic cross-sectional views of a temporary bonding method according to an embodiment of the disclosure.
Detailed Description
The following detailed description of specific embodiments of the present disclosure is provided in connection with the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present disclosure, are given by way of illustration and explanation only, not limitation.
Fig. 1 is a flow chart of a temporary bonding method according to one embodiment of the present disclosure. As shown in fig. 1, the method includes the following steps S11 to S15.
In step S11, a first-type sub-nested structure of the nested structure is formed on the substrate, wherein the nested structure includes a first-type sub-nested structure and a second-type sub-nested structure that are capable of being nested with each other.
By nested structure is meant that one of the two parts making up the nested structure is a grooved structure and the other part is a raised structure, so that the two can nest and interlock with each other when the raised structure is embedded in the grooved structure.
In the present disclosure, when the first type sub-nesting structure is a groove structure, the second type sub-nesting structure is a protrusion structure, and when the first type sub-nesting structure is a protrusion structure, the second type sub-nesting structure is a groove structure.
Under the condition that the first type of sub-nested structure or the second type of sub-nested structure is a groove structure, the section of the groove structure is in an inverted trapezoid shape, a triangular shape or a right-angle shape, and the opening of the groove structure is in a hexagonal shape, a pentagonal shape, a square shape, a triangular shape or a circular shape. It will be appreciated by those skilled in the art that the cross-sectional shape and the shape of the opening of the groove structure may be virtually any shape, provided that nesting is achieved. In addition, the depth of the groove structures is greater than 20 microns, and may be, for example, 30 microns, to enable a secure nested interlock.
In step S12, various patterns and devices are prepared in regions of the substrate where the first-type sub-nested structure is not formed.
The present disclosure is not limited to the methods of fabricating the various patterns and devices.
Typically, the first type of sub-nesting structure is located around the substrate and is of a relatively large size to facilitate the use of an aligned manner of nesting and interlocking.
In step S13, a protective layer is formed on the first type sub-nested structure and the pattern and the device.
The protective layer is formed to protect various patterns and devices formed in step S12 from damage during subsequent temporary bonding.
The material of the protective layer may be silicon dioxide, silicon nitride, polyimide, benzocyclobutene, or the like. The thickness of the protective layer is greater than 100 nm, for example 200 nm, so as to better protect the protective layer.
In step S14, a second-type sub-nest structure is formed on the carrier board for temporary bonding.
In step S15, the first-type sub-nested structure is nested and interlocked with the second-type sub-nested structure.
It will be understood by those skilled in the art that step S14 may be performed before step S11, or before S12, or before S13. That is, it is sufficient if the second-type sub-nesting structure can be formed before step S15.
The technical scheme of the disclosure has the following advantages: (1) the temporary bonding of the substrate and the carrier plate is realized by forming structures capable of being nested with each other on the substrate and the carrier plate, so that a polymer or a metal does not need to be additionally used as a temporary bonding glue material, and the material cost is saved; (2) because the materials of the mutually nested structures (namely the materials of the substrate and the carrier plate) are the same, the problem of thermal stress caused by mismatching of the thermal expansion coefficients of the materials does not exist, and the integration reliability is improved; (3) because the temporary bonding glue material is not used during temporary bonding, heating, exposure, chemical reaction and other operations are not needed during bonding removal, and the bonding removal time is greatly reduced. In general, the temporary bonding method according to the embodiments of the present disclosure is suitable for wafer level/chip-to-wafer/chip-to-chip temporary bonding, and the types of bonded chips are not limited, and in addition, the development of three-dimensional integration, especially heterogeneous integration where there are multiple materials and interfaces, can be greatly facilitated.
Fig. 2a-2i show schematic cross-sectional views of a temporary bonding method according to an embodiment of the disclosure. The cross-sectional diagram is described by taking the first type of sub-nesting structure as a groove structure and the second type of sub-nesting structure as a protrusion structure as an example.
First, in fig. 2a, a hard mask 2 is formed on a substrate 1, and for example, the hard mask 2 may be formed using a deposition (e.g., chemical vapor deposition, physical vapor deposition, etc.). The material of the substrate 1 may be silicon, glass, or the like. The material of the hard mask 2 may be an insulating material such as silicon dioxide, silicon nitride, or the like, or may be a metal material such as Al or the like. And then carrying out photoetching and wet etching on the substrate 1 with the hard mask 2 formed thereon to obtain the first type sub-nested structure 3.
Then, as shown in fig. 2b, the remaining hard mask 2 on the substrate 1 is etched away.
Then, as shown in fig. 2c, various patterns and devices 4 are prepared in the area of the substrate 1 where the first-type sub-nested structure 3 is not formed, so as to realize the preparation of the front patterns and devices of the substrate 1. Then, a protective layer 5 is formed on the first-type sub-nested structure 3 and the patterns and devices 4.
Then, as shown in fig. 2d, a hard mask 7 is formed on the carrier plate 6 for temporary bonding, for example, the hard mask 7 may be formed by a deposition (e.g., chemical vapor deposition, physical vapor deposition, etc.). The material of the carrier plate 6 may be silicon, glass, etc. The material of the hard mask 7 may be an insulating material such as silicon dioxide, silicon nitride, or the like, or may be a metal material such as Al or the like. Then, the hard mask 7 is patterned by photolithography.
Then, as shown in fig. 2e, the second-type sub-nested structure 8 is formed by wet etching.
The remaining hard mask 7 on the carrier plate 6 is then removed as shown in fig. 2 f.
Then, as shown in fig. 2g, the first-type sub-nesting structure 3 is nested and interlocked with the second-type sub-nesting structure 8.
In the process of performing nesting and interlocking, the first type sub-nesting structure 3 and the second type sub-nesting structure 8 can be aligned on a bonding machine, and then a small force is applied to enable the first type sub-nesting structure 3 of the groove structure and the second type sub-nesting structure 8 of the protrusion structure to be matched and nested, so that a mechanical interlocking structure is formed, and therefore the temporary bonding is completed.
The reason why alignment can be performed on the bonder according to the pattern of the nested structure is that the temporarily bonded pattern is larger in size around the wafer and can be used as an alignment pattern.
Then, as shown in fig. 2h, a back structure or back device 9 is prepared on the back side of the substrate 1 after the nested interlocking.
Then, as shown in fig. 2i, after the completed back structure or back device 9 is prepared on the back side of the substrate 1 after the nested interlocking, the substrate 1 is debonded from the carrier plate 6.
The substrate 1 and the carrier 6 can be respectively adsorbed by utilizing an adsorption mode, and the substrate 1 and the carrier 6 are debonded under the action of an adsorption external force. The adsorption method may be at least one of vacuum adsorption, magnetic adsorption, and capillary adsorption. In an embodiment, the substrate 1 and the carrier plate 6 may be adsorbed by vacuum adsorption, magnetic adsorption, capillary adsorption, or other adsorption methods, and then the substrate 1 and the carrier plate 6 are slowly separated upward and downward to achieve debonding between the two. Moreover, during the bonding process, the positions of the substrate 1 and the carrier plate 6 are ensured not to move left and right.
By adopting the technical scheme, the temporary bonding of the wafer and the carrier plate can be realized by utilizing the mechanical nested structure, the de-bonding of the wafer and the carrier plate is realized by utilizing the mechanical demoulding, the material cost is saved, the problem of thermal stress caused by the mismatching of the thermal expansion coefficients of the materials does not exist, the integration reliability is improved, in addition, the operations of heating, exposure, chemical reaction and the like are not needed when the de-bonding is carried out, and the de-bonding time is greatly reduced.
The preferred embodiments of the present disclosure are described in detail with reference to the accompanying drawings, however, the present disclosure is not limited to the specific details of the above embodiments, and various simple modifications may be made to the technical solution of the present disclosure within the technical idea of the present disclosure, and these simple modifications all belong to the protection scope of the present disclosure.
It should be noted that the various features described in the above embodiments may be combined in any suitable manner without departing from the scope of the invention. In order to avoid unnecessary repetition, various possible combinations will not be separately described in this disclosure.
In addition, any combination of various embodiments of the present disclosure may be made, and the same should be considered as the disclosure of the present disclosure, as long as it does not depart from the spirit of the present disclosure.
Claims (10)
1. A temporary bonding method, comprising:
forming a first type of sub-nested structure of a nested structure on a substrate, wherein the nested structure comprises the first type of sub-nested structure and a second type of sub-nested structure that are capable of nesting with each other;
preparing various patterns and devices in the area of the substrate where the first type sub-nested structure is not formed;
forming a protective layer on the first type sub-nested structure and the patterns and devices;
forming the second type sub-nesting structure on a carrier plate for temporary bonding; and
nesting and interlocking the first type sub-nesting structure and the second type sub-nesting structure.
2. The method of claim 1, wherein forming the first type of sub-nested structure of nested structures on the substrate comprises:
forming a hard mask on the substrate;
and carrying out photoetching and wet etching on the substrate on which the hard mask is formed to obtain the first type sub-nested structure.
3. The method according to claim 1, wherein in the case where the first type of sub-nesting structure or the second type of sub-nesting structure is a groove structure, the cross section of the groove structure is an inverted trapezoid, a triangle or a right-angle, and the opening shape of the groove structure is a hexagon, a pentagon, a square, a triangle or a circle.
4. The method of claim 1, wherein, in the case where the first type of sub-nesting structure or the second type of sub-nesting structure is a groove structure, the depth of the groove structure is greater than 20 microns.
5. The method of claim 1, wherein the protective layer is made of silicon dioxide, silicon nitride, polyimide, or benzocyclobutene.
6. The method of claim 1, wherein the protective layer has a thickness greater than 100 nanometers.
7. The method of claim 1, wherein said forming said second type of sub-nest structure on a carrier plate for temporary bonding comprises:
forming a hard mask on the carrier plate;
and photoetching and wet etching are carried out on the carrier plate with the hard mask formed, so as to obtain the second type sub-nested structure.
8. The method of claim 1, further comprising:
debonding the substrate from the carrier after fabricating a finished backside structure or backside device on the backside of the substrate after the nested interlocking.
9. The method of claim 8, wherein said debonding said substrate from said carrier plate comprises:
and respectively adsorbing the substrate and the carrier plate by utilizing an adsorption mode, and bonding the substrate and the carrier plate under the action of an adsorption external force.
10. The method of claim 9, wherein the adsorption means is at least one of vacuum adsorption, magnetic adsorption, and capillary adsorption.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011383320.1A CN112530813A (en) | 2020-11-30 | 2020-11-30 | Temporary bonding method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011383320.1A CN112530813A (en) | 2020-11-30 | 2020-11-30 | Temporary bonding method |
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| CN112530813A true CN112530813A (en) | 2021-03-19 |
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| CN202011383320.1A Pending CN112530813A (en) | 2020-11-30 | 2020-11-30 | Temporary bonding method |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107993937A (en) * | 2017-12-01 | 2018-05-04 | 华进半导体封装先导技术研发中心有限公司 | The supplementary structure and the wafer processing method using the structure of a kind of interim bonding technology |
| CN110379780A (en) * | 2019-07-31 | 2019-10-25 | 中国电子科技集团公司第五十八研究所 | A kind of silicon substrate fan-out-type wafer-level packaging method and structure |
| CN110896025A (en) * | 2019-10-28 | 2020-03-20 | 芯盟科技有限公司 | Wafer bonding method and bonded wafer |
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2020
- 2020-11-30 CN CN202011383320.1A patent/CN112530813A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107993937A (en) * | 2017-12-01 | 2018-05-04 | 华进半导体封装先导技术研发中心有限公司 | The supplementary structure and the wafer processing method using the structure of a kind of interim bonding technology |
| CN110379780A (en) * | 2019-07-31 | 2019-10-25 | 中国电子科技集团公司第五十八研究所 | A kind of silicon substrate fan-out-type wafer-level packaging method and structure |
| CN110896025A (en) * | 2019-10-28 | 2020-03-20 | 芯盟科技有限公司 | Wafer bonding method and bonded wafer |
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Application publication date: 20210319 |