JP2009289964A - Through wiring board, multilayer through wiring board, method of manufacturing through wiring board, and method of manufacturing multilayer through wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a through wiring board which has thin through wiring, a multilayer through wiring board, method of manufacturing the through wiring board, and method of manufacturing the multilayer through wiring board. <P>SOLUTION: The method of manufacturing the through wiring board includes a column formation body fabricating step of fabricating a column formation body having a flat plate portion made of silicon or metal and a plurality of column portions stood from one surface of the flat plate portion along the thickness of the flat plate portion, a filling step of filling gaps between the column portions of the column formation body with a resin or glass, a sealing body fabricating step of polishing both surfaces of the column formation body filled with the resin or the glass in the filling step along the thickness to fabricate the sealing body which has the column portions sealed with the resin or the glass and also has polished surfaces of the column portions exposed on both the surfaces, and an electrode forming step of forming an electrode over the polished surfaces of the column portions of the sealing body. The through wiring board is fabricated in this manufacturing method. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a through wiring board having a through wiring and a multilayer through wiring board in which the through wiring boards are stacked.

A manufacturing method of a through wiring substrate in which a through wiring is formed by filling a through hole provided in the substrate with metal by plating is known as a conventional technique (Patent Document 1).
WO2005 / 093827

  In the method of manufacturing a through wiring substrate described in Patent Document 1, if the through hole is thin, the through hole cannot be filled well with metal by plating, so that a thin through wiring may not be formed. In addition, a plating process is required, which is costly and time consuming. Furthermore, the yield was poor.

According to the first aspect of the present invention, a method of manufacturing a through wiring substrate includes a flat plate portion made of silicon, and a plurality of pillar portions made of silicon erected in the thickness direction of the flat plate portion from one surface of the flat plate portion. The column forming body manufacturing step for manufacturing the column forming body having a thickness of both sides of the column forming body filled with resin or glass by the filling step Polishing in the vertical direction, the sealing part manufacturing step for manufacturing the sealing body in which the column part is sealed with resin or glass and the polishing surface of the column part is exposed on both sides, and the polishing surface of the column part of the sealing body An electrode forming step of forming an electrode on the substrate.
According to the second aspect of the present invention, the method of manufacturing the through wiring board includes a flat plate portion made of metal, and a plurality of column portions made of metal erected in the thickness direction of the flat plate portion from one surface of the flat plate portion. The column forming body manufacturing step for manufacturing the column forming body having a thickness of both sides of the column forming body filled with resin or glass by the filling step Polishing in the vertical direction, the sealing part manufacturing step for manufacturing the sealing body in which the column part is sealed with resin or glass and the polishing surface of the column part is exposed on both sides, and the polishing surface of the column part of the sealing body An electrode forming step of forming an electrode on the substrate.

  According to the present invention, a through wiring substrate having a thin through wiring can be manufactured. In addition, the plating process is unnecessary, and it can be manufactured at a low cost, in a short time, and at a high yield.

-First embodiment-
The structure of the multilayer through wiring substrate 1 according to the first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a cross-sectional view of a multilayer through wiring substrate 1. The multilayer through wiring substrate 1 is produced by laminating two through wiring substrates 1A and 1B. The through wiring boards 1 </ b> A and 1 </ b> B have a through wiring 11, a resin portion 12, and electrodes 13 and 14. The through wiring 11 is made of silicon and is a wiring that electrically connects the electrode 13 formed on one surface of the through wiring substrates 1A and 1B and the electrode 14 formed on the other surface. By connecting the electrode 14 of the through wiring board 1A and the electrode 13 of the through wiring board 1B, the through wiring board 1A and the through wiring board 1B are electrically connected. The resin portion 12 is an insulating body in the mother phase of the through wiring boards 1A and 1B made of resin.

  Next, the manufacturing method of the multilayer penetration wiring board 1 of the 1st Embodiment of this invention is demonstrated with reference to FIGS. The manufacturing method of the multilayer penetration wiring board 1 of the 1st embodiment of the present invention has a pillar formation process, a resin filling process, a polishing process, an electrode formation process, a division process, and a lamination process.

(A) Column Forming Step The column forming step will be described with reference to FIGS.
The column forming process includes an alignment recess forming process, a primary crystal anisotropic etching process, and a secondary crystal anisotropic etching process. In the alignment recess forming step, a mark for determining the direction of the resist pattern formed on the surface of the silicon wafer in the primary crystal anisotropic etching step and the secondary crystal anisotropic etching step is formed on the surface. In the first crystal anisotropic etching step, a plurality of ridges along the resist pattern are formed on the surface of the silicon wafer. In the second crystal anisotropic etching step, pillars are formed by leaving only the portions where the resist pattern is formed on the surface of the silicon wafer.

(I) Alignment Concavity Formation Step As shown in FIG. 2A, a single crystal silicon wafer 2 cut out at the (110) plane is prepared. Next, a first protective film 21 made of Si ₃ N ₄ is formed on the surface of the silicon wafer 2 using known CVD or the like. A protective film made of SiO ₂ may be formed.

  As shown in FIG. 2B, an alignment opening 22 with a silicon surface exposed is formed in the protective film 21. For example, the alignment opening 22 is formed by performing RIE (Reactive Ion Etching) until the silicon surface is exposed.

  As shown in FIG. 2C, an alignment recess 23 is formed in the silicon surface of the alignment opening 22 by crystal anisotropic etching. Here, the crystal anisotropic etching is anisotropic etching utilizing the property that the etching rate varies depending on the crystal direction. Here, it is used that the etching rate of the (110) plane of silicon is considerably higher than the etching rate of the (111) plane. For example, crystal anisotropic etching is performed as follows. A TMAH (Tetramethyl Ammonium Hydroxide, (CH3) 4NOH) solution is heated to 60 to 80 ° C., and the silicon wafer 2 is immersed in the solution. As a result, as shown in FIG. 2C, an alignment recess 23 having a hexagonal shape when viewed from the surface direction is formed.

  The alignment recess 23 will be described in detail with reference to FIG. The crystal structure of the silicon wafer 2 has a (111) plane crystal plane perpendicular to the (110) plane. Of the six sides 23a to 23f of the alignment recess 23 shown in FIG. 3A, the side surface of the recess having two sides 23a and 23d is one (111) surface, and the side surface of the recess having two sides 23c and 23f is the other side. (111) plane. FIG. 3B is a DD cross-sectional view of FIG. 3A, and a V-shaped concave portion is formed on the silicon surface by the concave side surface 23ba having the side 23b and the concave side surface 23ea having the side 23e.

(Ii) Primary crystal anisotropic etching step A resist is applied to the entire surface of the silicon wafer 2 on which the protective film 21 has been formed, using a spin coater or a spray coater. Then, by exposure and development, as shown in FIG. 4A, a line pattern of the resist 24 parallel to the sides 23c and 23f of the alignment recess 23 is formed. Next, using RIE, as shown in FIG. 4B, the first protective film 21 not covered with the resist 24 is etched to expose the silicon surface. Then, the resist 24 is removed by washing with hot sulfuric acid / hydrogen peroxide. As a result, as shown in FIG. 4C, a line pattern of the first protective film 21 parallel to the sides 23c and 23f of the alignment recess 23 is formed on the surface of the silicon wafer 2.

  When the above-described crystal anisotropic etching is performed on the silicon wafer 2 shown in FIG. 4C, the portion where the silicon surface is exposed is etched, and a protrusion having the first protective film 21 as an upper surface is formed. Since the ridge is parallel to the sides 23 c and 23 f of the alignment recess 23, the side surface of the ridge is the (111) plane of the silicon wafer 2. Accordingly, the side surfaces of the ridges are perpendicular to the (110) plane of the silicon wafer 2.

(Iii) Secondary Crystal Anisotropic Etching Step By heating the silicon wafer 2 to about 1000 ° C. in an oxygen atmosphere, a second protection of SiO ₂ is formed on the entire surface of the silicon wafer 2 as shown in FIG. A film 25 is formed. Si ₃ N ₄ may be formed as the second protective film. Next, a resist is applied to the entire surface of the silicon wafer 2 using a spin coater or a spray coater. Since it is necessary to apply a resist also to the side surfaces of the ridges formed in the primary crystal anisotropic etching step, it is preferable to apply a thick film resist. Then, by exposure and development, a line pattern of the resist 24 parallel to the sides 23a and 23d of the alignment recess 23 is formed (see FIG. 5B).

  Next, the silicon wafer 2 is immersed in a hydrofluoric acid solution, and the second protective film 25 not covered with the resist 24 is etched to expose the silicon surface (see FIG. 5C). Then, the resist 24 is removed by washing with hot sulfuric acid / hydrogen peroxide. As a result, a line pattern of the second protective film 25 parallel to the sides 23a and 23d of the alignment recess 23 is formed on the surface of the silicon wafer 2 (see FIG. 6A).

  When the above-described crystal anisotropic etching is performed on the silicon wafer 2, the portion where the silicon surface of the protrusion is exposed is etched as shown in FIG. 6B, and the column portion having the second protective film 25 as the upper surface is etched. 26 is formed. Note that the newly formed side surface of the column portion 26 is parallel to the sides 23 a and 23 d of the alignment recess 23, and thus becomes the (111) surface of the silicon wafer 2. Therefore, the newly formed side surface of the pillar portion 26 is a vertical surface with respect to the (110) plane of the silicon wafer 2. Further, the side surface formed in the primary crystal anisotropic etching step of the column part 26 is not etched because it is protected by the second protective film 25.

  When the second protective film 25 is removed using a hydrofluoric acid solution or RIE, as shown in FIG. 6C, the flat plate portion 27 and the one surface of the flat plate portion 27 are erected in the thickness direction of the flat plate portion 27. Thus, the silicon wafer 2 composed of the plurality of pillar portions 26 made of silicon is produced. Hereinafter, this silicon wafer 2 is referred to as a columnar body 3.

(B) Resin Filling Step As shown in FIG. 7A, the epoxy resin 31 is discharged from the nozzle 7, and the epoxy resin 31 is poured between the column portions 26 of the column forming body 3. And as shown in FIG.7 (b), between the pillar parts 26 is filled with the epoxy resin 31, and the filled resin 31 is hardened. In FIG. 7B, the epoxy resin 31 is poured until the upper end of the column part 26 is covered with the epoxy resin 31, but the epoxy resin 31 is not covered with the epoxy resin 31. May be poured.

(C) Polishing Step As shown in FIG. 7 (c), one surface of the column forming body 3 filled with the epoxy resin 31 is polished in the thickness direction by the resin filling step, so that the flat plate portion 27 of the column forming body 3. Is removed, and one polished surface of the column portion 26 is exposed. Further, the other surface of the column forming body 3 is polished and flattened, and the other polished surface of the column portion 26 is exposed. The column forming body 3 in which the column portion 26 is sealed with the epoxy resin as described above and the polished surface of the column portion 26 is exposed on both surfaces is hereinafter referred to as a resin sealing body 4. The polishing method is not particularly limited as long as the flat plate portion 27 of the pillar forming body 3 can be deleted and the surface of the resin sealing body 4 can be planarized. For example, CMP (Chemical Mechanical Polishing) may be used.

(D) Electrode formation process As shown in FIG.7 (d), the electrodes 13 and 14 are formed in the surface of the resin sealing body 4 on the grinding | polishing surface of the column part 26 by well-known sputtering or etching. In addition, if it is a method which can form an electrode on the surface of the resin sealing body 4, it will not be limited to sputtering and etching, A vacuum evaporation etc. may be sufficient.

(E) Dividing Step The resin sealing body 4 on which the electrodes 13 and 14 are formed is divided along the two-dot chain line 32 shown in FIG. What divided | segmented the resin sealing body 4 as mentioned above becomes penetration wiring board 1A, 1B. Note that the method is not limited to the diamond blade dicing method as long as the resin sealing body 4 can be divided.

(F) Laminating Step A plurality of through wiring boards 1A and 1B are bonded together by thermocompression bonding in the same manner as the glass epoxy substrate to complete the multilayer through wiring board 1 shown in FIG. The method is not limited to thermocompression bonding as long as it is a method capable of laminating a plurality of through wiring substrate laminates 1A and 1B. Here, the column portion 26 becomes the through wiring 11, and the epoxy resin 31 becomes the resin portion 12.

The manufacturing method of the multilayer through-wiring board 1 according to the first embodiment has the following operational effects.
(1) A pillar forming body 3 having a flat plate portion 27 made of silicon and a plurality of pillar portions 26 made of silicon standing in the thickness direction of the flat plate portion 27 from one surface of the flat plate portion 27 was produced. Next, the space between the column portions 26 of the column forming body 3 is filled with the epoxy resin 31, and both sides of the column forming body 3 filled with the epoxy resin 31 are polished in the thickness direction. A sealed resin body 4 was produced which was sealed and the polished surface of the column portion 26 was exposed on both sides. Then, the through wiring boards 1A and 1B produced by forming the electrodes 13 and 14 on the polished surface of the column portion 26 of the resin sealing body 4 are produced, and the produced through wiring boards 1A and 1B are laminated. The multilayer through wiring substrate 1 was manufactured. Thereby, the multilayer penetration wiring board 1 which has a thin penetration wiring can be manufactured. Moreover, if it does not laminate | stack, the penetration wiring boards 1A and 1B which have a thin penetration wiring can be manufactured.

(2) Since the column portion 26 is formed by crystal anisotropic etching, the column portion 26 having a plane perpendicular to the surface of the silicon wafer 2 can be formed. Accordingly, since the column portion 26 having a high aspect ratio (the height of the column portion 26 divided by the length of the side of the upper surface of the column portion 26) can be formed, a thin and long through wiring can be formed. it can. As a result, high-density through wiring with a pitch can be formed.

(3) Using the silicon wafer 2 having the (110) plane, an alignment recess 23 having a surface along the (111) plane perpendicular to the (110) plane of the silicon wafer 2 is formed. A ridge having a side surface perpendicular to the (110) plane of the silicon wafer 2 is formed by alignment with one (111) plane of the two (111) planes. A column portion 26 having a side surface perpendicular to the (110) plane of the silicon wafer 2 is formed in alignment with the other (111) plane. Thereby, the column part 26 with a high aspect ratio can be formed, and a thin through wiring can be formed.

(4) Using the silicon wafer 2 having the (110) plane, an alignment recess 23 having a surface along the (111) plane perpendicular to the (110) plane of the silicon wafer 2 is formed. The resist patterning is formed, and crystal anisotropic etching is performed on the silicon wafer 2 to form a ridge having one (111) surface of the two (111) surfaces. The second protective film 25 is formed on the surface of the silicon wafer 2 including the resist patterning formed by the alignment recesses 23, and the silicon wafer 2 is subjected to crystal anisotropic etching to obtain two (111) The column part 26 having the side surface of the other (111) surface among the surfaces is formed. Thereby, the column part 26 with a high aspect ratio can be formed, and a thin through wiring can be formed.

-Second Embodiment-
A multilayer through wiring board according to a second embodiment of the present invention will be described. Also in the multilayer through wiring substrate of the second embodiment, the column portion 26 is formed by crystal anisotropic etching. Since the structure of the multilayer through wiring board in the second embodiment is not different from the structure of the multilayer through wiring board in the first embodiment (see FIG. 1), description of the structure of the multilayer through wiring board is omitted.

  Next, the manufacturing method of the multilayer penetration wiring board of the 2nd Embodiment of this invention is demonstrated with reference to FIGS. The manufacturing method of the multilayer penetration wiring board of a 2nd embodiment of the present invention has a pillar formation process, a resin filling process, a polishing process, an electrode formation process, a division process, and a lamination process. Among these, the resin filling process, the polishing process, the electrode forming process, the dividing process, and the laminating process are the same as those in the method for manufacturing the multilayer through-wiring board of the first embodiment, and thus description thereof is omitted.

(A) Column Forming Step The column forming step in the second embodiment is the same step up to the point where the resist 24 is peeled off in the primary crystal anisotropic etching step in the first embodiment (FIG. 4C). )reference). After removing the resist 24, the silicon wafer 2 is heated to about 1000 ° C. in an oxygen atmosphere without performing crystal anisotropic ion etching. As a result, as shown in FIG. 8A, the second protective film 25 is not formed on the formation portion of the first protective film 21, and the second protective film 25 is formed only on the silicon surface. At this time, unlike the first embodiment, the first protective film 21 remains. Then, as shown in FIG. 8B, a line pattern of the resist 24 parallel to the sides 23a and 23d of the alignment recess 23 is formed by exposure and development.

  As shown in FIG. 8C, the first protective film 21 and the second protective film 25 not covered with the resist 24 are etched by ion etching or the like to expose the silicon surface. Then, after removing the resist 24, crystal anisotropic etching is performed. As a result, as shown in FIG. 9A, a protrusion having the upper surface of the protective film surface in which the first protective film 21 and the second protective film 25 are alternately arranged is formed.

  The silicon wafer 2 is heated to about 1000 ° C. in an oxygen atmosphere, and as shown in FIG. 9B, a second protective film 25 is formed on the silicon surface. At this time, the second protective film is also formed on the side surface of the ridge. Next, RIE is performed to remove the first protective film 21 and expose the silicon surface as shown in FIG. 9C. Then, using a dicing saw or laser, as shown in FIG. 10A, the exposed portion of the silicon surface of the ridge is changed to the direction of the (111) plane (the direction parallel to the sides 23 c and 23 f of the alignment recess 23. ) To form a cut 28. By this cut 28, the etching is stopped at the (111) plane perpendicular to the (110) plane without being etched at another oblique (111) plane.

  As shown in FIG. 10B, crystal anisotropic etching is performed to etch the exposed silicon surface, thereby forming the column portion 26. Since the etch stop is performed on the (111) plane perpendicular to the (110) plane, the side surface of the newly formed column portion 26 is a plane perpendicular to the (110) plane of the silicon wafer 2. Then, when the second protective film 25 is removed, the silicon wafer 2 shown in FIG. 10C is obtained.

The manufacturing method of the multilayer penetration wiring board by the above 2nd embodiment has the following operation effects.
(1) As in the first embodiment, a multilayer through-wiring board having thin through-wiring can be manufactured. Moreover, if it does not laminate | stack, the penetration wiring board which has a thin penetration wiring can be manufactured.

(2) Using the silicon wafer 2 having the (110) plane, the alignment recess 23 having a surface along the (111) plane perpendicular to the (110) plane of the silicon wafer 2 is formed. The resist patterning is formed, and crystal anisotropic etching is performed on the silicon wafer 2 to form a ridge having one (111) surface of the two (111) surfaces. Are formed on the surface of the silicon wafer 2, and a part of the protective film on the upper surface of the ridge is removed, and the part from which the protective film is removed is cut in the direction of the (111) plane, Crystal anisotropic etching was performed on the silicon wafer 2 to form a column portion 26 having a side surface of the other (111) surface of the two (111) surfaces. Thereby, the column part 26 with a high aspect ratio can be formed, and a thin through wiring can be formed.

-Third embodiment-
A multilayer through wiring board according to a third embodiment of the present invention will be described. The multilayer through-wiring board according to the third embodiment forms pillars using a cutting machine such as a dicing machine. Since the structure of the multilayer through wiring board in the third embodiment is not different from the structure of the multilayer through wiring board in the first embodiment (see FIG. 1), description of the structure of the multilayer through wiring board is omitted.

  Next, the manufacturing method of the multilayer penetration wiring board of the 3rd embodiment of the present invention is explained with reference to FIG. The manufacturing method of the multilayer penetration wiring board of the 3rd embodiment of the present invention has a pillar formation process, a resin filling process, a polishing process, an electrode formation process, a division process, and a lamination process. Among these, the resin filling process, the polishing process, the electrode forming process, the dividing process, and the laminating process are the same as those in the method for manufacturing the multilayer through-wiring board of the first embodiment, and thus description thereof is omitted.

(A) Column forming step Using a cutting machine such as a dicing machine on the surface of the silicon wafer 2, a plurality of grooves are formed on the surface of the silicon wafer 2 along a predetermined direction as shown in FIG. To do. Next, as shown in FIG. 11B, a plurality of grooves are formed on the surface of the silicon wafer 2 along the other direction different from the predetermined direction. As a result, the column portion 26A is formed by two grooves in a predetermined direction and two grooves in the other direction. The silicon wafer 2 does not need to be a (110) plane silicon wafer.

The manufacturing method of the multilayer through-wiring board according to the third embodiment described above has the following operational effects.
(1) As in the first embodiment, a multilayer through-wiring board having thin through-wiring can be manufactured. Moreover, if it does not laminate | stack, the penetration wiring board which has a thin penetration wiring can be manufactured.

(2) The column portion 26A can be formed by a simple process of forming a plurality of grooves on the surface of the silicon wafer 2 with a cutting machine such as a dicing machine.

The multilayer through-wiring board of the above first to third embodiments can be modified as follows.
The column portion 26 may be formed by dry etching such as RIE. In this case, a protective film such as a photoresist film or an aluminum film is formed on the surface of the silicon wafer 2 where the column part 26 is to be formed, and RIE or ICP-RIE is performed. As a result, it is possible to form a thin and long column portion with almost no undercut, and thus a thin through wiring can be formed. The silicon wafer 2 does not need to be a (110) plane silicon wafer.

-Fourth Embodiment-
A multilayer through wiring board according to a fourth embodiment of the present invention will be described. In the multilayer through wiring substrate of the fourth embodiment, a metal such as Cu is used as the material of the through wiring 11. Further, the column portion is formed by an electric discharge machining method. Since the structure of the multilayer through wiring board in the fourth embodiment is not different from the structure of the multilayer through wiring board in the first embodiment (see FIG. 1), description of the structure of the multilayer through wiring board is omitted.

  Next, the manufacturing method of the multilayer penetration wiring board of the 4th embodiment of the present invention is explained with reference to FIG. The manufacturing method of the multilayer penetration wiring board of a 4th embodiment of the present invention has a pillar formation process, a resin filling process, a polishing process, an electrode formation process, a division process, and a lamination process. Among these, the resin filling process, the polishing process, the electrode forming process, the dividing process, and the laminating process are the same as those in the method for manufacturing the multilayer through-wiring board of the first embodiment, and thus description thereof is omitted.

(A) Column Forming Step As shown in FIG. 12, a column portion is formed from a metal flat plate 6 by an electric discharge machining method. As shown in FIG. 12A, a metal mask 5 having a large number of holes corresponding to pillars is used as a plate electrode. When electric discharge machining is performed on the metal flat plate 6 using the metal mask 5, the flat plate 6 remains as a pillar portion 26B only in the hole portion of the metal mask 5 as shown in FIG. 12B, and the other portions are removed. The

The manufacturing method of the multilayer penetration wiring board by the above 4th embodiment has the following operation effects.
(1) As in the first embodiment, a multilayer through-wiring board having thin through-wiring can be manufactured. Moreover, if it does not laminate | stack, the penetration wiring board which has a thin penetration wiring can be manufactured.

(2) The fine column portion 26B can be collectively formed by the electric discharge machining method.

The multilayer through-wiring board of the above fourth embodiment can be modified as follows.
Similarly to the case where the material of the through wiring is silicon, the pillar portion 26 may be formed by forming a plurality of grooves on the surface of the metal flat plate 6 with a cutting machine such as a dicing machine.

The multilayer through wiring board of the above embodiment can be modified as follows.
(1) Although the mother phase of the resin sealing body 4 is the epoxy resin 31, the resin sealing body 4 is not limited to the epoxy resin 31 as long as it is an insulating resin. For example, a green sheet of silicon resin, prepreg, or ceramic may be used. Moreover, if the mother phase of the resin sealing body 4 is an insulator, it will not be limited to resin. For example, glass may be used.

(2) The material of the column part 26 is not limited to a semiconductor such as silicon or Cu as long as it is a conductive material.

(3) A multilayer penetrating wiring substrate may be fabricated by laminating a penetrating wiring substrate fabricated from a silicon pillar and a penetrating wiring substrate fabricated from a metal pillar. Silicon pillars can be machined thinner than metal pillars, but have high resistance. Therefore, silicon is used for the through wiring board having fine wiring, and a metal having low resistance is used for the other through wiring boards, and these through wiring boards are laminated to produce a multilayer through wiring board. May be.

  It is also possible to combine one or a plurality of embodiments and modifications. It is possible to combine the modified examples in any way.

  The above description is merely an example, and the present invention is not limited to the above embodiment.

It is a figure which shows the structure of the multilayer penetration wiring board in the 1st Embodiment of this invention. 2A is a plan view of the silicon wafer and a partial cross-sectional view of the AA cross section of the plan view, and FIG. 2B is a plan view of the silicon wafer in which the alignment opening is formed and a BB cross section of the plan view. FIG. 2C is a plan view of the silicon wafer in which the alignment concave portion is formed, and a partial cross-sectional view in the CC cross section of the plan view. 3A is a plan view of the alignment recess, and FIG. 3B is a DD cross-sectional view of FIG. FIG. 4A is a plan view of a silicon wafer on which a resist line pattern is formed and a partial cross-sectional view of the EE cross section of the plan view, and FIG. 4B is a plan view of the silicon wafer obtained by etching the first protective film. FIG. 4C is a partial cross-sectional view of the silicon wafer from which the resist is removed, and FIG. 4C is a partial cross-sectional view of the GG cross-section of the plan view. FIG. 5A is a plan view of the silicon wafer on which the second protective film is formed and a partial cross-sectional view in the HH cross section of the plan view. FIG. 5B is a plan view of the silicon wafer on which the resist line pattern is formed. FIG. 5C is a plan view and a perspective view of a silicon wafer obtained by etching the second protective film. 6A is a plan view and a perspective view of the silicon wafer from which the resist is removed, and FIG. 6B is a plan view and a perspective view of the silicon wafer subjected to crystal anisotropic etching, and FIG. (A) and (B) are a plan view and a perspective view of a silicon wafer on which a pillar portion is formed. It is a figure for explaining the surface of the resin filling process, the polishing process, and the electrode forming process in the first embodiment of the present invention. FIG. 8A is a plan view of a silicon wafer on which a first protective film and a second protective film are formed, and a partial cross-sectional view in the II cross section of the plan view, and FIG. 8B forms a resist line pattern. FIG. 8C is a plan view of the silicon wafer and a partial cross-sectional view of the JJ cross section of the plan view, and FIG. 8C is a plan view of the silicon wafer from which the protective film exposed from the resist is removed and the KK cross section of the plan view. FIG. FIG. 9A is a plan view of a silicon wafer subjected to crystal anisotropic etching and a partial cross-sectional view in the LL cross section of the plan view, and FIG. 9B is a view of the silicon wafer on which the second protective film is formed. FIG. 8C is a cross-sectional view of the silicon wafer from which the first protective film is removed and a partial cross-sectional view of the NN cross-section of the plan view. FIG. 10A is a plan view and a perspective view of a silicon wafer having a cut line, and FIG. 10B is a plan view and a perspective view of a silicon wafer subjected to crystal anisotropic etching, and FIG. (A) and (B) are a plan view and a perspective view of a silicon wafer on which a pillar portion is formed. FIG. 11A is a plan view of a silicon wafer formed with a plurality of grooves in one direction, and FIG. 11B is a plan view of the silicon wafer formed with a plurality of grooves in the other direction. FIG. 12A is a diagram for explaining electric discharge machining, and FIG. 12B is a diagram for explaining a column portion formed by a discharge term.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Multi-layer through wiring board 1A, 1B Through wiring board 2 Silicon wafer 3 Column formation body 4 Resin sealing body 5 Metal mask 6 Metal flat plate 7 Nozzle 11 Through wiring 12 Resin 13 and 14 Electrode 21 1st protective film 22 Alignment opening Portion 23 Alignment recess 24 Resist 25 Second protective film 26, 26 A, 26 B Column 27 Flat plate

Claims (7)

A column forming body manufacturing step of manufacturing a column forming body including a flat plate portion made of silicon and a plurality of pillar portions made of silicon standing in the thickness direction of the flat plate portion from one surface of the flat plate portion; ,
A filling step of filling a space between the pillar portions of the pillar forming body with resin or glass;
Both sides of the column forming body filled with the resin or glass in the filling step are polished in the thickness direction, the column part is sealed with the resin or glass, and the polished surface of the column part is exposed on both sides. A sealing body manufacturing step of manufacturing a sealing body;
An electrode forming step of forming an electrode on the polished surface of the column portion of the sealing body. In the manufacturing method of the penetration wiring board according to claim 1,
The column forming body producing step includes forming a groove by a dicing saw on a flat plate made of silicon, or dry etching the flat plate made of silicon, or crystal anisotropic etching the flat plate made of silicon. A method of manufacturing a through wiring substrate, comprising forming a column portion. A column forming body manufacturing step of manufacturing a column forming body including a flat plate portion made of metal and a plurality of column portions made of the metal erected in the thickness direction of the flat plate portion from one surface of the flat plate portion; ,
A filling step of filling a space between the pillar portions of the pillar forming body with resin or glass;
Both sides of the column forming body filled with the resin or glass in the filling step are polished in the thickness direction, the column part is sealed with the resin or glass, and the polished surface of the column part is exposed on both sides. A sealing body manufacturing step of manufacturing a sealing body;
An electrode forming step of forming an electrode on the polished surface of the column portion of the sealing body. In the manufacturing method of the penetration wiring board according to claim 3,
The through-wiring board is characterized in that the pillar forming body forming step forms the pillar portion by forming a groove by a dicing saw on the flat plate made of the metal or by electric discharge machining the flat plate made of the metal. Manufacturing method.   A method for manufacturing a multilayer through-wiring board, comprising: a laminating step of stacking a plurality of through-wiring forming substrates produced by the method for manufacturing a through-wiring forming board according to claim 1.   A through wiring board produced by the method of manufacturing a through wiring board according to claim 1. A multilayer penetrating wiring board produced by the method for producing a multilayer penetrating wiring board according to claim 5.

Images