JP2007049066A - Semiconductor wafer as well as semiconductor chip, and method of manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor wafer capable of perform dicing with a good reliability. <P>SOLUTION: A semiconductor wafer 100 includes a plurality of semiconductor chip regions 50, and scribing regions 80, 82 which classify each of the semiconductor chip regions 50, wherein each of the semiconductor chip regions 50 has a passivation layer and the passivation layer has a slit 24 formed along the peripheries of the semiconductor chip region 50. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor wafer, a semiconductor chip, and a manufacturing method thereof.

  A semiconductor wafer in which a plurality of semiconductor chips are formed is cut by a diamond cutter or the like along a scribe line provided between the semiconductor chips and separated into individual semiconductor chips.

For example, a semiconductor wafer is cut along a scribe line after removing a passivation film and a planarizing film on the scribe line (for example, Japanese Patent Application Laid-Open No. 2003-197562).
JP 2003-197562 A

  An object of the present invention is to provide a semiconductor wafer that can be diced with high reliability. Another object of the present invention is to provide a semiconductor chip manufacturing method capable of manufacturing a semiconductor chip with high reliability and a semiconductor chip obtained by the manufacturing method.

The semiconductor wafer according to the present invention is
A plurality of semiconductor chip regions;
A scribe region that divides each of the semiconductor chip regions,
The semiconductor chip region has a passivation layer,
The passivation layer has a slit formed along the periphery of the semiconductor chip region.

  In this semiconductor wafer, the passivation layer has the slit formed along the periphery of the semiconductor chip region. Thereby, it is possible to suppress the occurrence of chipping, peeling, or the like in the passivation layer formed inside the slit. The reason for this will be described later.

In the semiconductor wafer according to the present invention,
The semiconductor chip region is
An interlayer insulating layer formed below the passivation layer;
A substrate formed below the interlayer insulating layer,
The slit passes through the interlayer insulating layer,
The slit can expose the upper surface of the substrate.

  In the description according to the present invention, the term “downward” refers to, for example, “other specific thing (hereinafter referred to as“ B ”) formed in“ downward ”of a specific thing (hereinafter referred to as“ A ”)”. Etc. In the description according to the present invention, in the case of this example, the case where B is formed directly under A and the case where B is formed under other via A The word “downward” is used as an expression including “.”.

The semiconductor chip according to the present invention is
A semiconductor chip having a passivation layer,
The passivation layer has a slit formed along the periphery of the semiconductor chip.

A method for manufacturing a semiconductor chip according to the present invention includes:
Preparing a semiconductor wafer having a passivation layer;
Opening the passivation layer and forming an opening in a predetermined region on the scribe region and the pad portion of the semiconductor chip region;
Forming a slit in the passivation layer along the periphery of the semiconductor chip region;
Cutting the semiconductor wafer along the scribe region.

In the method for manufacturing a semiconductor chip according to the present invention,
The step of forming the opening and the step of forming the slit can be performed in the same step.

  Preferred embodiments of the present invention will be described below with reference to the drawings.

  1. First, the semiconductor wafer 100 according to the present embodiment will be described. FIG. 1 is a plan view schematically showing a semiconductor wafer 100 according to the present embodiment. 2 is a view showing a cross section taken along line II-II in FIG. 3 is a view showing a cross section taken along line III-III in FIG. In FIG. 1, for convenience, four shots (first to fourth shots 90a to 90d) of the exposure shots of the exposure apparatus are illustrated, but the number of shots is not particularly limited. In the example shown in the drawing, five semiconductor chip regions 50 are arranged in the X direction and one in the Y direction in one shot of the exposure apparatus, but the number arranged in each direction is also different. It is not necessarily limited.

  As shown in FIG. 1, the semiconductor wafer 100 according to the present embodiment includes a plurality of semiconductor chip regions 50, a first scribe region 80, and a second scribe region 82. In the semiconductor chip region 50 shown in FIG. 1, only the slit 24 is schematically shown, and the other members are not shown. The slit 24 will be described in detail later.

  As shown in FIG. 1, the semiconductor chip region 50 has a rectangular (including a square) planar shape. In the illustrated example, the semiconductor chip region 50 has a rectangular planar shape, the short side is parallel to the first direction (X direction), and the long side is the second direction (Y direction) orthogonal to the first direction. Parallel to

  In the semiconductor chip region 50, a semiconductor element (not shown) such as a MOS transistor, a wiring layer (not shown), an element isolation region 16 (see FIGS. 2 and 3), and the like are formed near the surface of the substrate 10. Has been. As shown in FIGS. 2 and 3, first to fifth interlayer insulating layers 12 a to 12 e are sequentially formed on the substrate 10. A guard ring 30 is formed on the substrate 10. The guard ring 30 surrounds semiconductor elements and the like in the semiconductor chip region 50 and can prevent moisture from entering from the outside of the guard ring 30. The guard ring 30 can be formed, for example, by alternately stacking plug layers 32 made of tungsten and metal layers 34 made of aluminum.

  A passivation layer 20 is formed on the fifth interlayer insulating layer 12e. As shown in FIGS. 1 to 3, the passivation layer 20 has a slit 24 formed along the periphery of the semiconductor chip region 50. The passivation layer 20 can be divided into a first passivation portion 26 and a second passivation portion 28 by the slit 24. The first passivation part 26 is formed outside the slit 24 in plan view. In the illustrated example, the first passivation portion 26 can be formed between the slit 24 and the first opening 84 and between the slit 24 and the second opening 86. The second passivation portion 28 is formed inside the slit 24 in plan view. In the illustrated example, the second passivation portion 28 can be surrounded by the slit 24.

  As shown in FIG. 1, the slit 24 can be formed, for example, in a rectangular ring shape in plan view. That is, as shown in FIGS. 1 and 2, the slit 24 includes two linear slits parallel to the first direction (X direction) and two linear slits parallel to the second direction (Y direction). These slits can be formed by being continuous.

  A pad portion 18 is formed on the fifth interlayer insulating layer 12e. In a predetermined region on the pad portion 18, the passivation layer 20 is opened, and an opening portion 22 is formed. In the semiconductor chip region 50, illustration of a wiring layer formed on each interlayer insulating layer, a contact layer for electrically connecting the upper and lower wiring layers, and the like are omitted.

  As shown in FIG. 1, the first scribe region 80 is formed along the first direction (X direction) and divides each of the semiconductor chip regions 50 arranged in the second direction (Y direction). . That is, the first scribe region 80 is provided between the short sides of the adjacent semiconductor chip regions 50. As shown in FIG. 1, the second scribe region 82 is formed along the second direction (Y direction) and divides each of the semiconductor chip regions 50 arranged in the first direction (X direction). . That is, the second scribe region 82 is provided between the long sides of the adjacent semiconductor chip regions 50. The width of the first scribe region 80 can be wider than the width of the second scribe region 82. That is, the distance between the short sides of the adjacent semiconductor chip regions 50 can be made longer than the distance between the long sides of the adjacent semiconductor chip regions 50. Mark regions 60 and 62 and a TEG region 70 can be arranged in the wide first scribe region 80. Further, the mark regions 60 and 62 and the TEG region 70 may not be arranged in a region other than the region intersecting the first scribe region 80 in the narrow second scribe region 82. Thereby, since the width of the second scribe region 82 between the long sides having a larger number than the first scribe region 80 between the short sides of the semiconductor chip region 50 can be made as small as possible, one semiconductor wafer 100 The degree of integration and yield of the hit semiconductor chip region 50 can be improved.

  As shown in FIG. 2, in the first scribe region 80, a conductive layer 72 made of, for example, aluminum is formed on each interlayer insulating layer. The conductive layer 72 constitutes, for example, various marks in the mark areas 60 and 62, wiring in the TEG area 70, and the like. On the first scribe region 80, the passivation layer 20 is opened, and the first opening 84 can be formed. The first opening 84 can penetrate the passivation layer 20, and further, the first interlayer 84 can open the fifth interlayer insulating layer 12 e halfway. In plan view, the region where the first opening 84 is formed can coincide with the first scribe region 80. In the first scribe region 80, for example, a contact layer for electrically connecting the upper and lower conductive layers 72 is not shown.

  On the other hand, in the second scribe region 82, the mark region and the TEG region can not be arranged in a region other than the region intersecting the first scribe region 80, so that the conductive layer formed in the first scribe region 80. A conductive layer such as 72 may not be formed (see FIG. 3). In other words, since the mark regions 60 and 62 and the TEG region 70 can be disposed in the second scribe region 82 in the region intersecting with the first scribe region 80, the conductive layer 72 is formed. Can do. On the second scribe region 82, the passivation layer 20 is opened, and a second opening 86 can be formed. Similar to the first opening 84 described above, the second opening 86 can penetrate the passivation layer 20 as shown in FIG. 3. Further, the second opening 86 allows the fifth interlayer insulating layer 12 e to pass through the second opening 86. Can be opened halfway. In a plan view, the region where the second opening 86 is formed can coincide with the second scribe region 82.

  As shown in FIG. 1, the mark areas 60 and 62 can include, for example, an alignment mark area 60 and an inspection mark area 62. In the alignment mark region 60, for example, a mark 61 for detecting the alignment position of the photomask during exposure by the exposure apparatus is disposed. In the inspection mark area 62, for example, a mark 63 for inspecting the overlay deviation between the lower layer device pattern and the upper layer device pattern formed above the substrate 10 is disposed. Various TEGs 71 are arranged in the TEG region 70 as shown in FIG.

  A plurality of (10 in the illustrated example) semiconductor chip regions 50 are arranged in the X direction, and a plurality (two in the illustrated example) are arranged in the Y direction. In the X direction, each semiconductor chip region 50 sandwiches the second scribe region 82, and in the Y direction, each semiconductor chip region 50 sandwiches the first scribe region 80.

  2. Next, a method for manufacturing a semiconductor chip according to the present embodiment will be described. 4 to 8 are cross-sectional views schematically showing one manufacturing process of the semiconductor chip according to the present embodiment. 9 and 10 are cross-sectional views schematically showing a semiconductor chip 500 obtained by the semiconductor chip manufacturing method according to the present embodiment. 4, 8, and 9 correspond to the cross-sectional view shown in FIG. 2, and FIGS. 5 to 7 correspond to the cross-sectional view shown in FIG. 3, respectively.

  (1) First, a semiconductor wafer having a passivation layer 20 is prepared. As shown in FIGS. 4 and 5, the passivation layer 20 is formed on the entire upper surface of the semiconductor wafer. More specifically, the passivation layer 20 is formed on the fifth interlayer insulating layer 12e, the guard ring 30, the pad portion 18, and the like. As the passivation layer 20, for example, a film in which a silicon oxide layer and a silicon nitride layer are stacked in this order can be used.

  (2) Next, a predetermined region of the passivation layer 20 is opened using, for example, a known lithography technique and etching technique. 2 and 3, a first opening 84 is formed on the first scribe region 80, a second opening 86 is formed on the second scribe region 82, and the pad portion 18 is formed. An opening 22 is formed in a predetermined region. Further, the slit 24 is formed in the passivation layer 20 along the periphery of the semiconductor chip region 50. As described above, the first opening 84, the second opening 86, and the slit 24 can be formed in the same process as the opening 22 on the pad portion 18. Thereby, a manufacturing process can be simplified. In this step, the passivation layer 20 is etched so that the upper part of the fifth interlayer insulating layer 12e in the formation region of the first opening 84, the second opening 86, and the slit 24 is formed as shown in FIGS. Overetching can be performed.

  (3) Next, dicing is performed along the second scribe region 82 (that is, in the Y direction). Specifically, it is as follows.

  First, as shown in FIGS. 1 and 6, a groove 47 (see FIG. 7) is formed along the second scribe region 82 using the first blade 40. As shown in FIG. 6, the first blade 40 cuts the first to fifth interlayer insulating layers 12 a to 12 e in the second scribe region 82 and cuts the substrate 10 halfway. Although not shown, the conductive layer 72 formed in the region of the second scribe region 82 that intersects the first scribe region 80 can be cut and removed by the first blade 40.

  Next, as shown in FIGS. 1 and 7, using the second blade 48, the semiconductor wafer 100 (specifically, the substrate 10) is moved along the groove 47 formed along the second scribe region 82. Disconnect. The second blade 48 is narrower than the first blade 40 described above.

  In this manner, first, the formation layer on the substrate 10, particularly the conductive layer 72 made of aluminum or the like is removed using the first blade 40 having a large width, and then the semiconductor wafer 100 is cut using the second blade 48 having a small width. By doing so, it is possible to suppress the occurrence of chipping.

  (4) Next, dicing is performed along the first scribe region 80 (that is, in the X direction). Specifically, it is as follows.

  First, as shown in FIG. 1 and FIG. 8, the first dicing method using a wide blade and a narrow blade, as in the dicing performed along the second scribe region 82 described above. Dicing is performed along one end of the scribe region 80. That is, dicing is performed along the region inside the first scribe region 80 and adjacent to one of the semiconductor chip regions 50.

  Next, similarly, as shown in FIGS. 1 and 8, dicing is performed along the other end of the first scribe region 80. That is, dicing is performed along the region inside the first scribe region 80 and adjacent to the other semiconductor chip region 50 among the adjacent semiconductor chip regions 50. FIG. 8 is a diagram schematically showing a cross section after dicing along the first scribe region 80.

  (5) Through the above steps, the semiconductor chip 500 can be manufactured as shown in FIGS. FIG. 9 is a cross section taken along the line II-II in FIG. 1 and shows a cross section of the semiconductor chip 500 after the dicing process described above. FIG. 10 is a cross section taken along the line III-III in FIG. 1 and shows a cross section of the semiconductor chip 500 after the dicing process described above.

  As shown in FIG. 9, the first side surface 41 along the first direction (X direction) of the substrate 10 has a first step 43. Similarly, as shown in FIG. 10, the second side surface 45 along the second direction (Y direction) of the substrate 10 also has a second step 49. As described above, the first step 43 and the second step 49 are formed by dicing in two stages using a wide blade and a narrow blade.

  (6) In the above-described example, a case where dicing is performed along the first scribe region 80 (that is, in the X direction) after dicing is performed along the second scribe region 82 (that is, in the Y direction). However, this order can be reversed.

  In the above-described example, when dicing along the first scribe region 80, one end of the first scribe region 80 is cut with a wide blade and a narrow blade and then the other end. Although the case where a part is cut | disconnected was demonstrated, it is not necessarily limited to this example. For example, when forming a groove using a wide blade at a predetermined end of the first scribe region 80, at the same time, the other end already formed with the groove is cut by a narrow blade. You can also go.

  3. In the present embodiment, the passivation layer 20 has a slit 24 formed along the periphery of the semiconductor chip region 50. Thereby, it is possible to suppress the occurrence of chipping or peeling in the second passivation portion 28. The reason for this is as follows.

  For example, when dicing is performed along the first scribe region 80 and the second scribe region 82, the blade may shake and deviate from a predetermined cutting position. As a result, for example, the blade may hit the passivation layer 20 (first passivation portion 26) formed outside the slit 24. Then, chipping (peeling) or peeling may occur in the first passivation unit 26. According to the present embodiment, the slit 24 is provided between the passivation layer 20 (second passivation portion 28) formed inside the slit 24 and the first passivation portion 26. That is, the second passivation unit 28 and the first passivation unit 26 can be physically separated. Thereby, for example, even if chipping or peeling occurs in the first passivation part 26, it is possible to suppress occurrence of chipping or peeling in the second passivation part 28. Therefore, according to the present embodiment, the semiconductor wafer 100 can be diced with high reliability. That is, the semiconductor chip 500 can be manufactured with high reliability.

  4). Next, a modification according to this embodiment will be described. Note that the modifications described below are merely examples, and are not limited thereto.

  In the above-described example, the case where the first opening 84, the second opening 86, the slit 24, and the opening 22 on the pad portion 18 are formed in the same process has been described. It can also be formed. For example, the slit 24 can be formed in a single step, and for example, as shown in FIG. 11, the slit 24 can be formed so as not to penetrate the passivation layer 20. Further, for example, the slit 24 can be formed in a single step, and for example, as shown in FIG. 12, the slit 24 can be formed so as to penetrate all of the first to fifth interlayer insulating layers 12a to 12e. In this case, the upper surface of the substrate 10 can be exposed by the slit 24. According to this aspect, the slit 24 divides the passivation layer 20 into an outer portion (first passivation portion 26) and an inner portion (second passivation portion 28), and further, the first to first portions in the semiconductor chip region 50. The fifth interlayer insulating layers 12a to 12e can be divided into an outer portion and an inner portion. Thereby, it can suppress that chipping, peeling, etc. generate | occur | produce in the inner part of the 1st-5th interlayer insulation layers 12a-12e. The reason for this is the same as the above-described reason that it is possible to suppress occurrence of chipping or the like in the second passivation unit 28 according to the present embodiment. Therefore, according to this aspect, the semiconductor wafer 100 can be diced with higher reliability. 11 and 12 correspond to the cross-sectional view shown in FIG.

  In the above-described example, the case where the slits 24 are continuous in the plan view has been described. However, for example, as illustrated in FIG. 13, the slits 24 may not be continuous. Further, for example, as shown in FIG. 14, the slit 24 can be formed only along the long side direction (second direction) of the semiconductor chip region 50. Similarly, although not shown, for example, the slit 24 may be formed only along the short side direction (first direction) of the semiconductor chip region 50. 13 and 14 are plan views schematically showing the shape of the slit 24 in one semiconductor chip region 50. FIG.

  5. As described above, the embodiments of the present invention have been described in detail. However, those skilled in the art can easily understand that many modifications can be made without departing from the novel matters and effects of the present invention. . Accordingly, all such modifications are included in the scope of the present invention.

The top view which shows typically the semiconductor wafer which concerns on this embodiment. The figure which shows the cross section in the II-II line | wire of FIG. The figure which shows the cross section in the III-III line of FIG. Sectional drawing which shows typically one manufacturing process of the semiconductor chip which concerns on this embodiment. Sectional drawing which shows typically one manufacturing process of the semiconductor chip which concerns on this embodiment. Sectional drawing which shows typically one manufacturing process of the semiconductor chip which concerns on this embodiment. Sectional drawing which shows typically one manufacturing process of the semiconductor chip which concerns on this embodiment. Sectional drawing which shows typically one manufacturing process of the semiconductor chip which concerns on this embodiment. FIG. 3 is a cross-sectional view schematically showing the semiconductor chip according to the embodiment. FIG. 3 is a cross-sectional view schematically showing the semiconductor chip according to the embodiment. Sectional drawing which shows typically a part of semiconductor wafer which concerns on a modification. Sectional drawing which shows typically a part of semiconductor wafer which concerns on a modification. The top view which shows typically the slit in the semiconductor chip area | region which concerns on a modification. The top view which shows typically the slit in the semiconductor chip area | region which concerns on a modification.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 board | substrate, 12a-12e 1st-5th interlayer insulation layer, 16 element isolation region, 18 pad part, 20 passivation layer, 22 opening part, 24 slit, 26 1st passivation part, 28 2nd passivation part, 30 guard ring , 32 Plug layer, 34 Metal layer, 40 First blade, 41 First side, 43 First step, 45 Second side, 47 Groove, 48 Second blade, 49 Second step, 50 Semiconductor chip region, 60 Alignment mark Area, 61 mark, 62 inspection mark area, 63 mark, 70 TEG area, 71 TEG, 72 conductive layer, 80 first scribe area, 82 second scribe area, 84 first opening, 86 second opening, 90a ˜90d First to fourth shots, 100 semiconductor wafer, 500 semiconductor chip

Claims (5)

A plurality of semiconductor chip regions;
A scribe region that divides each of the semiconductor chip regions,
The semiconductor chip region has a passivation layer,
The said passivation layer is a semiconductor wafer which has a slit formed along the periphery of the said semiconductor chip area | region. In claim 1,
The semiconductor chip region is
An interlayer insulating layer formed below the passivation layer;
A substrate formed below the interlayer insulating layer,
The slit passes through the interlayer insulating layer,
A semiconductor wafer, wherein the upper surface of the substrate is exposed by the slit. A semiconductor chip having a passivation layer,
The said passivation layer is a semiconductor chip which has a slit formed along the periphery of the said semiconductor chip. Preparing a semiconductor wafer having a passivation layer;
Opening the passivation layer and forming an opening in a predetermined region on the scribe region and the pad portion of the semiconductor chip region;
Forming a slit in the passivation layer along the periphery of the semiconductor chip region;
And a step of cutting the semiconductor wafer along the scribe region. In claim 4,
The method of manufacturing a semiconductor chip, wherein the step of forming the opening and the step of forming the slit are performed in the same step.

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