JP2003258049A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase the number of semiconductor chips obtained from one semiconductor wafer when the chip of a slender square shape in plane is fabricated. <P>SOLUTION: A method for manufacturing a semiconductor device comprises steps of designing the width of a scribing region SCT extended in a direction parallel to the extending direction of the short side of a semiconductor chip forming region 1A in a degree in which the number of the chips obtained from one semiconductor wafer 1 is not decreased as much as possible; and designing the width of a scribing region SCY extended in a direction parallel to the extending direction of the long side of the semiconductor chip forming region 1A in a degree in which the region 1A is not cut at cutting the wafer 1 into individual chips. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of designing a scribe region in a semiconductor wafer and a TEG (Te
The present invention relates to a technique effective when applied to a wiring arrangement method for forming a st element group).

[0002]

2. Description of the Related Art In the process of manufacturing a semiconductor device, a plurality of rectangular semiconductor chip forming regions are regularly arranged in the vertical and horizontal directions on a main surface of a semiconductor wafer with a scribe region (divided region) therebetween. . Further, in the scribe area, wirings for forming TEG for product evaluation and alignment marks for correctly overlapping the mask patterns are arranged.

Regarding the TEG, for example, published by Nikkan Kogyo Shimbun Co., Ltd. on March 20, 1999,
It is described in the Semiconductor Term Dictionary, p162.

[0004]

The width of the scribe area is often the same in the vertical and horizontal directions.
However, the present inventors have found that the following problems occur when the width of the scribe region is the same in the vertical direction and the horizontal direction.

For example, an LCD (Liquid Crystal Displ
ay) In the semiconductor chip serving as a driver, the electrodes corresponding to one row of pixels in the horizontal direction or the vertical direction of the LCD are arranged in one row in the vertical direction or the horizontal direction, so that the semiconductor chip is an elongated rectangle. Therefore, if the widths of the scribe regions are the same in the short-side direction and the long-side direction of the semiconductor chip, the scribe region occupies a large proportion in the short-side direction, and there is a problem in that the semiconductor wafer is wasted in many regions. It was

The present inventors are also studying a technique for increasing the number of semiconductor chips obtained by narrowing the width of the scribe region. Among them, the present inventors
It has been found that the following problems exist in the technique of narrowing the width of the scribe region.

That is, since the wiring and the alignment mark that form the TEG are arranged in the scribe area, if the width of the wiring and the alignment mark is attempted to be narrowed, there is a problem that the wiring and the alignment mark cannot be narrowed. there were. Also, when dividing into individual semiconductor chips by dicing, the wiring and alignment marks arranged in the scribe area are also cut, so the chips of these wiring and alignment marks become foreign matter and adhere to the semiconductor chips. However, there is a problem that the yield of the semiconductor device is reduced. If dicing is performed while avoiding the center of the scribe region in order to prevent the generation of such chips, there is a problem that a predetermined semiconductor chip forming region is cut and the number of semiconductor chips to be obtained decreases.

An object of the present invention is to provide a technique capable of increasing the number of semiconductor chips to be obtained when manufacturing elongated rectangular semiconductor chips from a semiconductor wafer.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0010]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, according to the present invention, a plurality of chip forming regions each having a semiconductor element and a first wiring which is composed of a long side and a short side and is electrically connected to the semiconductor element, and the plurality of chip forming regions are divided to define the short side. A semiconductor wafer having a first divided region extending in a side direction and a second divided region which divides the plurality of chip formation regions and extends in the long side direction and has a relatively narrower width than the first divided region. And a step of dividing the first divided region into a wiring forming region and a cutting region in the width direction, and a second forming process in the wiring forming region.
After forming the wiring, the step of cutting the semiconductor wafer along the second divided region and the cutting region to form a plurality of semiconductor chips is included.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. In all the drawings for explaining the embodiments, members having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

The semiconductor device of this embodiment has, for example, L
It is a CD driver, and its manufacturing method will be described with reference to the flowchart shown in FIG.

First, a circuit forming the LCD driver of this embodiment is designed. Next, the layout of the semiconductor chip formation region and the layout when the circuit is arranged in the semiconductor chip formation region are designed. Further, the layout of the scribe area for dividing the semiconductor wafer into individual semiconductor chip forming areas is designed. Next, a mask used for transferring these layouts to a semiconductor wafer is designed. After that, the process proceeds to the step of forming a semiconductor element and wiring using the mask (previous step).

FIG. 2 is a plan view showing the semiconductor chip forming region 1A and the scribe regions SCT and SCY on the main surface (element forming surface) of the semiconductor wafer 1. As shown in FIG. 2, the semiconductor chip forming region 1A has a flat and elongated quadrangle, and its long sides are parallel to the extending direction of the orientation flat OF of the semiconductor wafer 1.
The short sides are arranged so as to be perpendicular to the extending direction of the orientation flat OF. The individual semiconductor chip forming areas 1A are the same as the semiconductor chip forming areas 1A.
Of the scribe region (first divided region) SCT extending in a direction parallel to the extending direction of the short side of the semiconductor chip and the scribe region extending in a direction parallel to the extending direction of the long side of the semiconductor chip forming region 1A. It is divided by the area (second divided area) SCY.

Next, the pre-process will be described with reference to FIGS.

First, as shown in FIG. 3, a semiconductor wafer 1 made of, for example, single crystal silicon is heat-treated to form a thin silicon oxide film (pad oxide film) on its main surface.
Next, a CV silicon nitride film is formed on the silicon oxide film.
After the deposition by the D (Chemical Vapor Deposition) method, the silicon nitride film and the silicon oxide film in the element isolation region are removed by dry etching using the photoresist film as a mask. The silicon oxide film is formed for the purpose of relieving stress applied to the semiconductor wafer 1 when the silicon oxide film embedded in the element isolation trench is densified (baked up) in a later step. In addition, since the silicon nitride film has a property of being less likely to be oxidized, it is used as a mask for preventing the surface of the semiconductor wafer 1 below (active region) from being oxidized.

Then, after depositing a silicon oxide film 2 on the semiconductor wafer 1 by the CVD method, the semiconductor wafer 1 is heat treated to improve the quality of the silicon oxide film 2. Densify. After that, the silicon oxide film 2 is polished by a chemical mechanical polishing (CMP) method using a silicon nitride film as a stopper and left inside the groove, so that the element isolation groove 3 having a flat surface is formed. To form. Then, after removing the silicon nitride film remaining on the active region of the semiconductor wafer 1 by wet etching using hot phosphoric acid, the semiconductor wafer 1 is subjected to impurity ions having a p-type conductivity type (for example, B (boron)). Ions are implanted to form the p-type well 4.

Next, as shown in FIG. 4, the semiconductor wafer 1
Is heat-treated to form a clean gate oxide film 5 on the surface of the p-type well 4. Then, for example, CVD
By the method, a polycrystalline silicon film 6, a WSi _x (tungsten silicide) film 7 and a silicon oxide film 8 are sequentially deposited from the lower layer on the main surface of the semiconductor wafer 1. Subsequently, the silicon oxide film 8, the WSi _x film 7, the polycrystalline silicon film 6 and the gate oxide film 5 are patterned by dry etching using a photoresist film (not shown) patterned by photolithography as a mask. , The gate electrode 9 made of the WSi _x film 7 and the polycrystalline silicon film 6 is formed.

Next, after removing the photoresist film used to form the gate electrode 9, as shown in FIG. 5, with the gate electrode 9 as a mask, the p-type well 4 is doped with an impurity having an n-type conductivity type. The n ⁻ type semiconductor region 10 is formed by ion-implanting As (arsenic), for example.

Next, as shown in FIG. 6, for example, CVD
After a silicon oxide film is deposited on the semiconductor wafer 1 by the method, the silicon oxide film is removed by RIE (Reactive Ion Etchi
The sidewall spacers 11 are formed on the sidewalls of the gate electrode 9 by anisotropically etching by the ng) method. Then, using the gate electrode 9 and the sidewall spacer 11 as a mask, an impurity having an n-type conductivity, such as As, is ion-implanted into the p-type well 4 to form an n ⁺ -type semiconductor region 12. Through the steps up to here, the n-channel type MISFET (semiconductor element) Qn
Can be formed.

Next, as shown in FIG. 7, an n-channel type M
An interlayer insulating film 13 on the top of ISFETQn, an interlayer insulating film 13 using a photoresist film as a mask followed by dry etching, n ⁺ -type semiconductor region 12
After forming the through hole 14 on the upper part of the
A wiring (first wiring) 15 is formed on the upper part of the wiring 3. Wiring 15
Is, for example, after depositing a metal film such as W or Al alloy on the interlayer insulating film 13 by a sputtering method,
It can be formed by patterning this metal film by dry etching using a photoresist film as a mask. The wiring may be formed in multiple layers by repeating the process of forming the interlayer insulating film 13, the through hole 14 and the wiring 15 a plurality of times.

Here, as shown in FIG.
In the step of forming, the wiring (second wiring) 15A for TEG and an alignment mark (not shown) for correctly overlapping the mask pattern are also formed in the scribe region. In the present embodiment, the width of the scribe region SCT is designed to be as wide as possible so that the number of semiconductor chips that can be obtained from one semiconductor wafer 1 does not decrease, and the width of the scribe region SCY is different for each semiconductor wafer 1. The semiconductor chip formation region 1A is designed to be narrow enough not to be cut during the step of cutting into semiconductor chips.
Further, the wiring 15A and the alignment mark are not arranged in the scribe area SCY but are arranged in the scribe area SCT. As a result, as shown in FIG. 2, the number of scribe regions SCY extending in the direction parallel to the extending direction of the long side of the semiconductor chip forming region 1A is the same as that of the short side of the semiconductor chip forming region 1A. Since the number is greater than the number of scribe regions SCT extending in the direction parallel to the extending direction, the semiconductor chip forming region 1A is further arranged in the extending direction of the short side of the semiconductor chip forming region 1A. It becomes possible. That is, it is possible to increase the number of semiconductor chips that can be obtained from one semiconductor wafer 1. Further, since the width of the scribe region SCT is widened, the wiring 15A and the alignment mark can be arranged with a margin.

Further, in the present embodiment, the scribe area SCT is the wiring formation area S in which the wiring 15A is arranged.
The semiconductor wafer 1 is divided into CT1 and a cutting region SCT2 for cutting the semiconductor wafer 1 in a later step, and the wiring 15A and the alignment mark are arranged in the wiring forming region SCT1. When the semiconductor wafer 1 is cut into individual semiconductor chips, the semiconductor wafer 1 is cut along the cutting region SCT2 so that the scribe region SCT does not pass through the center in the width direction. Thereby, the wiring 15A is formed by the cutting process.
Further, it is possible to prevent chips of the alignment mark from being generated. As a result, it is possible to prevent the chips of the wiring 15A and the alignment marks from becoming foreign matters and adhering to the semiconductor chips, which lowers the yield of the semiconductor chips.

After the wirings 15 and 15A are formed, the semiconductor wafer 1 is covered with the scribe area SCY and the cutting area SC.
The semiconductor device according to the present embodiment is manufactured by dicing along T2 and dividing into individual semiconductor chips. The hatched area in FIG. 8 indicates an actually diced area.

Although the invention made by the present inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the scope of the invention. It goes without saying that it can be changed.

For example, in the above-described embodiment, the semiconductor chip forming region has long sides parallel to the extending direction of the orientation flat of the semiconductor wafer and short sides perpendicular to the extending direction of the orientation flat. Although the case where the semiconductor chip formation region is arranged is illustrated as an example, the long side of the semiconductor chip forming region is perpendicular to the extending direction of the orientation flat of the semiconductor wafer, and the short side is parallel to the extending direction of the orientation flat. You may arrange so. Even in that case, the width of the scribe region extending in the direction parallel to the extending direction of the short side of the semiconductor chip formation region can be set so that the number of semiconductor chips obtainable from one semiconductor wafer does not decrease. Design as wide as possible, and the width of the scribe region that extends in the direction parallel to the extension direction of the long side of the semiconductor chip formation region is such that the semiconductor chip formation region is cut during the process of cutting the semiconductor wafer into individual semiconductor chips. It should be designed so narrow that it will not end up.

[0028]

The effects obtained by the typical ones of the inventions disclosed by the present application will be briefly described as follows. (1) When forming a semiconductor chip having a rectangular shape in a plane, the width of the scribe region (first divided region) extending in the direction parallel to the extending direction of the short side of the semiconductor chip forming region is 1 A scribe region (second divided region) that is designed as wide as possible so that the number of semiconductor chips that can be obtained from one semiconductor wafer does not decrease and that extends in a direction parallel to the extension direction of the long side of the semiconductor chip formation region. ) Is designed to be narrow so that it does not interfere with the process of cutting the semiconductor wafer into individual semiconductor chips, so that it is possible to further arrange the semiconductor chip forming region in the extending direction of the short side of the semiconductor chip forming region. it can. That is, the number of semiconductor chips that can be obtained from one semiconductor wafer can be increased. (2) When forming a semiconductor chip having an elongated rectangular shape in a plane, a scribe region (first divided region) extending in a direction parallel to the extending direction of the short side of the semiconductor chip forming region is used for TEG. Since the wiring is divided into a wiring forming area in which the wiring is arranged and a cutting area for cutting the semiconductor wafer, and the wiring for the TEG (second wiring) is arranged in the wiring forming area, in the step of cutting the semiconductor wafer, It is possible to prevent the generation of chips from the TEG wiring. That is, it is possible to prevent the chips of the wiring for the TEG from becoming foreign matters and adhering to the semiconductor chips, which lowers the yield of the semiconductor chips.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a manufacturing process of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a plan view illustrating a layout of a semiconductor chip forming region and a scribe region during a manufacturing process of a semiconductor device according to an embodiment of the semi-invention.

FIG. 3 is a main-portion cross-sectional view illustrating the method for manufacturing the semiconductor device which is the embodiment of the present invention.

FIG. 4 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device subsequent to FIG.

5 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device subsequent to FIG.

FIG. 6 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device subsequent to FIG.

7 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device subsequent to FIG.

FIG. 8 is a main-portion plan view of the semiconductor device during the manufacturing process according to the embodiment of the present invention;

[Explanation of symbols]

1 Semiconductor Wafer 1A Semiconductor Chip Forming Region 2 Silicon Oxide Film 3 Element Isolation Groove 4 P-type Well 5 Gate Oxide Film 6 Polycrystalline Silicon Film 7 WSi _x Film 8 Silicon Oxide Film 9 Gate Electrode 10 n ^- Type Semiconductor Region 11 Sidewall Spacer 12 n ⁺ type semiconductor region 13 interlayer insulating film 14 through hole 15 wiring (first wiring) 15A wiring (second wiring) OF orientation flat Qn n channel type MISFET (semiconductor element) SCT scribe area (first divided area) SCT1 wiring Formation area SCT2 Cutting area SCY Scribing area (second divided area)

Claims (3)

[Claims] 1. (a) A plurality of chip forming regions each having a semiconductor element and a first wiring having a long side and a short side and electrically connecting to the semiconductor element; A first divided region extending in the lateral direction,
A step of preparing a semiconductor wafer having a plurality of chip forming regions and extending in the long side direction and having a second divided region relatively narrower than the first divided region; (b) the first divided region Dividing the region into a wiring forming region and a cutting region in the width direction, (c) forming a second wiring in the wiring forming region, (d) after the step (c), the second dividing region and the A step of cutting the semiconductor wafer along a cutting area to form a plurality of semiconductor chips. 2. (a) A plurality of chip forming regions each having a semiconductor element and a first wiring which is composed of a long side and a short side and electrically connects to the semiconductor element; A first divided region extending in the lateral direction,
A step of preparing a semiconductor wafer having a plurality of chip forming regions and extending in the long side direction and having a second divided region relatively narrower than the first divided region; (b) the first divided region Dividing the region into a wiring forming region and a cutting region in the width direction, (c) forming a second wiring in the wiring forming region, (d) after the step (c), the second dividing region and the A step of cutting the semiconductor wafer along a cutting area to form a plurality of semiconductor chips, wherein the cutting area does not include a center in the width direction of the first divided area. Production method. 3. (a) A plurality of chip formation regions each having a semiconductor element and a first wiring having a long side and a short side and electrically connected to the semiconductor element; A first divided region extending in the lateral direction,
A step of preparing a semiconductor wafer having a plurality of chip forming regions and extending in the long side direction and having a second divided region relatively narrower than the first divided region; (b) the first divided region Dividing the region into a wiring forming region and a cutting region in the width direction, (c) forming a second wiring for evaluating the semiconductor element and the first wiring in the wiring forming region, (d) the ( After the step c), the method includes a step of cutting the semiconductor wafer along the second divided area and the cutting area to form a plurality of semiconductor chips.