KR20060084649A - Semiconductor chip - Google Patents

Abstract

There is provided a semiconductor chip capable of preventing the propagation of cracks. The semiconductor chip is formed around a semiconductor substrate having an active region and the active region, the first line having a first cut portion formed at a predetermined interval, and the second cut portion spaced apart from the first line at a predetermined interval and staggered from the first cut portion. And a crack prevention structure having an omega shape having a second line formed thereon, and a third line bending and connecting the first cut portion and the second cut portion two or more times.

Cracks, Crack Isolation, Patterns

Description

Semiconductor chip

1 is a plan view of a semiconductor chip according to an embodiment of the present invention.

2 is a plan view of a crack prevention structure according to an embodiment of the present invention.

3 is a cross-sectional view taken along the line II ′ of FIG. 2.

Figure 4 is a plan view of a crack prevention structure according to another embodiment of the present invention.

FIG. 5 is a cross-sectional view taken along the line II-II ′ of FIG. 4.

6 is a plan view of a crack prevention structure according to another embodiment of the present invention.

FIG. 7 is a cross-sectional view taken along line III-III ′ of FIG. 6.

8 is a plan view of a crack prevention structure according to another embodiment of the present invention.

FIG. 9 is a cross-sectional view taken along line IV-IV ′ of FIG. 8.

<Explanation of symbols on main parts of the drawings>

10: semiconductor substrate 12: active region

20: crack preventing structure 22: first line

24: second line 26: third line

The present invention relates to a semiconductor chip, and more particularly to a semiconductor chip comprising a crack prevention structure.

Generally, a semiconductor chip is made of a plurality of semiconductor chips on a wafer and then separated into individual semiconductor chips. In this case, a process of cutting a wafer on which a plurality of semiconductor chips are formed and separating the wafer into individual semiconductor chips is called a wafer dicing process. The wafer dicing process cuts along a scribe line formed between a plurality of semiconductor chips by using a blade rotating at a high speed. When the wafer dicing process is performed, cracks may occur in the semiconductor chip due to collision between the wafer particles and the blades. Such cracks may propagate from the edge region of the semiconductor chip to the active region, causing damage to the semiconductor chip and degrading its performance.

Thus, a crack stop is formed in the edge region of each semiconductor chip to prevent cracks from propagating to the active region. However, the crack preventing material formed in the conventional semiconductor chip does not sufficiently prevent the cracks generated during the wafer dicing process from propagating to the active region of the semiconductor chip. In addition, since the crack preventive material filled with air among the conventional crack preventive materials is formed by additionally performing a diffusion, etching, and mask process, there is a problem in that the economic cost of forming a semiconductor chip increases.

 SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a semiconductor chip including a crack preventing structure capable of more effectively preventing cracks caused during a wafer dicing process.

The technical problem to be achieved by the present invention is not limited to the above-mentioned problem, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

In order to achieve the above technical problem, a semiconductor chip according to an embodiment of the present invention is formed around a semiconductor substrate having an active region and an active region, and includes a first line having a first cut portion at a predetermined interval, And an omega type crack prevention structure having a second line spaced at regular intervals and staggered from the first cutout to form a second cutout, and a third line bending and connecting the first cutout and the second cutout two or more times. do.

Specific details of other embodiments are included in the detailed description and the drawings.

Advantages and features of the present invention, and methods for achieving them will be apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view of a semiconductor chip according to an embodiment of the present invention.

As shown in FIG. 1, a semiconductor chip according to an exemplary embodiment of the present invention may include a semiconductor substrate 10 and a crack preventing structure 20.

A plurality of semiconductor chips are formed on the wafer and cut into respective semiconductor chips, so that the semiconductor chips cut from the wafer are formed with four-sided edge regions 14.

The semiconductor substrate 10 includes an active area 12 at a central portion thereof, so that transistors, capacitors, wirings, and the like are formed on the active area 12.

The crack stop structure 20 is formed around the active region 12 of the semiconductor substrate 10 to rotate at a high speed during a dicing process for cutting a plurality of semiconductor chips formed on the wafer. This is to prevent cracks caused by the blades from propagating to the active region 12 of the semiconductor substrate 10.

The crack prevention structure 20 is formed in an omega form, which is a pattern that can disperse the energy propagated to the active region 12 as much as possible. The pattern of the crack preventing structure 20 will be described in detail with reference to FIGS. 2 to 9.

2 is a plan view of a crack prevention structure according to an embodiment of the present invention.

As shown in FIG. 2, the crack prevention structure 20 consists of a first line 22, a second line 24, and a third line 26. At this time, the first lines 22 and the second lines 24 are parallel to each other, and cut lines 23 and 25 are formed in the lines at which the lines are cut at regular intervals. At this time, the 1st cut part 23 formed in the 1st line 22 and the 2nd cut part 25 formed in the 2nd line 24 are mutually offset. The first line 22 and the second line 24 having the cut portions 23 and 25 formed thereon are bent two or more times to form the first cut portion 23 and the second cut portion 25 by the third line 26 formed therein. ) Is connected. In detail, the third line 26 has a predetermined portion formed in parallel with the first line 22 and the second line 24 to vertically connect the first cutout 23 and the second cutout 25. . The crack preventing structure 20 is formed of a metal material to prevent cracks from propagating to the active region 12 of the semiconductor substrate 10.

The crack prevention structure 20 having such a pattern has a portion bent at least two times in the third line 26 connecting the first line 22 and the second line 24, that is, the first line 22 and A portion parallel to the second line 24 is included, thereby increasing the barrier to prevent cracking. Specifically, in the exemplary embodiment of the present invention, since the third line 26 is bent twice, one portion parallel to the first line 22 and the second line 24 is formed. In order to disperse the propagation energy of the larger crack, two or more bent portions of the third line 26 are formed to form one or more portions parallel to the first line 22 and the second line 24 so as to crack the propagation energy of the larger crack. It is possible to further increase the barrier that can prevent propagation.

A cross-sectional view of such a crack prevention structure is shown in FIG. 3. 3 is a cross-sectional view taken along the line II ′ of FIG. 2.

As shown in FIG. 3, the crack preventing structure 20 is formed in a form in which metal layers are stacked. Each metal layer includes a metal contact MC connected to a semiconductor substrate, metal lines M1 to M4, vias V1 to V4 connecting metal lines, and a terminal pad (TV). At this time, each of the metal layers has the same width and is constantly aligned to form a barrier. In this case, aluminum, copper, or tungsten may be used as the metal material for forming the metal layer.

Such a method of forming the crack preventing structure 20 includes forming a gate G on a wafer W for forming a semiconductor chip, and then insulating such as a silicon oxide film on the wafer W including the gate G. The material is deposited to form the first interlayer insulating film D0. Next, the first interlayer insulating film D0 is patterned to form a metal contact MC for electrically connecting the wafer W and the metal line M1. In this patterning process, the metal contact MC formed on the crack prevention structure 20 is also patterned at the same time.

As described above, patterning is performed on the first interlayer insulating layer D0 to form the metal contact MC, and then the region where the metal contact MC is to be formed is partially etched. A metal material is then deposited and planarized on the etched portion to complete the first layer.

Next, a second interlayer insulating film D1 is formed on the first layer, and the first metal line M1 is formed in the same manner as described above. In the patterning process for defining the first metal line M1, the region where the first metal layer M1 of the crack prevention structure 20 is formed is also patterned. Then, the region in which the first metal line and the first metal layer M1 are to be formed is partially etched and a metal material is deposited to form a second layer including the first metal line M1 and the first metal layer M1.

Subsequently, the interlayer insulating film is laminated and the patterning process, etching process and deposition process as described above are repeated to form the metal line and the metal layer. Each layer formed by such a repeating process includes vias V1 to V4 and metal lines M1 to M4 and TVs electrically connecting the metal lines.

After performing the process as described above, the crack prevention structure 20 is formed by alternately stacking the metal layers MC, M1 to M4, and TVs V1 to V4. Each metal layer and via has the same width.

A terminal via formed on the uppermost layer is exposed to provide a contact surface for testing a semiconductor chip as a bonding pad.

Figure 4 is a plan view of a crack prevention structure according to another embodiment of the present invention.

The crack preventing structure 20a illustrated in FIG. 4 is formed by stacking metal layers alternately, and the planar pattern is the same as the crack preventing structure illustrated in FIG. 2. Accordingly, the third line 26a, which is composed of the first line 22a, the second line 24a, and the third line 26a, has a predetermined area parallel to the first line 22a and the second line 24a. ) Can be more effectively prevented from propagating cracks into the active region of the semiconductor substrate.                     

FIG. 5 is a cross-sectional view taken along the line II-II ′ of FIG. 4.

As shown in FIG. 5, the crack prevention structure 20a is stacked with the metal layers MC, V1 to V4, M1 to M4, and TV alternately stacked. In detail, each metal layer has the same width, and a portion of the upper metal layer and the lower metal layer are stacked to overlap each other.

As such, when the crack preventing structure 20a is formed, the surface area for dispersing the energy propagated by the crack is increased to more effectively prevent the crack from propagating to the active region of the semiconductor substrate.

The method of forming the crack preventing structure 20a is the same as the method described above, and may be formed by changing only a pattern defining a metal layer of the crack preventing structure 20a during the patterning process of each step.

6 is a plan view of a crack prevention structure according to another embodiment of the present invention.

FIG. 7 is a cross-sectional view taken along line III-III ′ of FIG. 6.

The crack prevention structure 20b shown in FIG. 6 and FIG. 7 consists of metal layers MC, V1-V4, M1-M4, and TV having two kinds of widths. In detail, the crack preventing structure 20b is formed of the metal contacts MC, the vias V1 to V4, and the metal layers M1 to M4 and the TVs. The metal contacts MC and the vias V1 to V4 are formed to have a smaller width than the metal layers M1 to M4 and TV. As such, when the metal layers having different widths are alternately stacked, a step is formed regularly, thereby increasing the surface area for dispersing the energy propagating the cracks.

8 is a plan view of a crack prevention structure according to another embodiment of the present invention.                     

The crack prevention structure 20c shown in FIG. 8 includes the first lines 22c-1 and 22c-2, the second lines 24c-1 and 24c-2 and the third lines 26c-1 and 26c-2. The crack prevention structure 20c formed in this manner is formed in double, and cuts 23c-1 and 23c-2 are formed in the first lines 22c-1 and 22c-2 and the second lines 24c-1 and 24c-2, respectively. , 25c-1, 25c-2) are formed and parallel to each other. The third lines 26c-1 and 26c-2 connect both ends of the first lines 22c-1 and 22c-2 and the second lines 24c-1 and 24c-2. It is formed in parallel with the first lines 22c-1 and 22c-2 and the second lines 24c-1 and 24c-2, and a predetermined portion thereof is formed by the first lines 22c-1 and 22c-2 and the second line. It is located in parallel with (24c-1, 24c-2).

The first crack preventing structure 20c-1 and the second crack preventing structure 20c-2 thus formed are staggered with each other to have an offset as shown in FIG. 8.

Therefore, it is possible to more effectively prevent cracks that can propagate to the active region of the semiconductor chip through the cutouts 23c-1, 23c-2, 25c-1, and 25c-2.

FIG. 9 is a cross-sectional view taken along line IV-IV ′ of FIG. 8.

As shown in FIG. 9, the dual crack prevention structure 20c is formed by stacking metal layers MC, V1 to V4, M1 to M4, and TV. In this case, as described above, the metal layers may be stacked such that the metal layers have the same width and are uniformly aligned. In contrast, the widths of the metal layers are all the same, but may be stacked alternately with each other. Further, metal layers having two kinds of widths may be formed by alternately laminating them.                     

As described above, the pattern of the crack prevention structure described in the present invention may form more barriers, thereby increasing the surface area where cracks caused during the wafer dicing process may disperse the energy propagated to the active region of the semiconductor substrate. Therefore, it is possible to more effectively prevent a crack from occurring in the active region of the semiconductor substrate and damaging the semiconductor chip.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention belongs may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. You will understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

As described above, according to the semiconductor chip of the present invention, the crack prevention structure of the omega type may disperse the energy propagated to the active region of the semiconductor substrate in a wider area. Therefore, it is possible to prevent cracks from propagating to the active region of the semiconductor substrate and damaging the semiconductor chip.

 In addition, the crack preventing structure is formed at the same time as the structures formed in the active region of the semiconductor chip during the semiconductor chip forming process, thereby reducing the semiconductor chip manufacturing process.

Claims (8)

A semiconductor substrate having an active region; And A first line formed around the active area, the first line having a first cut portion at a predetermined interval, a second line spaced apart from the first line at a predetermined interval, and having a second cut portion alternately with the first cut portion; 1. A semiconductor chip comprising an omega type crack prevention structure having a first cut portion and a third line that is bent and connected two or more times. The method of claim 1, And the first line and the second line are parallel to each other. The method of claim 2, And the third line has a predetermined area parallel to the first line or the second line. The method of claim 3, wherein And the crack preventing structure is formed in duplicate around the active region. The method of claim 4, wherein The crack prevention structure formed of a double semiconductor chip having a constant offset. The method of claim 4, wherein The crack preventing structure has a structure in which a plurality of metal layers having the same width are stacked. The method of claim 4, wherein The crack preventing structure has a structure in which a plurality of metal layers are stacked alternately with each other. The method of claim 4, wherein The crack preventing structure has a structure in which metal layers having different widths are alternately stacked.

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