JP3872031B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a scribe region in which a plurality of TEG elements are arranged in a scribe region.
[0002]
[Prior art]
Conventionally, in a manufacturing process of a semiconductor device using a silicon substrate or a compound semiconductor substrate, a semiconductor wafer having a large number of semiconductor elements formed on the substrate is composed of the large number of semiconductor elements using a diamond blade or the like during dicing. A scribe region provided around the semiconductor device region to be formed is diced (also referred to as scribing) to be divided into chip-shaped semiconductor devices. Conventionally, this scribe region has a structure in which the substrate surface is exposed. However, etching remains due to a difference in height between the scribe region and the semiconductor device region during the manufacturing process, problems such as variations in resist film thickness, and the scribe region has an interlayer. In the case of a structure having an insulating film, in a region where a plurality of mask alignment marks necessary for manufacturing are arranged, there is a problem of peeling due to side etching of the interlayer insulating film immediately below the pattern portion of the mark. It was.
[0003]
Therefore, in order to solve the above problems, the structure in which the interlayer insulating film and the passivation film are left on the entire surface of the scribe region (conventional technology 1), and the interlayer insulating film and the passivation film are left in most of the scribe region. Although there is a structure, a method (prior art 2) in which a slit groove is provided along an edge around the semiconductor device region in the passivation film on the scribe region and the passivation film in the slit groove portion is removed, and a mask In areas where there are patterns such as alignment marks, a slit groove is provided along the edge of the periphery of the semiconductor device area, and the passivation film in the slit groove portion is removed and the passivation on the scribe area in the area where there is no pattern A structure (prior art 3) for removing most of the film is disclosed in Patent Document 1 below. Hereinafter, according to FIGS. 3 to 5, the scribe areas of the related arts 1 to 3 disclosed in Patent Document 1 will be described.
[0004]
FIG. 3A is a cross-sectional view of the scribe region of the prior art 1, and FIG. 3B is a cross-sectional view of the dicing end state. As shown in FIG. 3A, by leaving the first interlayer insulating film 208 and the second interlayer insulating film 211 in the scribe region 203 provided in the periphery of the semiconductor device region 202 formed in the semiconductor substrate 201. Consideration to almost eliminate the step.
[0005]
4 (a) and 4 (b) are a cross-sectional view and a plan view of the scribe region of the above-described prior art 2. FIG. As shown in FIG. 4A, the step is almost eliminated by leaving the first interlayer insulating film 208 and the second interlayer insulating film 211 in the scribe region 203 provided around the semiconductor device region 202. The slit groove 218 is provided along the edge portion around the semiconductor device region, and the passivation film 214 in the slit groove 218 portion is removed. Thereby, it is considered that the crack 217 (see FIG. 3B) generated in the passivation film 214 at the time of dicing in the prior art 1 does not reach the passivation film 214 inside the element by the slit groove 218. Yes.
[0006]
FIG. 5 is a cross-sectional view of the scribe region of the conventional technique 3. As in FIG. 5, the step is almost eliminated by leaving the first interlayer insulating film 208 and the second interlayer insulating film 211 in the scribe region 203 provided in the periphery of the semiconductor device region 202, as in the prior art 1. However, the passivation film 214 on the scribe region is removed. Thus, consideration is given to reducing the burden on the diamond blade during dicing.
[0007]
[Patent Document 1]
Japanese Patent Laid-Open No. 3-72653 [0008]
[Problems to be solved by the invention]
In the scribe region forming method using the prior arts 1 to 3 disclosed in Patent Document 1, when the pattern of TEG elements (Test Element Group, characteristic evaluation elements) increases in the scribe region, the passive layer remaining on the scribe region is increased. -The area of the film increases. An increase in the area of the passivation film remaining on the scribe region increases the burden on the diamond blade during dicing. Further, when the passivation film on the pattern of the TEG element in the scribe region is removed, the wiring of the uppermost metal wiring layer is affected by the etching when the passivation film is removed, resulting in variations in wiring resistance. . In addition, since there is a problem that the characteristics of the TEG element change due to the absence of the passivation film, a passivation film on the pattern of the TEG element is necessary.
[0009]
The present invention has been made in view of the above-mentioned problems in the prior art, and the object thereof is to solve the above-described problems, have no influence on the characteristics of the TEG element, and to be applied to a diamond blade or the like during dicing. An object of the present invention is to provide a method of manufacturing a semiconductor device capable of forming a scribe region that can reduce the burden.
[0010]
[Means for Solving the Problems]
In order to achieve this object, a semiconductor device manufacturing method according to the present invention includes a passivation film deposited on a scribe region provided around a semiconductor device region on a semiconductor substrate in a state before dicing. It is removed from the scribe region other than the TEG body part so as to cover only the TEG body part other than the electrode pad of the TEG element provided in the scribe area. Furthermore, the method for manufacturing a semiconductor device according to the present invention is characterized in that the TEG body includes a metal wiring in the uppermost layer other than the electrode pads.
[0011]
According to the method for manufacturing a semiconductor device having the above characteristics, the scribe region can be formed without changing the characteristics of the TEG element on the scribe region and reducing the burden on the diamond blade during dicing. Can do.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of a method for manufacturing a semiconductor device according to the present invention (hereinafter referred to as “the present invention method” as appropriate) will be described with reference to the drawings.
[0013]
1A to 1D are cross-sectional views of a semiconductor device manufactured by the method of the present invention. FIG. 1A shows the uppermost layer constituting a part of the TEG main body other than the electrode pad of the TEG element at the cross-sectional location on the scribe region 103 provided around the semiconductor device region 102 on the semiconductor substrate 101. The case where the metal wiring layer 116 exists and the other TEG main-body part does not exist is illustrated.
[0014]
The semiconductor device region 102 is in contact with the source / drain 105, the gate insulating film 106, the gate electrode 107, the first interlayer insulating film 108, and the source / drain 105 formed on the semiconductor substrate 101 by a known manufacturing method. The contact hole 109, the first metal wiring layer 110, the second interlayer insulating film 111, the via hole 112 that makes contact between the first metal wiring layer 110 and the second metal wiring layer 113, and the second metal wiring layer 113 are formed. .
[0015]
The scribe region 103 is also formed by a conventional manufacturing method until the passivation film 114 is formed. That is, the unnecessary gate electrode 107 and the first metal wiring layer 110 in the scribe region 103 are removed by performing etching simultaneously at the time of patterning, and the first interlayer insulating film 108 and the second interlayer insulating film 111 are removed over the entire surface. To leave. When the bonding pad 115 is formed after depositing the passivation film 114, the passivation film 114 on the uppermost metal wiring 116 is protected by the resist pattern from being etched during etching, and the passivation film 114 is protected from the uppermost metal wiring. 116 is left to cover. In this way, variations in resistance of the uppermost metal wiring 116 due to the influence of etching when etching the passivation film 114 can be suppressed. In some experiments, when all of the wiring pattern is covered, even if the passivation film on a part of the pattern is removed, the standard deviation of the variation may be reduced by an order of magnitude. Expected enough.
[0016]
FIG. 1B illustrates a case where the gate electrode 107 and the first metal wiring layer 110 that constitute a part of the TEG main body other than the electrode pad of the TEG element 117 are present at the cross-sectional location on the scribe region 103. is doing. As shown in FIG. 1B, the passivation film 114 is left so as to cover the TEG body, and the other passivation film 114 is etched away.
[0017]
FIG. 1C illustrates a case where an alignment mark 118 formed by the uppermost metal wiring layer (second metal wiring layer 113) is present at the cross-sectional location on the scribe region 103. FIG. 1D illustrates a case where an alignment mark 119 by the first metal wiring layer 110 is present at the cross-sectional location on the scribe region 103.
[0018]
In FIG. 1D, the first metal wiring layer 110 is illustrated, but the same applies to the alignment mark formed by the gate electrode layer 107. 1 (b) to 1 (d), the same portions and the same portions as those in FIG. 1 (a) are denoted by the same reference numerals, and the description of the portions overlapping with FIG.
[0019]
In FIG. 1C, the passivation film 114 on the alignment mark 118 by the uppermost metal wiring layer is removed, but the alignment mark is usually formed in a pattern of about 4 to 70 μm. Since the film is usually less than about 1 μm thick, it is possible to prevent peeling due to side etching of the interlayer insulating film layer under the alignment mark by adjusting the etching conditions of the passivation film.
[0020]
FIG. 2 is a plan view of a scribe region of a semiconductor device formed according to the present invention. In FIG. 2, the same reference numerals are given to the same portions and the same portions as those in FIG. As shown in FIG. 2, it can be seen that the passivation film 114 exists so as to cover the TEG body portion 122 other than the electrode pad 121 of the TEG element 117.
[0021]
In FIG. 2, the metal wiring connecting the left TEG body 122 and the electrode pad 121 uses the uppermost metal wiring layer 116, whereas the metal wiring connecting the right TEG body 122 and the electrode pad 121 is used. The wiring 120 uses the first metal wiring layer 110. In the TEG main body 122 on the right side, since the metal wiring 120 connecting the electrode pad 121 is not the uppermost metal wiring 116, the passivation film 114 does not completely cover the first metal wiring layer 110. Since there is no possibility that the first metal wiring layer 110 is etched when the film 114 is etched, the wiring resistance is not affected.
[0022]
As can be seen from FIG. 2, the area of the passivation film 114 in the scribe region 103 can be reduced to the minimum necessary, and the burden on the diamond blade during dicing can be reduced.
[0023]
In the above embodiment, the first and second interlayer insulating films 108 and 111 are silicon oxide films, and the passivation film 114 is a moisture-resistant silicon nitride film. Regarding the hardness, since the silicon nitride film is larger than the silicon oxide film, the burden on the diamond blade or the like can be reduced by reducing the area of the passivation film 114 on the scribe region 103 to the maximum.
[0024]
Moreover, the structure of the TEG element illustrated in the above embodiment, the pattern, and the manufacturing process used for manufacturing the semiconductor device are examples, and the present invention is not limited thereto.
[0025]
【The invention's effect】
As described above, in the method for manufacturing a semiconductor device according to the present invention, since the passivation film is left only on the TEG elements arranged in the scribe region, the following effects can be obtained.
[0026]
First, in a plurality of TEG elements arranged in the scribe region, since the passivation film remains on the TEG element, the resistance variation of the uppermost metal wiring is prevented without being affected by the etching of the passivation film. Deterioration or change in the characteristics of the element can be prevented.
[0027]
Next, in the dicing of the scribe region, the passivation film remains in the scribe region only in the necessary region on the TEG element, so the area of the passivation film in the scribe region is reduced and the burden on the diamond blade and the like is reduced. can do.
[Brief description of the drawings]
1A and 1B are cross-sectional views showing an embodiment of a semiconductor device manufactured by a method for manufacturing a semiconductor device according to the present invention, in which FIG. 1A shows a case where an uppermost metal layer wiring is present in a scribe region; Shows the case where the TEG element is in the scribe region, (c) shows the alignment mark of the uppermost metal wiring layer in the scribe region, and (d) shows the case where the alignment mark of the first metal layer is in the scribe region. .
FIG. 2 is a plan view showing an embodiment of a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the present invention.
3A and 3B are cross-sectional views showing an example of a scribe region of a semiconductor device manufactured by a conventional method for manufacturing a semiconductor device (conventional technology 1), where FIG. 3A is a state before dicing, and FIG. 3B is a state after dicing. Indicates the state.
4A and 4B are a cross-sectional view and a plan view showing an example of a scribe region of a semiconductor device manufactured by a conventional method for manufacturing a semiconductor device (conventional technology 2).
FIG. 5 is a cross-sectional view showing an example of a scribe region of a semiconductor device manufactured by a conventional semiconductor device manufacturing method (prior art 3).
[Explanation of symbols]
101, 201: semiconductor substrate 102, 202: semiconductor device region 103, 203: scribe region 104, 204: element isolation region 105, 205: source / drain region 106, 206: gate insulating film 107, 207: gate electrode 108, 208 : First interlayer insulating films 109, 209: contact holes 110, 210 for making contact with the source / drain regions: first metal wiring layers 111, 211: second interlayer insulating films 112, 212: first metal wiring and first holes Via holes 113 and 213 for making contact between two metal wirings: second metal wiring layer (uppermost metal wiring layer)
114, 214: Passivation film 115, 215: Bonding pads 116, 222: Top layer metal wiring (layer)
117, 220: TEG elements 118, 219: Alignment marks 119 on the uppermost metal wiring layer 119: Alignment marks 120 on the first metal wiring layer, 221: Wirings 121, 223 on the first metal wiring layer, electrode pads of the TEG element
122: TEG body 216: gap formed by dicing 217: crack 218: slit groove

Claims (3)

On the scribe region provided around the semiconductor device region on the semiconductor substrate, the TEG body part excluding the electrode pads and the electrode pads electrically connected to the TEG body part are arranged separately in a plane. A method of manufacturing a semiconductor device provided with a TEG element,
In dicing the previous state, the scribe region deposited on passivation - the passivation film so as to cover only the TEG body portion other than the electrode pads of the TEG element provided in the scribe region, the TEG body A method of manufacturing a semiconductor device, wherein the semiconductor device is removed from the scribe region other than the portion.   The method of manufacturing a semiconductor device according to claim 1, wherein the TEG main body includes a metal wiring of an uppermost layer other than the electrode pads.   3. The method of manufacturing a semiconductor device according to claim 1, wherein the interlayer insulating film formed on the semiconductor substrate is a silicon oxide film, and the passivation film is a silicon nitride film.