JP2006041236A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent generation of failures, resulting from connective wiring of a test pad formed in a scribe region. <P>SOLUTION: Two or more semiconductor chip regions are arranged on a wafer, and the scribe regions arranged between individual semiconductor chip regions are carried out, by dicing of the scribe regions so as to make the semiconductor chip regions into individual pieces. In the manufacturing method of a semiconductor device, a testing circuit which connects conductively to a bonding pad formed in the semiconductor chip region is formed in the scribe region. Connection wiring for connecting a bonding pad and a testing circuit connects wiring which extends from the bonding pad to the vicinity of the boundary of the semiconductor chip region and the scribe region, and wiring which extends from the pattern to the vicinity of the boundary of the semiconductor chip region and the scribe region with a lower layer wiring, which extends going across the boundary of the semiconductor chip region and the scribe region. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a technique effective when applied to dicing of a semiconductor chip.

  In a semiconductor device, patterns are collectively formed in a plurality of semiconductor chip regions of a wafer using single crystal silicon or the like, and each semiconductor chip region is cut and diced to separate individual semiconductor chips, thus For example, die bonding and wire bonding that are fixed to a lead frame are performed on each separated semiconductor chip, and further resin sealing is performed to complete the semiconductor device.

  In this dicing, the back surface of the wafer is attached to an adhesive dicing tape, and the dicing tape is fixed to the cutting table by vacuum suction with the periphery of the dicing tape fixed to a ring-shaped frame. For example, Ni, Cu, etc. A dicing blade made by sintering diamond abrasive grains with a metal powder as a binder is rotated at high speed to cut and remove the scribe areas between the semiconductor chip areas to cut the wafer vertically and horizontally, and to separate the individual semiconductor chip areas. Yes.

  Each semiconductor chip area of the wafer is formed with an integrated circuit in which various elements formed are connected by a wiring layer and a pad which is an external terminal of this integrated circuit. Each semiconductor chip area is surrounded by a scribe area. ing.

  Prior to the dicing, in order to exclude nonstandard semiconductor chips from the mounting process, a probe test is performed to measure the characteristics of the formed circuit. Usually, in a probe test, the tip of a needle-like contact called a probe is brought into contact with a bonding pad connected to a circuit formed in the element formation region of a wafer, and a measurement signal is transmitted between the circuit and the measuring device. Measurements are made by transmitting.

  The contact of the probe may damage the bonding pad, and this damage may affect subsequent processes such as wire bonding. In order to avoid such an influence, a bonding pad is formed larger than a necessary size, and wire bonding is performed to avoid a damaged portion.

  However, as the number of pads required increases with the increase in the size of the circuit to be mounted, it is required to reduce the size of the bonding pads, and it is difficult to form pads larger than the required size. For this reason, a method has been considered in which a test is performed by connecting a bonding pad and a test pad formed in a scribe region, and bringing a probe into contact with the test pad.

  A technique for forming a test circuit such as a test pad or a signal generation circuit in the scribe region as described above is described in, for example, Patent Document 1 below.

Japanese Patent Publication No.46-19012 JP 2002-33360 A

  Both the bonding pad and the test pad are formed by the uppermost metal wiring layer and connected by connection wiring in the same layer. For this reason, since the connection wiring is formed across the semiconductor chip region and the scribe region, it is cut by the dicing blade at the time of dicing. At this time, when the wiring is cut, a force is applied to the end of the cut wiring due to friction with the rotating dicing blade, and the end of the wiring peels off from the surface of the semiconductor chip and protrudes from the surface. As a result, the end of the turned-up wiring may come into contact with the bonding wire, the inner lead or the like, resulting in a short circuit failure.

  Further, during cutting, a small piece of the metal film may be peeled off from the wiring in the scribe region and become a foreign substance, and this foreign substance may adhere to the semiconductor chip, resulting in a defective semiconductor chip and a decrease in yield.

  The subject of this invention is providing the technique which can solve such a subject and can prevent generation | occurrence | production of the defect resulting from a connection wiring. The above and other problems and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
In a semiconductor device in which wiring is connected to a bonding pad formed on a semiconductor chip, the wiring connected to the bonding pad is connected to the end of the semiconductor chip and connected to the wiring. It consists of exposed lower layer wiring.

  Further, in a method of manufacturing a semiconductor device in which a plurality of semiconductor chip regions are disposed on a wafer, and a scribe region disposed between individual semiconductor chip regions is diced to separate the semiconductor chip regions. A test circuit that is electrically connected to the bonding pad formed in the semiconductor chip region is formed in the scribe region, and a connection wiring that connects the bonding pad and the test circuit is connected from the bonding pad to the semiconductor chip region and the scribe region. The wiring extending to the vicinity of the boundary and the wiring extending from the pattern to the vicinity of the boundary between the semiconductor chip region and the scribe region are connected by the lower layer wiring extending beyond the boundary between the semiconductor chip region and the scribe region. When dicing the scribe area, the lower layer wiring is cut and the Not cut extending wiring from loading pad.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
(1) According to the present invention, since the connection between the bonding pad and the test pad is connected by the lower layer wiring at the boundary between the semiconductor chip region and the scribe region, the boundary between the semiconductor chip region and the scribe region is at the maximum. The lower layer wiring that does not form the upper layer metal wiring and crosses the boundary between the semiconductor chip region and the scribe region is connected to the uppermost layer metal wiring by the via hole wiring having a low mechanical connection strength. When a force is applied to the portion, the uppermost connection wiring and the lower layer wiring are separated and removed from the semiconductor chip, so that there is an effect that it is difficult to generate a long foreign object from the connection wiring.
(2) According to the present invention, the effect (1) has an effect of preventing the connection wiring from being turned up.
(3) According to the present invention, due to the effect (2), it is possible to prevent the end of the turned-up wiring from coming into contact with the bonding wire or the inner lead or the like to cause a short circuit failure. is there.
(4) According to the present invention, due to the effect (1), the connection wiring removed from the scribe region is separated into the uppermost connection wiring and the lower layer wiring, so that a long foreign object is generated from the connection wiring. This is advantageous in that it is possible to prevent a short circuit due to adhesion of foreign matter.

  Embodiments of the present invention will be described below. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
FIG. 1 is a partial plan view showing a wafer state of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a partially enlarged longitudinal sectional view taken along line aa in FIG.

  In the semiconductor device of this embodiment, an element is formed in a semiconductor region in which a semiconductor substrate 1 such as single crystal silicon is separated by an isolation insulating film 2. Layers 4 are formed, and the wiring layers 4 of the respective layers are connected to each other by via-hole wirings 5 penetrating the interlayer insulating film 3. Elements formed on the semiconductor substrate 1 are connected by the wiring layer 4 and the via-hole wiring 5, and a predetermined circuit is configured in the semiconductor chip region which is a unit region of the semiconductor chip. In the semiconductor chip region of the present embodiment, a four-layer wiring structure is formed on the main surface of the semiconductor substrate 1 on which elements are formed.

  In the state of the semiconductor wafer, such semiconductor chip regions are arranged vertically and horizontally on the wafer, and scribe regions (hatched in FIG. 1) are arranged between the individual semiconductor chip regions.

  FIG. 3 is a partial plan view showing a state of dicing, and FIG. 4 is a partially enlarged longitudinal sectional view taken along line aa in FIG. When dicing the semiconductor chips into individual pieces, as shown in FIG. 3, the scribe areas are cut and removed by a dicing blade 6 to separate the semiconductor chip areas into individual semiconductor chips.

  In addition, a rectangular annular guard ring 7 is provided on the outer peripheral portion of the semiconductor chip region in order to prevent moisture or ions from entering after assembly, and the guard ring 7 is formed by laminating the wiring layers 4 of the respective layers. Then, the lowermost wiring layer 4 is connected to the contact layer 8 of the semiconductor substrate 1 separated by the isolation insulating film 2.

  A bonding pad 9 serving as an external terminal of the semiconductor chip is disposed inside the guard ring 7, and the bonding pad 9 is formed from the uppermost wiring layer 4, and similarly to the bonding pad, the uppermost wiring layer. Are connected by a connection wiring 11 and a test pad 10 formed in the scribe region.

  In the present embodiment, the connection wiring 11 that connects the bonding pad 9 and the test pad 10 includes the uppermost layer wiring 11 a extending from the bonding pad 9 to the vicinity of the boundary between the semiconductor chip region and the scribe region, and the interlayer insulating film 3. The lower layer wiring 11b connected to the uppermost layer wiring 11a is connected to the uppermost layer wiring 11a by a via hole wiring 5 penetrating through the semiconductor layer. 3 is connected to the uppermost layer wiring 11 c in the scribe region by a via hole wiring 5 penetrating through the wiring 3. The uppermost layer wiring 11c extends from the test pad 10 to the vicinity of the boundary between the semiconductor chip region and the scribe region.

  Since the bonding pad 9 and the test pad 10 are connected by the lower layer wiring 11b at the boundary between the semiconductor chip region and the scribe region, in the present embodiment, the boundary between the semiconductor chip region and the scribe region is at the maximum. The upper metal wiring is not formed.

  Therefore, in the conventional semiconductor device in which the bonding pad and the test pad are made conductive by the uppermost connection wiring 11, the uppermost layer cut by friction with the dicing blade 6 as shown in FIG. A force was applied to the end portion of the connection wiring 11 to cause turning.

  However, in the semiconductor device of the present embodiment, the uppermost layer metal wiring is not formed at the boundary between the semiconductor chip region and the scribe region, and the lower layer wiring 11b that crosses the boundary between the semiconductor chip region and the scribe region is Since the connection wiring 11a is connected by the via hole wiring 5 having a low general connection strength, when the force is applied to the end of the lower layer wiring 11b, the uppermost connection wiring 11c and the lower layer wiring 12b are separated, A long foreign object is less likely to be generated from the connection wiring 11. Further, when a force is applied to the cut lower layer wiring 11b, the lower layer wiring 11b easily falls off and is separated from the semiconductor chip. For this reason, it is possible to prevent a short circuit between the bonding pad 9 and the semiconductor substrate 1 or a short circuit between other parts such as a bonding wire due to adhesion of foreign matter.

  Therefore, in the semiconductor device of this embodiment, the occurrence of turning can be prevented. As a result, the end of the turned-up wiring comes into contact with the bonding wire or the inner lead or the like to cause a short circuit failure. Can be prevented.

  FIG. 6 shows a modification of the above-described embodiment. In the above-described embodiment, the bonding pad 9 and the test pad 10 are formed by using the wiring layer 4 below the uppermost layer as the lower layer wiring 11b. In this example, the lowermost wiring layer 4 is used as the connection wiring 11 that connects the bonding pad 9 and the test pad 10. For this reason, since the lower layer wiring 11b crossing the boundary between the semiconductor chip region and the scribe region by the interlayer insulating film 3 is fixed by the three layers of the interlayer insulating film 3, it is more difficult to separate from the semiconductor chip.

  In the multilayer wiring structure, the material to be used for each layer is determined according to the purpose of use of the wiring. For example, in the present embodiment, polycrystalline silicon is used for the lowermost wiring layer 4 that has a relatively short connection distance and is affected by the subsequent processes, and tungsten is used for the upper wiring layer 4. The upper two layers that require low resistance because of the long connection distance use aluminum or copper.

  The turning of the connection wiring 11c is a material that is easily deformed, that is, a metal having low brittleness and high ductility, and is more likely to occur. In this example, the lower layer wiring 11b of the connection wiring 11 is made less likely to be deformed by the dicing blade 6 by using polycrystalline silicon which is more brittle and lower in ductility than the upper layer copper or aluminum. Therefore, the connection wiring 11 can be prevented from being turned over.

  FIG. 7 shows another modified example of the above-described embodiment. In this example, the n-type diffusion layer 12 formed on the semiconductor substrate 1 is connected to the bonding pad 9 and the test pad 10 in a conductive manner. 11 lower layer wiring. Since the n-type diffusion layer 12 forms a pn junction with the p-type semiconductor substrate 1, a diode is connected to the bonding pad 9 by appropriately selecting the conductivity type of the diffusion layer 12. By using the current-voltage characteristics to function as a protection element against electrostatic breakdown, it is possible to improve the breakdown voltage when testing a semiconductor chip in a wafer state.

  When the diffusion layer 12 is used for the connection wiring 11 and an increase in wiring resistance between the bonding pad 9 and the test pad 10 becomes a problem, for example, as shown by a broken line in FIG. It is possible to ensure conduction with the wiring layer 4. Since the upper wiring layer 4 is cut after dicing, the function of the diode is not affected.

(Embodiment 2)
FIG. 8 is a partial plan view showing a wafer state of a semiconductor device according to another embodiment of the present invention. The semiconductor device of the present embodiment is effective when the uppermost connection wiring 11c extending to the scribe region is relatively long, and the other configuration is the same as that of the above-described embodiment.

  In the present embodiment, the uppermost layer connection wiring 11 c extending to the scribe region is divided into three, and the divided connection wiring 11 c is connected by a plurality of lower layer wirings 11 b via the via hole wiring 5.

  During dicing, a small piece of the metal film may be peeled off from the wiring 4 in the scribe region to form a foreign substance, and this foreign substance may adhere to the semiconductor chip, resulting in a defective semiconductor chip and a decrease in yield. Such foreign matter has an increased effect depending on its size.

  As in the present embodiment, when the uppermost connection wiring 11c extending on the scribe region is divided into a plurality of parts and connected by the via hole wiring 5, the mechanical connection strength of the via hole wiring 5 is low. Since the connection wiring 11c extending long is separated into the divided connection wirings 11c, it is possible to reduce the size of the foreign matter generated by peeling off small pieces of the metal film from the connection wiring 11c in the scribe region during dicing. it can.

  In the example shown in FIG. 9, the signal generation circuit 13 formed in the whole process or a partial process of the device is formed in the scribe region, and various electrical measurements are performed on the signal generation circuit 13 to obtain actual device characteristics. The process management data is collected.

  When such a signal generation circuit 13 is formed, the signal generation circuit 13 and the control signal test pad 10a or the power supply test pad 10b are provided in a narrow scribe region, and a test is performed in order to connect them. The wiring connecting the pads 10a and 10b and the signal generation circuit 13 becomes long. For this reason, since the size of the foreign material generated by peeling off a small piece of the metal film from the wiring in the scribe area during dicing increases, the influence of the foreign material increases.

  In this example, the uppermost layer connection wiring 11 c extending to the scribe region is divided into three, and the divided connection wiring 11 c is connected by a plurality of lower layer wirings 11 b via the via hole wiring 5. Thus, when the uppermost connection wiring 11c extending on the scribe region is divided into a plurality of parts and connected by the via-hole wiring 5, the mechanical connection strength of the via-hole wiring 5 is low, so that the connection wiring 11c extends long. Since the connecting wiring 11c to be separated is divided into the divided connecting wirings 11c, the size of the foreign matter generated by peeling off the small pieces of the metal film from the wiring in the scribe area at the time of dicing can be reduced.

  In the via chain structure, the length of the upper layer connection wiring 11c and the lower layer wiring 11b can be arbitrarily set except for the connection portion. Therefore, when a low resistance is required, a low resistance wiring can be set long. In order to avoid the generation of foreign matter as much as possible, it is conceivable to increase the number of divisions of the connection wiring 11c to shorten the chain pitch.

  Although the invention made by the present inventor has been specifically described based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention. Of course.

It is a fragmentary top view which shows the wafer state of the semiconductor device which is one embodiment of this invention. It is a longitudinal cross-sectional view along the aa line in FIG. It is a fragmentary top view which shows the cutting state of a wafer. It is a longitudinal cross-sectional view along the aa line in FIG. It is a fragmentary top view which shows the state of the dicing of the conventional semiconductor device. It is a longitudinal cross-sectional view which shows the wafer state of the modification of the semiconductor device which is one embodiment of this invention. It is a longitudinal cross-sectional view which shows the wafer state of the other modification of the semiconductor device which is one embodiment of this invention. It is a fragmentary top view which shows the wafer state of the semiconductor device which is other embodiment of this invention. It is a fragmentary top view which shows the wafer state of the modification of the semiconductor device which is other embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Wafer, 2 ... Isolation insulation film, 3 ... Interlayer insulation film, 4 ... Wiring layer, 5 ... Via-hole wiring, 6 ... Dicing blade, 7 ... Guard ring, 8 ... Contact layer, 9 ... Bonding pad, 10 ... Test pad , 11 ... connection wiring, 12 ... diffusion layer, 13 ... signal generation circuit.

Claims (5)

In a semiconductor device in which wiring is connected to a bonding pad formed on a semiconductor chip,
The semiconductor device, wherein the wiring connected to the bonding pad includes a wiring extending to the vicinity of the end of the semiconductor chip and a lower layer wiring connected to the wiring and exposed at the end face of the semiconductor chip. In a semiconductor device manufacturing method in which a plurality of semiconductor chip regions are arranged on a wafer, and a scribe region arranged between individual semiconductor chip regions is diced to separate the semiconductor chip regions.
A test circuit that is electrically connected to the bonding pad formed in the semiconductor chip region is formed in the scribe region, and a connection wiring that connects the bonding pad and the test circuit is connected from the bonding pad to the semiconductor chip region and the scribe region. The wiring extending to the vicinity of the boundary and the wiring extending from the pattern to the vicinity of the boundary between the semiconductor chip region and the scribe region are connected by the lower layer wiring extending beyond the boundary between the semiconductor chip region and the scribe region. ,
A method of manufacturing a semiconductor device, comprising: cutting a lower layer wiring and not cutting a wiring extending from the bonding pad when dicing a scribe region. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the lower layer wiring is any layer of a multilayer wiring. 4. The method of manufacturing a semiconductor device according to claim 2, wherein the test circuit in the scribe region is a test pad. 4. The method of manufacturing a semiconductor device according to claim 2, wherein the test circuit in the scribe region is a signal generation circuit.

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