JP2015185683A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can easily detect a defect in a short time; and provide a manufacturing method of a semiconductor device which can easily detect a defect in a short time.SOLUTION: A semiconductor device 1 comprises: a substrate 2; a first electrode 3 provided to contact a circumference of the substrate 2 in plan view; an insulation layer 4 provided to cover the first electrode 3; a second electrode 5 provided to contact the circumference of the substrate 2 in plan view and to be opposed to the first electrode 3 across the insulation layer 4; a first terminal 7 connected to the first electrode 3; and a second terminal 8 connected to the second electrode 5.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  In general, a semiconductor device is manufactured by forming a plurality of semiconductor devices together on a wafer and then individually cutting them in a dividing process called dicing. After dicing, quality inspection is performed on the obtained individual semiconductor devices (see, for example, Patent Documents 1 and 2).

JP 2012-33760 A JP 2005-277338 A

  In the above-described dicing process, there may be a mechanical defect in which an end portion of the cut semiconductor device is chipped. Further, due to deterioration of the dicing blade, the scribe line is shifted, and as a result of not being able to perform the dicing as set, there may be a defect that the semiconductor device has a shape and size different from the design.

  In general, such a defect is detected by visual inspection or visual inspection. However, such a method is time-consuming and time-consuming, and the subject of the person who performs the inspection is likely to be included in the inspection result and lacks accuracy. In addition, reproducibility is lacking when different persons are inspected.

  Therefore, there has been a demand for a technique that can easily detect a defect in a semiconductor device in a short time.

  The present invention has been made in view of such circumstances, and an object thereof is to provide a semiconductor device capable of easily detecting defects in a short time. It is another object of the present invention to provide a method of manufacturing a semiconductor device that can easily detect defects in a short time.

  In order to solve the above problems, an embodiment of the present invention includes a substrate, a first electrode provided in contact with the periphery of the substrate in a plan view, an insulating layer provided to cover the first electrode, A second electrode provided in contact with the periphery of the substrate in plan view and opposed to the first electrode across the insulating layer; a first terminal connected to the first electrode; and the second electrode And a second terminal connected to the semiconductor device.

  In one embodiment of the present invention, the first electrode and the second electrode may be provided in contact with two sides of the substrate in plan view.

  In one aspect of the present invention, the substrate includes a seal ring that surrounds a region where an internal circuit is provided, and the first electrode and the second electrode are surrounded by the seal ring in a plan view. It is good also as a structure arrange | positioned in the area | region of the outer side of an area | region.

  In one aspect of the present invention, the substrate has a rectangular shape in plan view, the first electrode and the second electrode are provided in contact with two adjacent sides of the substrate in plan view, and the seal ring includes: It is good also as a structure which has the side along the extending direction of the said 1st electrode and the said 2nd electrode in planar view.

  In one embodiment of the present invention, a step of forming a plurality of integrated circuits on a wafer, a step of cutting the wafer along a preset scribe line, and cutting each semiconductor device having the integrated circuit, A step of performing an inspection for each of the semiconductor devices, and the plurality of integrated circuits include an inspection integrated circuit including a capacitor having a stacked structure of a first electrode, an insulating layer, and a second electrode, In the step of cutting, the wafer is cut along the scribe line set to overlap a part of the capacitor portion in a plane, and in the inspection step, the capacitor portion is formed for each of the inspection integrated circuits. A method of manufacturing a semiconductor device that measures a capacitance and determines pass / fail of the separated semiconductor device based on a measured value of the capacitance that changes in accordance with a planar view shape of the first electrode and the second electrode To provide.

  In one aspect of the present invention, in the step of forming the integrated circuit, two inspection integrated circuits are provided adjacent to each other on the wafer, and the scribe line extends across the two inspection integrated circuits. In the step of forming a pair of electrodes sandwiching the insulating layer so as to intersect and separating the pair of electrodes, the pair of electrodes is divided into the first electrode and the second electrode, and the two adjacent to each other with the scribe line interposed therebetween It is good also as a manufacturing method which forms one said capacity | capacitance part.

  In one aspect of the present invention, in the step of forming the integrated circuit, the four test integrated circuits are arranged in a matrix on the wafer, and the four test integrated circuits are arranged across the four test integrated circuits. A pair of electrodes sandwiching the insulating layer is formed so as to intersect the scribe line, and in the step of separating, the pair of electrodes are divided into the first electrode and the second electrode, and set in a matrix direction It is good also as a manufacturing method which forms the four said capacity parts around the intersection of the scribe line.

  In one aspect of the present invention, the step of forming the integrated circuit may be a manufacturing method in which at least one integrated circuit for inspection is formed for each scribe line.

  According to one embodiment of the present invention, a semiconductor device capable of easily detecting defects in a short time can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device can be provided in which defects can be easily detected in a short time.

It is a schematic diagram which shows the semiconductor device of this embodiment. It is explanatory drawing which shows the manufacturing method of a semiconductor device. It is explanatory drawing which shows the manufacturing method of a semiconductor device. It is explanatory drawing explaining the test | inspection process of a semiconductor device. It is a figure which shows the modification of the manufacturing method of a semiconductor device. It is a figure which shows the modification of a semiconductor device. It is a figure which shows another modification of a semiconductor device.

  Hereinafter, the semiconductor device and the method for manufacturing the semiconductor device according to the present embodiment will be described with reference to the drawings. In all the drawings below, the dimensions and ratios of the constituent elements are appropriately changed in order to make the drawings easy to see.

[Semiconductor device]
The semiconductor device of the present embodiment includes a substrate, a first electrode provided in contact with the periphery of the substrate in plan view, an insulating layer provided to cover the first electrode, and a periphery of the substrate in plan view A second electrode provided opposite to the first electrode across the insulating layer, a first terminal connected to the first electrode, and a second terminal connected to the second electrode And.

  FIG. 1 is a schematic diagram showing a semiconductor device 1 of this embodiment. FIG. 1A is a plan view, and FIG. 1B is a cross-sectional view taken along line Ib-Ib shown in FIG.

  As shown in FIG. 1A, the semiconductor device 1 has a rectangular shape in plan view and has an integrated circuit formed on the substrate 2. The corner portion of the semiconductor device 1 has a capacitor portion 10. In the present specification, “plan view” refers to a visual field viewed from above in the normal direction of the substrate 2 toward the bottom.

  In the following description, the entire circuit structure of the semiconductor device 1 is referred to as an “integrated circuit”, and the capacitor 10 is a part of the circuit structure included in the integrated circuit. In addition to the capacitor portion, the integrated circuit includes circuit elements having functions such as arithmetic processing and storage, such as a logic circuit, an analog circuit, and a memory circuit.

  The semiconductor device 1 is provided with a seal ring 20 having a rectangular shape in plan view. In the region surrounded by the seal ring 20 (inner region 20a), the above-described circuit elements of the integrated circuit are formed, and on the outer side of the region surrounded by the seal ring 20 (outer region 20b), the capacitor unit 10 is provided. Is formed.

  The internal region 20a is provided with a plurality of connection terminals 30 arranged in a 3 × 3 matrix in plan view. The semiconductor device 1 is configured to be connected to a package substrate (not shown) by flip chip bonding using a plurality of connection terminals 30.

  In the external region 20b, the capacitor 10 is provided in contact with the side of the semiconductor device 1 that is rectangular in plan view. Reference numeral 5 denotes a second electrode (described later) constituting the capacitor unit 10. In FIG. 1A, the capacitor 10 (second electrode 5) is provided in the vicinity of the corner 1 c of the semiconductor device 1 so as to contact the side 1 a and the side 1 b that are continuous with the corner 1 c interposed therebetween.

  As illustrated in FIG. 1B, the semiconductor device 1 includes a substrate 2, a first electrode 3, an insulating layer 4, a second electrode 5, a first terminal 7, and a second terminal 8.

  The substrate 2 is made of silicon, and an integrated circuit is formed on one surface.

  The first electrode 3 is made of aluminum or copper and is provided on one surface of the substrate 2. The first electrode 3 is provided on one surface of the substrate 2 and is connected to a wiring 31 extending from the external region 20b to the internal region 20a. The first electrode 3 and the wiring 31 may be formed at the same time, or may be formed individually.

The insulating layer 4 covers the first electrode 3 and is provided on the entire surface on the one surface side of the substrate 2. The insulating layer 4 is made of, for example, silicon oxide (SiO ₂ ) or BPSG (Boron Phosphor Silicate Glass) containing boron (B) or phosphorus (P) in addition to SiO ₂ . Such an insulating layer 4 can be formed, for example, by forming a film on the substrate 2 using a generally known CVD method.

  The insulating layer 4 may be a single layer, but normally, since the integrated circuit formed on the substrate 2 has a multilayer laminated structure, the insulating layer 4 also has a multilayer laminated structure. In the figure, the insulating layer 4 is shown as a stack of layers 4a, 4b and 4c.

  The second electrode 5 is made of aluminum or copper and is provided on one surface of the insulating layer 4. The second electrode 5 is provided on one surface of the insulating layer 4 and is connected to the wiring 51 extending from the external region 20b to the internal region 20a. The second electrode 5 and the wiring 51 may be formed at the same time, or may be formed individually. The second electrode 5 is insulated from the first electrode 3.

  The first electrode 3, the insulating layer 4, and the second electrode 5 as described above form a capacitor portion 10. The first electrode 3 and the second electrode 5 have the same shape, and the second electrode 5 is provided to face the first electrode 3 with the insulating layer 4 interposed therebetween.

  As shown to Fig.1 (a), the shape of the 2nd electrode 5 of this embodiment has a trapezoid in planar view. The first electrode 3 (not shown) in FIG. 1A has the same shape as the second electrode 5. The second electrode 5 is provided so that the two oblique sides are in contact with the sides 1 a and 1 b of the semiconductor device 1. The first electrode 3 (not shown) has the same arrangement as the second electrode 5.

  The insulating film 6 is provided on the entire surface of the insulating layer 4 so as to cover the second electrode 5. As a material for forming the insulating film 6, the same material as that of the insulating layer 4 described above can be used. Alternatively, an insulating resin material such as an epoxy resin, an acrylic resin, or a polyimide resin may be used.

  The first terminal 7 and the second terminal 8 are made of aluminum or copper and are provided on the surface of the insulating film 6. The first terminal 7 is connected to the wiring 31 through the via 71 in the through hole 47 formed in the insulating layer 4, and is connected to the first electrode 3 through the wiring 31. The second terminal 8 is connected to the wiring 51 through the via 81 in the through hole 48 formed in the insulating layer 4, and is connected to the second electrode 5 through the wiring 51.

  With such a configuration, it is possible to measure the capacitance of the capacitance unit 10 from the first terminal 7 and the second terminal 8.

  Further, the capacitor unit 10 may have an electrode disposed between the first electrode 3 and the second electrode 5. In the semiconductor device 1 of this embodiment, as shown in FIG. 1B, electrodes 91 and 92 are arranged between the first electrode 3 and the second electrode 5. The electrode 91 is sandwiched between the layer 4a and the layer 4b, and the electrode 92 is sandwiched between the layer 4b and the layer 4c. The capacitance value of the capacitance unit 10 can be controlled by the presence or absence of the electrodes 91 and 92.

The seal ring 20 is formed by connecting a conductive pattern 20x provided inside a through hole 41b penetrating the layer 4b and a conductive pattern 20y provided inside a through hole 41c penetrating the layer 4c. ing. The seal ring 20 is made of aluminum or copper. The wiring 51 connected to the second electrode 5 is connected to the seal ring 20 on the surface of the insulating layer 4.
The semiconductor device 1 of this embodiment has the above configuration.

[Method for Manufacturing Semiconductor Device]
The method of manufacturing a semiconductor device according to the present embodiment includes a step of forming a plurality of integrated circuits on a wafer, a step of cutting the wafer along a preset scribe line, and cutting each semiconductor device having the integrated circuit. And a step of inspecting each semiconductor device, wherein the plurality of integrated circuits include an inspection integrated circuit including a capacitor having a stacked structure of a first electrode, an insulating layer, and a second electrode. And in the step of cutting, the wafer is cut along the scribe line set so as to overlap with a part of the capacitor portion in a plane, and in the step of performing the inspection, the capacitance is determined for each of the inspection integrated circuits. And measuring the capacity of the semiconductor device based on the measured value of the capacitance that changes corresponding to the shape of the first electrode and the second electrode in plan view. .

  2 to 4 are explanatory views showing a method for manufacturing the semiconductor device 1. Hereinafter, a method for manufacturing the semiconductor device 1 will be described with reference to the drawings.

(Process for forming an integrated circuit)
First, as shown in FIG. 2A, a plurality of integrated circuits are formed on a silicon wafer (wafer W). In FIG. 2A, a plurality of unit structures 100 of a semiconductor device including a seal ring 20 and a plurality of connection terminals 30 provided in an inner region 20a of the seal ring 20 are arranged in a matrix. It shows as being.

  Although an integrated circuit is not shown in FIG. 2A, as described above, circuit elements constituting the integrated circuit are formed in the inner region 20a of the seal ring 20. That is, an integrated circuit is formed on the wafer W by appropriately forming an insulating layer having a laminated structure, wirings provided between the insulating layers, and the like. The unit structure 100 includes a seal ring 20, a plurality of connection terminals 30, and an unillustrated integrated circuit.

  Further, as shown in the enlarged view of FIG. 2B, a rectangular annular second annular electrode 5X in a plan view is provided in a region between the four seal rings 20 adjacent in a 2 × 2 matrix. ing. Further, a first annular electrode having the same shape as the second annular electrode 5X is provided so as to overlap the second annular electrode 5X in plan view. The first annular electrode and the second annular electrode 5X sandwich an insulating layer (not shown). The first annular electrode and the second annular electrode 5X correspond to “a pair of electrodes” in the present invention.

  The second annular electrode 5 </ b> X is connected to the four seal rings 20 arranged so as to surround the periphery via wirings 51. The wiring 51 is connected to the second terminal 8 provided in each seal ring 20. Of the plurality of unit structures 100 formed on the wafer W, the integrated circuit included in the unit structure 100 in which the first annular electrode and the second annular electrode 5X are connected corresponds to the “inspection integrated circuit” in the present invention. To do. A semiconductor device having an inspection integrated circuit corresponds to the semiconductor device 1 described above.

(Process to separate each semiconductor device)
Next, as shown in FIG. 3A, the wafer W is cut along a scribe line SL set along a region between the plurality of unit structures 100 (a region between the seal rings 20). By cutting the wafer W, a plurality of integrated circuits are cut into integrated circuits (dicing). Thereby, a plurality of semiconductor devices are formed.

  At this time, as shown in the enlarged view of FIG. 3B, the scribe line SL is set so as to overlap with a part of the first annular electrode and the second annular electrode 5X. Thus, the second annular electrode 5X is divided along the scribe line SL, and four second electrodes 5 are formed. Similarly, the first annular electrode is also divided into four to form four first electrodes. As a result, four capacitor portions 10 are formed around the intersection of the scribe lines SL. Of the integrated circuits that divide the wafer W along the scribe line SL, the integrated circuit having the capacitor 10 corresponds to the “inspection integrated circuit” in the present invention.

(Inspection process for each semiconductor device)
Next, a quality inspection is performed on the separated semiconductor device. The quality inspection is performed by measuring the capacity of the capacity unit 10. The capacity of the capacity unit 10 can be easily measured via the first terminal 7 and the second terminal 8 shown in FIG.

  Here, when the semiconductor device is manufactured by cutting the wafer W, there may be a mechanical defect in which the end of the cut semiconductor device is chipped. Further, due to the deterioration of the dicing blade or the like, the scribe line SL is displaced, and as a result of the failure to perform the dicing as set, there may be a defect that the semiconductor device has a shape and size different from the design.

  In the semiconductor device manufacturing method of the present embodiment, the defect can be easily detected by measuring the capacitance of the capacitor 10 in the semiconductor device having the “inspection integrated circuit”.

  FIG. 4 is an explanatory diagram for explaining the inspection process of the semiconductor device. FIG. 4A shows a non-defective semiconductor device 1. FIG. 4B shows the semiconductor device 1x cut smaller than the design due to the displacement of the scribe line. FIG. 4C shows a semiconductor device 1y having a chipped end.

  First, in the non-defective semiconductor device 1 as shown in FIG. 4A, the capacitance portion 10 having a predetermined shape in plan view is formed. Therefore, the measured value of the capacitance of the capacitance portion 10 is the first electrode 3. And a value close to a design value based on the shape of the second electrode 5, the layer thickness of the insulating layer 4 (see FIG. 1), the dielectric constant, and the like.

  On the other hand, as shown in FIG. 4B, when the scribe line is cut to a size smaller than the design, the second electrode 5 of the capacitor portion 10 is also cut at the end portion and does not have a plan view shape as designed. There is.

  In addition, as shown in FIG. 4C, in the semiconductor device 1y lacking the end portion, the second electrode 5 of the capacitor portion 10 may also lack the end portion and may not have a plan view shape as designed.

  For this reason, in the semiconductor devices 1x and 1y, when the capacitance of the capacitance unit 10 is measured, a value greatly deviating from the design value is shown.

As described above, in the semiconductor device having the capacitor portion 10, when the scribe line is displaced or the end portion of the semiconductor device is chipped, the electrodes (first electrode and second electrode) constituting the capacitor portion 10 are viewed in plan. A shape changes and the measured value of the capacity | capacitance of the capacity | capacitance part 10 changes. For this reason, an allowable range is set in advance for the capacitance value of the capacitance unit 10, and it is easy to determine whether a measured value is included in the allowable range and a non-acceptable range is determined as a defective product. The quality of the device can be determined.
The manufacturing method of the semiconductor device of this embodiment is as described above.

  According to the semiconductor device 1 configured as described above, it is possible to provide a semiconductor device that can easily detect defects in a short time.

  Further, according to the method for manufacturing a semiconductor device having the above-described configuration, it is possible to provide a method for manufacturing a semiconductor device capable of easily detecting defects in a short time.

  In the semiconductor device 1 of the present embodiment, the capacitor 10 is provided at the corner in plan view, but the present invention is not limited to this. The capacity | capacitance part 10 changes a capacity | capacitance by a planar view shape changing with the shape change of the periphery of a board | substrate. Then, the quality of the semiconductor device is determined based on the change in the capacitance. For this reason, the capacitor 10 is preferably provided in contact with the periphery of the substrate (the contour line in the plan view shape of the substrate). The capacitor 10 does not necessarily need to touch two sides, and may touch only one side.

  In addition, the semiconductor device 1 of the present embodiment has the seal ring 20, but may be configured without the seal ring 20.

  Further, in the semiconductor device 1 of the present embodiment, the second electrode 5 is connected to the seal ring 20. However, the present invention is not limited to this, and the first electrode 3 is connected to the seal ring 20 and the second electrode is connected. 5 may not be connected to the seal ring 20. Further, the first electrode 3 and the second electrode 5 may not be connected to the seal ring 20.

  Moreover, although the semiconductor device 1 of the present embodiment includes only one capacitor unit 10, it may include a plurality of capacitors. For example, in a semiconductor device having a rectangular shape in plan view, assuming that capacitor portions are provided diagonally and each capacitor portion is in contact with adjacent sides, the shape change of all sides can be detected by the two capacitor portions. It becomes possible.

  In the semiconductor device manufacturing method of this embodiment, the first annular electrode 5X and the second annular electrode 5X that are rectangular in a plan view are formed in a region between the four seal rings 20 adjacent in a 2 × 2 matrix. However, the first annular electrode and the second annular electrode 5X are divided to form the four capacitor portions. However, the present invention is not limited to this.

  For example, as shown in FIG. 5, two integrated circuits (inspection integrated circuits) are provided adjacent to each other on a wafer, and a pair of electrodes (not shown) sandwiching an insulating layer across the two integrated circuits. After forming the first electrode and the second electrode 5Y), the two capacitor portions may be formed by dividing the pair of electrodes along the scribe line SL.

  Alternatively, the inspection integrated circuits formed on the wafer may be independent from each other.

  Further, the integrated circuit formed on the wafer may be an inspection integrated circuit in which all the integrated circuits have a capacitor portion. In this case, since all the manufactured semiconductor devices are provided with a capacitor portion, electrical defect inspection can be performed on all manufactured semiconductor devices.

  Further, the integrated circuit formed on the wafer may be formed so that at least one inspection integrated circuit corresponds to each scribe line, and the rest may be an integrated circuit having no capacitor. In this case, since the inspection integrated circuit is arranged for each scribe line, the displacement of the scribe line is detected by measuring the capacitance of the capacitor portion of the manufactured semiconductor device (semiconductor device having the inspection integrated circuit). It becomes possible to do.

  The deviation of the scribe line affects all the semiconductor devices cut along the displaced scribe line. Therefore, for a semiconductor device corresponding to a certain scribe line, when it is detected that the capacitance of the capacitor portion is not included in the allowable range, it is estimated that all the semiconductor devices along the corresponding scribe line have defects. Can do. If necessary, an appearance inspection or a visual inspection may be performed on all the semiconductor devices along the displaced scribe lines.

(Modification)
In the semiconductor device 1 according to the present embodiment, the capacitance of the capacitance unit 10 that changes corresponding to the planar shape of the capacitance unit 10 can be measured, and the semiconductor device can be easily inspected based on the measurement value. It has become. Therefore, the planar view shape of the capacitor 10 is not limited to the trapezoidal shape shown in the above embodiment, and various configurations can be employed.

  FIG. 6 is a diagram illustrating a modification of the semiconductor device, and is an enlarged view of the capacitor.

  The capacitor portion included in the semiconductor device may be provided so as to extend to the corner 1c of the substrate as in the capacitor portions 10A to 10C illustrated in FIGS. Although the capacitor portion 10A has a triangular shape in plan view, it may have a polygonal shape like the capacitor portion 10B shown in FIG. 6B, and may have a fan shape like the capacitor portion 10C shown in FIG. May be.

  Moreover, it is good also as having two or more 2nd electrodes (it is 2 in FIG.6 (d) (e)) by planar view like capacitive part 10D, 10E shown to FIG.6 (d) (e). In that case, the widths of the plurality of second electrodes 5D may be the same as in the capacitance unit 10D illustrated in FIG. 6D, and the plurality of second electrodes 5D may be configured as in the capacitance unit 10E illustrated in FIG. The widths of the two electrodes 5E may be different.

  FIG. 7 is a diagram illustrating another modification of the semiconductor device, and is an enlarged view of the capacitor.

  In the semiconductor device 1 </ b> A shown in FIG. 7, the seal ring 20 has a side 21 along the extending direction of the capacitor 10 (the extending direction of the first electrode 3 and the second electrode 5) in plan view. By setting it as such a structure, the internal area | region 20a enclosed by the seal ring 20 can be expanded, and the external area | region 20b can be narrowed. Therefore, it is possible to increase the integration density of the semiconductor device and improve the yield of the semiconductor device manufactured from the wafer.

  The preferred embodiments of the present invention have been described above with reference to the accompanying drawings, but it goes without saying that the present invention is not limited to such examples. Various shapes, combinations, and the like of the constituent members shown in the above-described examples are examples, and various modifications can be made based on design requirements and the like without departing from the gist of the present invention.

  DESCRIPTION OF SYMBOLS 1,1A ... Semiconductor device, 1a, 1b ... Side, 2 ... Substrate, 3 ... 1st electrode, 4 ... Insulating layer, 5, 5D, 5E, 5Y ... 2nd electrode, 7 ... 1st terminal, 8 ... 2nd Terminal, W ... Wafer, 10, 10A, 10B, 10C, 10D, 10E ... Capacitor, 20 ... Seal ring, SL ... Scribe line

Claims (8)

A substrate,
A first electrode provided in contact with the periphery of the substrate in plan view;
An insulating layer provided to cover the first electrode;
A second electrode provided in contact with the periphery of the substrate in plan view and opposed to the first electrode across the insulating layer;
A first terminal connected to the first electrode;
And a second terminal connected to the second electrode.   The semiconductor device according to claim 1, wherein the first electrode and the second electrode are provided in contact with two sides of the substrate in a plan view. A seal ring surrounding the periphery of the area where the internal circuit is provided in the substrate;
The semiconductor device according to claim 1, wherein the first electrode and the second electrode are arranged in a region outside the region surrounded by the seal ring in a plan view. The substrate has a rectangular shape in plan view,
The first electrode and the second electrode are provided in contact with two adjacent sides of the substrate in plan view,
The semiconductor device according to claim 3, wherein the seal ring has sides along the extending direction of the first electrode and the second electrode in a plan view. Forming a plurality of integrated circuits on the wafer;
Cutting the wafer along a preset scribe line, and cutting each semiconductor device having the integrated circuit;
A step of inspecting each semiconductor device,
The plurality of integrated circuits include an inspection integrated circuit including a capacitor having a stacked structure of a first electrode, an insulating layer, and a second electrode
In the step of cutting, the wafer is cut along the scribe line that is set to overlap with a part of the capacitor portion in a plane,
In the step of performing the inspection, the capacitance of the capacitance unit is measured for each of the inspection integrated circuits, and based on the measured value of the capacitance that changes corresponding to the planar view shape of the first electrode and the second electrode. A method for manufacturing a semiconductor device, wherein the semiconductor device is judged to be good or bad. In the step of forming the integrated circuit, the two inspection integrated circuits are provided adjacent to each other on the wafer, and the insulating layer is formed so as to cross the scribe line across the two inspection integrated circuits. Forming a pair of sandwiched electrodes,
6. The manufacturing method of a semiconductor device according to claim 5, wherein in the step of dividing, the pair of electrodes are divided into the first electrode and the second electrode, and the two capacitor portions adjacent to each other with the scribe line interposed therebetween are formed. Method. In the step of forming the integrated circuit, the four test integrated circuits are arranged in a matrix on the wafer, and the four test integrated circuits are crossed with the scribe line so as to cross the scribe line. Forming a pair of electrodes sandwiching an insulating layer;
6. In the step of dividing, the pair of electrodes are divided into the first electrode and the second electrode, and the four capacitor portions are formed around intersections of the scribe lines set in a matrix direction. The manufacturing method of the semiconductor device of description.   8. The method of manufacturing a semiconductor device according to claim 5, wherein in the step of forming the integrated circuit, at least one of the inspection integrated circuits is formed for each scribe line.

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