JP5428002B2 - Check pattern and mounting evaluation device - Google Patents

Description

  The present invention relates to a check pattern for performing mounting evaluation of a semiconductor chip, and more particularly to a check pattern for performing mounting evaluation in a dicing process and an evaluation apparatus thereof.

  In order to reduce the decrease in yield, it is necessary to confirm and evaluate the occurrence of damage to the wafer in the processes after the wafer test. However, in the processes after the wafer test, a standard method for confirming and evaluating the occurrence of damage to the wafer has not been established.

  In particular, a low dielectric constant (hereinafter referred to as “Low-k”) material that is generally used to realize high-speed operation of next-generation semiconductor devices is structurally weak in mechanical strength, and has a film during mounting. It is easy to cause the disconnection of the wiring accompanying a fracture | rupture or peeling, and has a big subject in quality improvement.

Therefore, a technique disclosed in Patent Document 1 is disclosed as a technique related to the above problem. The technique shown in Patent Document 1 is a technique related to a semiconductor chip and a test method thereof that can identify a damaged part of the guard ring and a damaged part thereof. A circuit element formed on the surface, a wiring layer including wiring electrically connected to the circuit element, an intermediate insulating layer provided between the wiring layer and the semiconductor substrate, and surrounding the circuit element A guard ring provided in the intermediate insulating layer, and a capacitor electrode provided between the guard ring and the circuit element or in the intermediate insulating layer outside the guard ring and spaced apart from each other; And a pad electrically connected to each.
Also, a technique disclosed in Patent Document 2 is disclosed as an inspection technique in which an evaluation element is arranged outside the guard ring.
JP 2005-228854 A JP 2006-339549 A

However, although the technique shown in Patent Document 1 can specify damage to the guard ring and the damaged portion thereof, it cannot specify the damaged portion outside the guard ring. Damage to the outside of the guard ring may lead to damage that may affect the circuit in the future even if there is no problem during testing, and it cannot be completely ignored, resulting in a lack of reliability of the semiconductor chip. Connected. Therefore, the technique disclosed in Patent Document 1 has a problem that the test becomes insufficient.
Further, the technique disclosed in Patent Document 1 is unsuitable for verifying the depth when damage such as a crack occurs in a semiconductor chip.
The technique shown in Patent Document 2 is one in which an evaluation element is arranged outside the guard ring. However, like the technique shown in Patent Document 1, it is unsuitable for verifying the depth of damage such as cracks.

  Accordingly, the present invention has been made to solve the above-described problems, and a check pattern and mounting evaluation that can easily and reliably detect damage occurring outside the guard ring and perform mounting evaluation of a semiconductor chip. An object is to provide an apparatus.

(1. Evaluation of outer area of guard ring)
The check pattern disclosed in the present application includes a plurality of electric circuits connected in parallel or arranged in parallel from a scribe area for dicing to an outer area of the guard ring at a predetermined interval from the inside of the semiconductor chip. A detection unit and an output unit connected to the detection unit and disposed outside the guard ring are provided.

  As described above, the check pattern disclosed in the present application includes a detection unit in which a plurality of electric circuits are connected in parallel or arranged in parallel at a predetermined interval toward the inside of the semiconductor chip in the outer region of the guard ring. Therefore, when a crack such as a crack enters, the characteristics of the electric circuit can be changed by disconnection of the electric circuit. In other words, the damage state can be analyzed by an electrical change rather than a mechanical effect, and the processing can be performed simply by omitting the labor of the analysis work.

  In addition, since a plurality of electric circuits are connected in parallel or arranged in parallel at a predetermined interval, it is possible to detect how far the damage of the semiconductor chip has spread inside the chip and analyze the degree of damage. There is an effect that can be done.

  Furthermore, since the output unit connected to the detection unit and disposed outside the guard ring is provided, it is possible to extract and analyze information regarding electrical changes caused by damage to the semiconductor chip.

  Furthermore, even damage that has no effect during testing can be analyzed for damage outside the guard ring that could affect circuit operation in the future, leading to the development of highly reliable semiconductor chips. There is an effect that can be done.

(2. Electric circuit is configured between layers)
In the check pattern disclosed in the present application, the semiconductor chip has a laminated structure, and the electric circuit is configured between the layers of the laminated layer.
Thus, when the semiconductor chip has a laminated structure, the check pattern disclosed in the present application configures the electric circuit between the respective layers of the laminated layer, thereby increasing the degree of freedom of the layout of the electric circuit, There is an effect that it is possible to analyze in detail the damage of the semiconductor chip.

(3. Configure an electric circuit for each layer)
In the check pattern disclosed in the present application, the semiconductor chip has a laminated structure, and the electric circuit is configured for each layer of the laminated layer.
As described above, when the semiconductor chip has a laminated structure, the check pattern disclosed in the present application configures the electric circuit for each layer of the laminated layer. For example, the mechanical strength differs for each layer. In such a case, it becomes possible to analyze the damage for each layer, and it is possible to analyze the damage of the semiconductor chip in detail.

(4. Arrangement of output part)
The check pattern disclosed in the present application is arranged in the guard ring, and an output pad connected to an integrated circuit of a semiconductor chip and an output part arranged outside the guard ring are arranged adjacent to each other at a predetermined interval. To do.

  As described above, the check pattern disclosed in the present application includes an output pad disposed in the guard ring and connected to the integrated circuit of the semiconductor chip, and an output portion disposed outside the guard ring. Because they are arranged adjacent to each other at intervals, when testing with a probe, integrated circuit tests using output pads and damage analysis using outputs can be performed simultaneously, dramatically increasing processing efficiency. There is an effect that can be.

(5. low-k material)
In the check pattern disclosed in the present application, the electric circuit is formed on an insulating film of a low-k material.
As described above, the check pattern disclosed in the present application is a detailed analysis of a material that is mechanically brittle and susceptible to damage, such as a low-k material, because the electric circuit is formed on an insulating film of a low-k material. As a result, the semiconductor mounting evaluation can be performed accurately.
The low-k material is a material having a dielectric constant equal to or lower than that of SiO ₂ that has been mainly used as an interlayer insulating material.

(6. Arranged around the guard ring)
The check pattern disclosed in the present application is arranged such that the electric circuit goes around the outside of the guard ring.
Thus, since the check pattern disclosed in the present application is arranged so that the electric circuit circulates outside the guard ring, it is possible to identify the damaged portion of the semiconductor chip by analyzing the electric circuit characteristics. There is an effect that can be done.

  Further, since the electric circuit is circulated, there is an effect that the damage can be reliably detected and confirmed regardless of where the semiconductor chip is damaged by dicing.

(7. Mounting evaluation device)
The mounting evaluation apparatus disclosed in the present application includes a damage detection unit that detects a state of damage due to the dicing based on an output value of the check pattern as compared with a preset circuit characteristic value.
As described above, the mounting evaluation device disclosed in the present application is based on the output value of the check pattern, and compared with a preset circuit characteristic value, the state of damage caused by the dicing (for example, the depth of damage, the damage location, etc.) ) Is detected, it is possible to accurately perform mounting evaluation of the semiconductor chip when the semiconductor chip is damaged or the like.

  So far, the present invention has been shown as a check pattern and apparatus, but the present invention can also be regarded as a method as will be apparent to those skilled in the art. That is, it is possible to apply to the method any combination of the check pattern and the mounting evaluation apparatus disclosed in the present application.

Embodiments of the present invention will be described below. The present invention can be implemented in many different forms. Therefore, the present invention should not be construed based only on the description of the present embodiment. Also, the same reference numerals are given to the same elements throughout the present embodiment.
In the following embodiments, the check pattern and the apparatus will be mainly described. However, as is apparent to those skilled in the art, the present invention can also be implemented as a method.

(First embodiment of the present invention)
A check pattern according to the present embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a diagram illustrating a configuration of a check pattern according to the present embodiment, and FIG. 2 is an enlarged view of the check pattern according to the present embodiment.

  FIG. 1A is a view showing a semiconductor wafer 1, and FIG. 1B is an enlarged view of a semiconductor chip 5 cut by dicing. The semiconductor chips 5a, 5b, 5c, and 5d are adjacently arranged vertically and horizontally with a scribe region 6 for contacting the dicing blade interposed therebetween. Each semiconductor chip 5a, 5b, 5c, 5d cut by dicing is formed with at least an electric circuit 2, an output terminal 3, and a guard ring 4. Although not shown, an integrated circuit is formed inside the guard ring 4.

  In the semiconductor wafer 1, for example, an integrated circuit is formed on a thin slice of an ingot generated by crystallizing a semiconductor material such as silicon. After the formed integrated circuit is inspected, the semiconductor wafer 1 is cut into a plurality of chips by using a dicing blade.

As a material of the semiconductor wafer 1, gallium arsenide, indium phosphorus, gallium nitride, or the like may be used.
Further, the method for cutting the semiconductor wafer 1 may be any method such as a method using a laser or a combination thereof, in addition to the cutting using a dicing blade.

  Furthermore, in the check pattern according to the present embodiment, a low-k material may be used as a material for a layer in which the electric circuit 2 and the integrated circuit are formed. This low-k material is brittle in structure and mechanically fragile, and damage such as film breakage or peeling may occur during mounting, which may degrade the quality of the product. There is a demand for a technology that improves the above.

  The electric circuit 2 has a configuration in which a plurality of capacitors are connected in parallel as shown in the figure, and is parallel to the boundary between the scribe region 6 and the semiconductor chip 5a at the shortest distance from the output terminals 3a and 3b. A horizontal portion 2a is formed so as not to overlap different distances, and a connecting portion 2b that connects one end of the horizontal portion 2a is connected to the output terminal 3a or 3b. Two such comb-like patterns are arranged so as to face each other, and the horizontal portions 2a are juxtaposed to form a capacitor as shown in the figure.

Here, although the horizontal portion 2a is formed in parallel from the boundary between the scribe region 6 and the semiconductor chip 5a, it is not necessarily required to be parallel.
Moreover, although the horizontal part 2a is formed in the straight line, it is not necessarily a straight line and can be variously formed like a curve or a wavy line.

Furthermore, the material of the horizontal portion 2a and the connecting portion 2b is preferably a highly conductive material, more preferably copper.
The guard ring 4 is formed inside the output terminals 3a and 3b in order to connect the output terminals 3a and 3b and the electric circuit 2. The other output terminals 3 are formed inside the guard ring 4 so as to be connected to an internal integrated circuit.

  FIG. 2 shows an enlarged view of the electric circuit 2 and the output terminals 3a and 3b. FIG. 2A shows a normal state, and FIG. 2B shows a state where a crack 8 is generated by dicing and a part of the electric circuit 2 is disconnected. A hatched portion 7 in the figure indicates the electric capacity generated by the capacitor. As shown in FIG. 2 (b), breakage occurs at five points from the side closer to the boundary between the scribe region 6 and the semiconductor chip 5a due to the crack 8. In the case of FIG. 2B, only the thick line portion functions as a conductor after the disconnection, so that the electric capacity indicated by the shaded portion 7 is reduced as compared with the case of FIG. It can be confirmed electrically. In addition, by analyzing the value of the electric capacity, it is possible to specify where the disconnection has occurred, and to specify the depth of the crack.

  As described above, according to the check pattern according to the present embodiment, the detection unit in which a plurality of electric circuits 2 are arranged in parallel at predetermined intervals toward the inner side of the semiconductor chip 5a in the outer region of the guard ring 4 is provided. Therefore, when a crack such as a crack enters, the characteristics of the electric circuit can be changed by disconnection of the electric circuit 2. That is, the damage state can be analyzed by an electrical change rather than mechanically, and the processing can be performed simply by omitting the labor of the analysis work.

  In addition, since a plurality of electric circuits 2 are arranged in parallel at a predetermined interval, it is possible to detect how far the damage of the semiconductor chip 5a has spread inside the chip and analyze the degree of damage.

  In addition, since the output terminal 3 is connected to the detection unit and disposed outside the guard ring 4, it is possible to extract and analyze information on electrical changes caused by damage to the semiconductor chip 5a. It becomes.

  Furthermore, even if the damage is not affected during the test, it is possible to analyze the damage on the outside of the guard ring 4 that may affect the circuit operation in the future, leading to the development of a highly reliable product. it can.

  Furthermore, when the electrical circuit 2 is formed on an insulating film of a low-k material, a detailed analysis of a material that is mechanically brittle and susceptible to damage, such as a low-k material, can be used to evaluate the mounting of a semiconductor. Can be done accurately.

(Second embodiment of the present invention)
A check pattern according to the present embodiment will be described with reference to FIGS. 3 and 4. FIG. 3 is a diagram illustrating a configuration of a check pattern according to the present embodiment, and FIG. 4 is an enlarged view of the check pattern according to the present embodiment.
In addition, description about the same part as the check pattern which concerns on 1st Embodiment is abbreviate | omitted here.

  In FIG. 3, the difference from the check pattern according to the first embodiment is that the electric circuit 2 has a configuration in which a plurality of resistors are connected in parallel. That is, the connecting portion 2b in the electric circuit 2 is connected to both ends of the horizontal portion 2a, and a resistor is provided between the horizontal portions 2a, and each connecting portion 2b has different output terminals 3a and 3b. It is connected to the.

  FIG. 4 shows an enlarged view of the electric circuit 2 and the output terminals 3a and 3b according to the present embodiment. FIG. 4A shows a normal state, and FIG. 4B shows a state where a crack 8 is generated by dicing and a part of the electric circuit 2 is disconnected. As shown in FIG. 4B, the crack 8 causes disconnection at three locations from the side closer to the boundary between the scribe region 6 and the semiconductor chip 5 a. In the case of FIG. 4B, since only the thick line portion functions as a conductor after the disconnection, the resistance value between the output terminals 3a and 3b is reduced as compared with the case of FIG. This can be confirmed electrically. In addition, by analyzing the resistance value, it is possible to specify at which point the disconnection occurs and to specify the depth of the crack.

  Thus, according to the check pattern according to the present embodiment, since the electric circuit 2 is a resistor, a change in the characteristics of the electric circuit 2 is reliably detected, and an accurate analysis is performed on the damage to the semiconductor chip 5a. be able to.

(Third embodiment of the present invention)
A check pattern according to the present embodiment will be described with reference to FIG. FIG. 5 is a top view and a cross-sectional view of the check pattern according to the present embodiment. FIG. 5A is a top view of the check pattern according to this embodiment, FIG. 5B is a cross-sectional view taken along the line AA in FIG. 5A, and FIG. FIG. 6 is a cross-sectional view taken along line BB in FIG.

In addition, description about the same part as the check pattern which concerns on 1st Embodiment or 2nd Embodiment is abbreviate | omitted here.
Here, pattern formation of the electric circuit 2 and the integrated circuit is performed using an insulating film forming method and a metallization method in an integrated circuit manufacturing process. 5B and 5C, an insulating layer 11 (11a, 11b, and 11c) is laminated on the semiconductor wafer 1, and the insulating layer 11a has a pattern including a horizontal portion 2a and a connecting portion 2b. 2A, the insulating layer 11b has a horizontal portion 2c, a pattern 2B composed of a connecting portion 2d, and the insulating layer 11c has an output terminal 3a. That is, the electric circuit 2 is formed between the respective layers.

  The guard ring 4 is formed for each layer, and is formed with an arbitrary thickness based on the pattern and the material of the insulating layer 11. That is, the strong guard layer 4 is formed in the strong layer, and the thick guard ring 4 is formed in the fragile layer.

  When cracking occurs due to dicing, the horizontal portion 2a or 2c is disconnected from the side closer to the boundary between the scribe region 6 and the semiconductor chip 5a as in the case of FIG. By decreasing, it is possible to confirm the occurrence of cracks and to analyze the value of electric capacity to confirm the depth of cracks.

  In the first embodiment and the second embodiment, it is necessary to form the electric circuit 2 so that the horizontal portions do not overlap with each other. However, in this embodiment, the horizontal portions in the same layer are required. What is necessary is just to form so that a part may not overlap, and about the horizontal part (horizontal part 2a and horizontal part 2c) between different layers, you may form so that it may overlap seeing from an upper surface. That is, the degree of freedom of pattern layout increases, and it becomes possible to analyze damage to the semiconductor chip 5a from various viewpoints.

  As described above, according to the check pattern according to the present embodiment, when the semiconductor chip 5a has a laminated structure, the electric circuit 2 is configured between the layers of the laminated layer. It is possible to increase the degree of freedom and analyze the damage of the semiconductor chip 5a in detail.

(Fourth embodiment of the present invention)
A check pattern according to the present embodiment will be described with reference to FIG. FIG. 6 is a perspective view of a check pattern according to the present embodiment. The two layers in the figure are actually stacked and in close contact with each other, but for the sake of clarity, each layer is illustrated separately. As shown in FIG. 6, in the check pattern according to this embodiment, when the semiconductor chip 5a has a laminated structure, the electric circuit 2 is formed for each layer.

In addition, description about the same part as the check pattern which concerns on 1st Embodiment, 2nd Embodiment, or 3rd Embodiment is abbreviate | omitted here.
The plurality of electrical circuits 2 formed for each layer are connected to different output terminals 3 (3a, 3b, 3c, 3d) on the uppermost layer, and the circuit characteristics of the electrical circuit 2 are confirmed and analyzed for each layer. can do. When the semiconductor chip 5 has a laminated structure, the strength and the deflection rate may vary depending on the layer. That is, since there are layers where cracks are likely to occur and layers where cracks are unlikely to occur, the depth of cracks differs for each layer.

  Further, since the pattern of the integrated circuit differs depending on the layer, there may be a layer in which the pattern is disposed just inside the guard ring 4 or a layer in which the pattern is disposed only near the inner center. In such a case, if it is the former, even a slight crack may affect the operation of the circuit, and if it is the latter, it is less likely that a slight crack will affect the operation of the circuit.

  That is, according to the check pattern according to the present embodiment, as shown in FIG. 6, when the semiconductor chip 5a has a laminated structure, the electric circuit 2 is configured for each layer of the laminated layer. It becomes possible to analyze the damage for each, and to analyze the damage of the semiconductor chip in detail. Then, as a result of the analysis, when a layer that is easily damaged is found, for example, the width of the guard ring 4 may be adjusted to ensure durability according to each layer.

(Fifth embodiment of the present invention)
A check pattern according to the present embodiment will be described with reference to FIG. FIG. 7 is a layout diagram of check pattern output terminals and guard rings according to the present embodiment.
In addition, description about the same part as the check pattern which concerns on 1st Embodiment, 2nd Embodiment, 3rd Embodiment, or 4th Embodiment is abbreviate | omitted here.

  As shown in FIG. 7, the output terminal 3 is disposed on the semiconductor chip 5a so as to go around the inside of the chip. The output terminal 3 is connected mainly to an integrated circuit (not shown) formed inside the guard ring, and is connected to the outside via a thin conductive line by wire bonding. However, the output terminal 3 includes dummy terminals (3a, 3b, 3c, 3d) that are not connected to an integrated circuit or the outside. In the check pattern according to the present embodiment, the electric circuit 2 is connected to the dummy terminal. The terminal is formed as an output terminal.

  That is, the output terminal disposed outside the guard ring 4 and the output terminal disposed inside the guard ring 4 are disposed adjacent to each other. By doing so, an operation test of the integrated circuit performed using the output terminal 3 arranged inside the guard ring 4 and connected to the integrated circuit, and arranged outside the guard ring 4 and connected to the electric circuit 2 The electrical analysis of damage performed using the output terminals 3a to 3d can be performed simultaneously using a probe or the like, and the processing efficiency can be improved.

(Sixth embodiment of the present invention)
A check pattern according to the present embodiment will be described with reference to FIG. FIG. 8 is a top view of the check pattern according to the present embodiment. FIG. 8A shows a case where the electric circuit 2 is a capacitor, and FIG. 8B shows a case where the electric circuit 2 is a resistor.
In addition, description about the same part as the check pattern which concerns on 1st Embodiment, 2nd Embodiment, 3rd Embodiment, 4th Embodiment, or 5th Embodiment is abbreviate | omitted here.

  As shown in FIG. 8, the electric circuit 2 is arranged so as to go around the outside of the guard ring 4, and when a crack occurs in the semiconductor chip 5a, almost all cracks are detected and the depth thereof is detected. Can be confirmed. Further, when the capacitor is formed as shown in FIG. 8A, the position where the crack is generated can be specified by calculating the electric capacitance value. That is, in FIG. 8 (a), when the break is caused by the crack A and when the break is caused by the crack B, the difference in the capacitance value occurs even if the crack depth is the same. It becomes possible to do.

As described above, according to the check pattern according to the present embodiment, since the electric circuit 2 is arranged so as to go around the outside of the guard ring 4, the damaged portion of the semiconductor chip can be identified by analyzing the electric capacitance value. Can be identified.
Further, since the electric circuit 2 is circulated, the damage can be detected and confirmed reliably even if the damage is generated from any part of the semiconductor chip 5a by dicing.

(Other embodiments)
A mounting evaluation apparatus according to the present embodiment will be described with reference to FIGS. 9 and 10. FIG. 9 is a functional block diagram of the mounting evaluation apparatus according to the present embodiment, and FIG. 10 is a flowchart showing the operation of the mounting evaluation apparatus according to the present embodiment.

  In addition, here, about the same part as the check pattern according to the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, the fifth embodiment, or the sixth embodiment. Description is omitted.

9, the mounting evaluation device 10 according to the present embodiment includes an electric circuit 2, an output terminal 3, an input unit 15, a detection unit 20, and circuit characteristic information 25, and the result detected by the detection unit 20 is damage information. 30 is output.
Since the electric circuit 2 and the output terminal 3 are the same as those in the first to sixth embodiments, description thereof will be omitted.

The input unit 15 performs processing for receiving information output from the output terminal 3.
Based on the information input to the input unit 15 and the information stored in the circuit characteristic information 25, the detection unit 20 performs a process of detecting damage such as cracks received by the semiconductor chip 5a.

The circuit characteristic information is a database that stores information related to the circuit characteristics of the electric circuit 2. As the information on the circuit characteristics, a theoretical value at the time of circuit design may be registered in advance, or the circuit characteristics may be measured and registered immediately before dicing.
The damage information 30 is information relating to damage detected by the detection unit 20. For example, information indicating the depth of a crack generated in the semiconductor chip 5a, the position of the crack, and the degree of damage.

  Next, the operation of the mounting evaluation apparatus 10 according to the present embodiment will be described based on the flowchart of FIG. First, the circuit information of the electric circuit 2 is registered in the circuit characteristic information 25 (step 1). The circuit characteristic information may be registered by registering theoretical values as described above, or by registering actually measured values. The circuit characteristic information includes various information related to the electric circuit 2 including the capacitance value and resistance value of the capacitor. When the circuit characteristic information is registered, dicing is performed (step 2), and the wafer 1 is cut into a plurality of semiconductor chips.

  Once the semiconductor chip is cut, measurement is performed with a probe to confirm whether or not each semiconductor chip is damaged (step 3) and input to the input unit 15 (step 4). The input measurement data is compared with the circuit characteristic information registered in the circuit characteristic information 25 (step 5), and it is determined whether or not the semiconductor chip is damaged (step 6).

  Note that the presence / absence of damage is determined by a change in impedance such as a capacitance value or a resistance value as described above. By comparing the measurement data with the circuit characteristic information registered in the circuit characteristic information 25, the amount of change in impedance is calculated, and from the amount of change, it is determined whether or not a break has occurred in the electric circuit 2, and the crack The occurrence can be detected.

If the result of determination in step 6 is that there is no damage, the processing ends. If there is damage, the damage state is analyzed (step 7), damage information 30 is output (step 8), and the process is terminated.
In the analysis of the damage state, the state of the electric circuit 2 is obtained from the amount of change in impedance calculated as a result of the comparison in Step 5. Specifically, the location where the disconnection occurs is identified from the amount of change in impedance, and the depth and position of the crack are analyzed.

  Further, a table for associating the mounting evaluation apparatus 10 with various information regarding the semiconductor chip 5 such as information on the depth and position of the crack and the distance between the wiring of the integrated circuit and the guard ring 4, the width of the guard ring, the strength of the insulating layer, etc. May be prepared (not shown), and the semiconductor chip 5 may be comprehensively analyzed based on the table. By doing so, the quality of the semiconductor chip 5 can be improved.

  Thus, according to the mounting evaluation apparatus according to the present embodiment, the state of damage due to dicing is detected based on the output value of the electric circuit 2 in comparison with the preset circuit characteristic value. When there is damage or the like, mounting evaluation of the semiconductor chip 5 can be accurately performed.

  In general, the occurrence of cracks due to dicing is highly likely to occur starting from the test patterns remaining in the four corners and the scribe region of the semiconductor chip 5a. It is desirable to be disposed.

  Although the present invention has been described with the above embodiments, the technical scope of the present invention is not limited to the scope described in the embodiments, and various modifications or improvements can be added to these embodiments. . And embodiment which added such a change or improvement is also contained in the technical scope of the present invention. This is apparent from the claims and the means for solving the problems.

It is a figure which shows the structure of the check pattern which concerns on 1st Embodiment. It is an enlarged view of a check pattern according to the first embodiment. It is a figure which shows the structure of the check pattern which concerns on 2nd Embodiment. It is an enlarged view of a check pattern according to the second embodiment. It is the upper side figure and sectional drawing of the check pattern which concern on 3rd Embodiment. It is a perspective view of a check pattern concerning a 4th embodiment. It is an arrangement drawing of an output terminal and a guard ring of a check pattern concerning a 5th embodiment. It is a top view of the check pattern concerning a 6th embodiment. It is a functional block diagram of the mounting evaluation apparatus which concerns on other embodiment. It is a flowchart which shows operation | movement of the mounting evaluation apparatus which concerns on other embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 2 Electrical circuit 2a Horizontal part 2b Connection part 3 (3a, 3b, 3c, 3d) Output terminal 4 Guard ring 5 (5a, 5b, 5c, 5d) Semiconductor chip 6 Scribe area 7 Diagonal part 8 Crack 10 Mounting evaluation Device 11 (11a, 11b, 11c) Insulating layer 15 Input unit 20 Detection unit 25 Circuit characteristic information 30 Damage information

Claims (7)

A guard ring to prevent mechanical damage that occurs during dicing,
The outer region of the guard ring from the scribe region for performing the dicing, a plurality parallel connection, or arranged in parallel and becomes detector at predetermined intervals an electric circuit towards the inside of the semiconductor chip,
The inside of the semiconductor chip, of the electrode pads plurality arranged along the outer periphery of the semiconductor chip, and a detection result output terminal is an electrode pad that will be connected to the detector,
The guard ring is formed inside an electrode pad that is the detection result output terminal among the plurality of electrode pads arranged, and is formed outside an electrode pad other than the detection result output terminal. And check pattern.
The check pattern according to claim 1,
The check pattern, wherein the semiconductor chip has a laminated structure, and the electric circuit is configured between the layers of the laminated layer. The check pattern according to claim 1,
The check pattern, wherein the semiconductor chip has a laminated structure, and the electric circuit is configured for each layer of the laminated layer. The check pattern according to any one of claims 1 to 3,
Is disposed in the guard in the ring, check pattern, characterized in that the said electrode pad connected to the integrated circuit of the semiconductor chip, is disposed adjacent the electrode pad which is the detection result output terminal at a predetermined interval .

The check pattern according to any one of claims 1 to 4,
The check pattern, wherein the electric circuit is formed on an insulating film of a low-k material. The check pattern according to any one of claims 1 to 5,
The check pattern, wherein the electric circuit is arranged so as to go around the outside of the guard ring.   A damage detection unit that detects a state of damage due to the dicing based on the output value of the check pattern according to any one of claims 1 to 6 in comparison with a preset circuit characteristic value. Mounting evaluation device.

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