JP2012256787A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which inhibits defects at the time of dicing by using a semiconductor substrate having a TEG pattern.SOLUTION: A semiconductor device comprises: a semiconductor substrate singlulated or to be singulated into semiconductor chips 2a by dicing; an inter layer insulation layer formed on the semiconductor substrate; a seal ring 5a provided in the interlayer insulation layer and formed along a periphery of the semiconductor chip 2a; and TEG wiring 7 with one end connected to the seal ring 5a and with another end extending toward an end face of an outer periphery of the semiconductor chip 2a.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  2. Description of the Related Art In recent years, a semiconductor device provided with TEG (Test Element Group) elements having various configurations has been proposed in order to evaluate the characteristics of semiconductor elements in a semiconductor chip at the manufacturing process stage.

  Patent Document 1 (Japanese Patent Application Laid-Open No. 2007-180112) describes the following electronic device. On a semiconductor wafer, a pad electrically connected to the semiconductor chip, a seal ring for protecting the semiconductor chip during dicing, and a circuit characteristic evaluation unit for a scribe line are provided. A part of the seal ring is narrowed. The wiring part in the circuit evaluation part is provided in an empty area by narrowing the seal ring. Thereby, since the wiring part in a circuit evaluation part uses a part of area | region of a seal ring, it is supposed that the width | variety of a scribe line can be narrowed.

  Patent Document 2 (Japanese Patent Laid-Open No. 2010-205889) describes the following semiconductor device. A plurality of electrode terminals are provided on the semiconductor substrate on which the multilayer wiring is formed. A seal ring is provided on the outer periphery of the semiconductor substrate. Further, the semiconductor substrate is provided with an impurity implantation region for electrically connecting the electrode terminal and the seal ring. Thereby, it is said that an abnormality in the peripheral portion of the semiconductor device can be detected by measuring the resistance between two of the plurality of electrode terminals.

JP 2007-180112 A JP 2010-205889 A

  In order to measure the TEG element as described above, an electrode pad may be disposed in the dicing region. The inventor has found that in such a case, the occurrence of chipping and cracks becomes obvious when the metal of the electrode pad adheres to the dicing blade. In particular, if chipping or cracking that breaks the seal ring occurs, moisture absorption from the end of the dicing reaches the inside of the chip and the dielectric constant of the low dielectric constant interlayer insulation layer changes, etc. Could occur.

According to the present invention,
A semiconductor chip separated into semiconductor chips by dicing, or a semiconductor substrate separated into pieces;
An interlayer insulating layer formed on the semiconductor substrate;
A seal ring provided in the interlayer insulating layer and formed along a peripheral edge of the semiconductor chip;
TEG wiring having one end connected to the seal ring and the other end extending toward the outer peripheral end surface of the semiconductor chip;
A semiconductor device is provided.

According to the present invention,
A semiconductor chip separated into semiconductor chips by dicing, or a semiconductor substrate separated into pieces;
An interlayer insulating layer formed on the semiconductor substrate;
A seal ring provided in the interlayer insulating layer and formed along a peripheral edge of the semiconductor chip;
A TEG element provided inside the seal ring in plan view;
TEG wiring having one end connected to the TEG element and the other end not contacting the seal ring and extending toward the outer peripheral end surface of the semiconductor chip beyond the seal ring;
TEG wiring for element connection, one end connected to the TEG element and the other end connected to the seal ring;
A semiconductor device is provided.

According to the present invention,
A step of forming a multilayer wiring including an interlayer insulating layer on a semiconductor substrate separated into a plurality of semiconductor chips,
In the step of forming the multilayer wiring,
In the interlayer insulating layer, forming a seal ring along the peripheral edge of the semiconductor chip,
There is provided a method for manufacturing a semiconductor device, in which one end is connected to the seal ring, and the other end forms a TEG wiring extending toward an outer peripheral end face of the semiconductor chip.

  According to the present invention, the seal ring formed along the periphery of the semiconductor chip is used as a common wiring for the TEG pattern. Thereby, the number of electrode pads required for the TEG pattern can be reduced. Therefore, the amount of metal cutting during dicing is reduced, and the occurrence of chipping and cracks can be suppressed. As described above, when a semiconductor substrate having a TEG pattern is used, a semiconductor device in which defects during dicing are suppressed can be provided.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device which suppressed the defect at the time of dicing using the semiconductor substrate which has a TEG pattern can be provided.

1 is a plan view showing a configuration of a semiconductor wafer according to a first embodiment. 1 is a plan view showing a configuration of a semiconductor device according to a first embodiment. FIG. 3 is an equivalent circuit diagram of a TEG pattern according to the first embodiment. 1 is a cross-sectional view illustrating a configuration of a semiconductor device according to a first embodiment. It is the figure which expanded the TEG element concerning a 1st embodiment. 3 is a flowchart for explaining a method for manufacturing the semiconductor device according to the first embodiment; It is the figure which expanded the TEG element concerning a 2nd embodiment. It is the figure which expanded the TEG element concerning a 3rd embodiment. It is a top view which shows the structure of the semiconductor device which concerns on 4th Embodiment. It is an equivalent circuit diagram of the TEG pattern concerning a 4th embodiment. It is the figure which expanded the TEG element concerning a 4th embodiment. It is a top view which shows the structure of the semiconductor device which concerns on 5th Embodiment. FIG. 9 is an equivalent circuit diagram of a TEG pattern according to a fifth embodiment. It is the figure which expanded the TEG element concerning a 5th embodiment. It is a top view which shows the structure of the semiconductor device which concerns on 6th Embodiment. It is an equivalent circuit diagram of the TEG pattern concerning a 6th embodiment. It is a top view which shows the structure of the semiconductor device which concerns on 7th Embodiment. It is a top view which shows the structure of the semiconductor device which concerns on 8th Embodiment. It is sectional drawing which shows the structure of the semiconductor device which concerns on 8th Embodiment. It is sectional drawing which shows the structure of the semiconductor device which concerns on 9th Embodiment. It is a top view which shows the structure of the semiconductor device which concerns on 10th Embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

(First embodiment)
A semiconductor device 10 according to the first embodiment will be described with reference to FIGS. 1 to 5. The semiconductor device 10 has the following configuration. The semiconductor chip 100 is separated into individual pieces by dicing, or the semiconductor substrate 100 is divided into pieces, the interlayer insulating layer 200 formed on the semiconductor substrate 100, and the interlayer insulating layer 200. A seal ring 5 formed along the peripheral edge, and a TEG wiring 7 having one end connected to the seal ring 5 and the other end extending toward the outer peripheral end face of the semiconductor chip 2 are provided. Details will be described below.

  The semiconductor device 10 described below includes a form before the semiconductor substrate 100 is separated into semiconductor chips 2 by dicing. That is, the semiconductor device 10 in a state where it is not singulated includes a form provided to an assembly manufacturer or the like. On the other hand, the semiconductor device 10 may have a form after the semiconductor substrate 100 is separated into semiconductor chips 2 by dicing.

  First, the semiconductor wafer 1 used for this embodiment is demonstrated using FIG. FIG. 1 is a plan view showing a configuration of a semiconductor wafer 1 according to the first embodiment. As shown in FIG. 1, for example, the semiconductor wafer 1 is divided into a plurality of semiconductor chip 2 regions through a dicing region 3. Here, the semiconductor wafer 1 is, for example, a silicon wafer. The “semiconductor substrate 100” described below includes both the substrate in the state of “semiconductor wafer 1” that is not divided and the substrate in the state of “semiconductor chip 2” after being divided. The “dicing area 3” here refers to an area including a margin in consideration of positioning accuracy of the dicing blade, chipping during dicing, and the like in the cutting area 4 cut by the dicing blade.

  For example, a semiconductor element (not shown) is formed in the semiconductor chip 2, and a multilayer wiring is formed in an interlayer insulating layer 200 described later.

  A seal ring 5 is provided along the peripheral edge of the semiconductor chip 2. The seal ring 5 refers to a wiring groove that penetrates the interlayer insulating layer 200 and is filled with metal. Thereby, when the interlayer insulating layer 200 is a low dielectric constant layer or the like, moisture can be prevented from entering.

  Next, FIG. 2 is a plan view showing the semiconductor device 10 according to the first embodiment. 2A shows an enlarged part of the dicing area in FIG. Moreover, FIG.2 (b) is an enlarged view of (alpha) part in Fig.2 (a).

  2A, the seal ring 5a, the seal ring 5b, the seal ring 5c, and the seal ring 5d are provided along the peripheral edges of the semiconductor chip 2a, the semiconductor chip 2b, the semiconductor chip 2c, and the semiconductor chip 2d, respectively. It has been.

  A dicing region 3 for dividing the semiconductor wafer 2a or the like is disposed in a region sandwiched by the seal ring 5a or the like. In actual dicing, the dicing blade cuts the cutting area 4 in the center portion inside the dicing area 3.

  The TEG pattern 6a in the first embodiment is a region indicated by a one-dot chain line in the drawing. The TEG pattern 6 a includes a TEG wiring 7 having one end connected to the seal ring 5 a and the other end extending toward the outer peripheral end surface of the semiconductor chip 2. Thereby, the seal ring 5a can be used as a common wiring of the TEG pattern 6a.

  The TEG pattern 6a includes electrode pads 9a to 9h for applying a voltage to the TEG pattern 6a in addition to the TEG wiring 7 described above. The electrode pads 9a and the like are disposed in the dicing region 3 outside the seal ring 5a and the like in plan view.

  Further, as shown in FIG. 2B, the electrode pads 9a and the like are provided so as to be in contact with the uppermost layer of the interlayer insulating layer 200 and are connected to the TEG wiring 7a for electrode connection. The “electrode connection TEG wiring 7 a” here refers to the TEG wiring 7 that connects the seal ring 5 a and the like to the electrode pad 9 a and the like in the vicinity of the uppermost layer of the interlayer insulating layer 200. With this electrode pad 9a and the like, measurement can be performed with a stylus in the inspection process.

  Here, the width of the electrode pad 9a is smaller than the width of the dicing blade when the semiconductor substrate 100 is diced. In other words, the electrode pads 9a and the like are preferably arranged in the cutting area 4 of the dicing area 3. Thereby, all the electrode pads 9a are cut at the time of dicing. Therefore, when the semiconductor chip 2 is wire-bonded after dicing, there is no short-circuit between wires.

  Further, the TEG pattern 6a includes TEG elements 8a to 8g. Here, the “TEG element” refers to an element formed based on the same design rule as a semiconductor element (not shown) in the semiconductor chip 2. Thereby, it has the performance equivalent to the semiconductor element provided in the semiconductor chip 2. Therefore, by inspecting the TEG element 8a and the like, it is possible to inspect for defects as performance equivalent to the semiconductor elements in the semiconductor chip 2.

  The TEG element 8a and the like are provided on the semiconductor substrate 100 or the interlayer insulating layer 200, and are connected to the seal ring 5a and the like via the TEG wiring 7b for element connection. The “element connection TEG wiring 7b” herein refers to the TEG wiring 7 that connects the seal ring 5a and the like to the TEG element 8a and the like in the interlayer insulating layer. In the first embodiment, the TEG element 8 a and the like are also provided in the dicing region 3.

  In addition, a third TEG wiring 7c connected to the TEG element 8a and the like, a via (not shown) connected from the third TEG wiring 7c to the electrode pad 9a and the like are provided. Here, the “third TEG wiring 7 c” refers to the TEG wiring 7 that is connected to the TEG element 8 a and connected to the electrode pad 9 a and the like through a via (not shown) in the interlayer insulating layer 200. . Hereinafter, unless otherwise specified, the TEG wiring 7 a for electrode connection, the TEG wiring 7 b for element connection, and the third TEG wiring 7 c are collectively referred to as a TEG wiring 7.

  Here, the seal ring 5a connected to the TEG wiring 7 is, for example, a ground line. Thus, the semiconductor element in the semiconductor chip 2a is not adversely affected in the inspection process of the TEG pattern 6a.

  Next, FIG. 3 is an equivalent circuit diagram of the TEG pattern 6a according to the first embodiment. As shown in FIG. 3, the TEG element 8 a and the like in the TEG pattern 6 a of the first embodiment includes a resistor. Thereby, the resistance value of the portion having the same pattern as the TEG element 8a or the like in the semiconductor chip 2 can be measured.

  Moreover, as shown in FIG. 3, the TEG elements 8a to 8g are connected in parallel, for example. Here, as described above, the seal ring 5a is used as the common wiring connected from the electrode pad 9a to the TEG element 8a and the like.

  For example, the resistance value of the TEG element 8a can be measured by applying a voltage between the electrode pad 9a and the electrode pad 9b and measuring the current value. Similarly, if the resistance value is abnormal after measuring up to the TEG element 8g, it can be considered that the semiconductor chip 2a or 2b near the TEG pattern 6a includes a defective element. Details of the method for manufacturing the semiconductor device 10 including the inspection process will be described later.

  Next, FIG. 4 is a cross-sectional view showing a configuration of the semiconductor device 10 according to the first embodiment. 4 shows a cross-sectional view taken along the line AA ′ in FIG.

  As shown in FIG. 4, the well 120 is formed on the semiconductor substrate 100. Well 120 is, for example, a P-type well into which B (boron) is implanted.

In addition, an element isolation region 160 is formed in the semiconductor substrate 100. The element isolation region 160 has an opening under the seal ring 5a and the like. The element isolation region 160 is, for example, a SiO ₂ film.

  In addition, a diffusion layer 140 into which an impurity having a conductivity opposite to that of the well 120 of the semiconductor substrate 100 is introduced is provided in a portion of the semiconductor substrate 100 that is in contact with the seal ring 5a and the like. Thereby, even if a voltage is applied in the step of inspecting the TEG pattern 6a, no overcurrent flows to the semiconductor chip 2 side.

  Here, the diffusion layer 140 is, for example, an N-type diffusion layer doped with As when the well 120 is a P-type well.

  An interlayer insulating layer 200 is formed on the semiconductor substrate 100. The interlayer insulating layer 200 includes, for example, a first via forming insulating layer 210, a first wiring forming insulating layer 220, a second via forming insulating layer 230, a second wiring forming insulating layer 240, a third via forming insulating layer 250, a third A wiring forming insulating layer 260 and a fourth interlayer insulating layer 270 are provided. Note that the number of the interlayer insulating layers 200 in the present embodiment is not limited, and may be more than or less than the above.

Here, the interlayer insulating layer 200 includes, for example, a low dielectric constant layer having a relative dielectric constant of 3 or less. As a result, the inter-wiring capacitance can be reduced, so that the impedance of the entire semiconductor device 10 can be reduced. As the material for forming the low dielectric constant layer, for _example, SiO 2, SiOC, and the like. Such a low dielectric constant layer may have a porous structure.

  However, for example, a SiN film is used as the fourth interlayer insulating layer 270 close to the electrode pad 9a in the interlayer insulating layer 200. As described above, by using a film having a high mechanical strength, the inside of the semiconductor chip 2a and the like can be protected at the time of a stylus at the time of inspection.

  Among them, the first via formation insulating layer 210 is formed so as to be in contact with the semiconductor substrate 100. In the first via formation insulating layer 210, a first via 310 is formed along the peripheral edge of the semiconductor chip 2a and the like.

  A first wiring formation insulating layer 220 is formed on the first via formation insulating layer 210. In the first wiring formation insulating layer 220, a first wiring 320 having a width wider than that of the first via 310 is formed along the peripheral edge of the semiconductor chip 2a and the like.

  Similarly, the second via forming insulating layer 230, the second wiring forming insulating layer 240, the third via forming insulating layer 250, and the third wiring forming insulating layer 260 are provided along the peripheral portion of the semiconductor chip 2a, etc. Two vias 330, second wirings 340, third vias 350, and third wirings 360 are formed in this order.

  Further, a fourth interlayer insulating layer 270 is formed on the third wiring formation insulating layer 260. The fourth interlayer insulating layer 270 has an opening on the third wiring 360 of the seal ring 5a. In the fourth interlayer insulating layer 270, a fourth via (not shown) may be provided immediately above the third wiring 360.

  A fourth wiring 400 including the electrode pad 9a is formed on the fourth interlayer insulating layer 260 so as to be connected to the third wiring 360. The fourth wiring 400 includes an electrode pad 9a and a TEG wiring 7 for electrode connection. In the illustrated fourth wiring 400, a portion from the portion connected to the third wiring 360 to the electrode pad 9a is a region of the TEG wiring 7 for electrode connection.

  Here, the fourth wiring 400 is, for example, Al. That is, the electrode pad 9a and the TEG wiring 7 for electrode connection are, for example, Al. The electrode pad 9a and the electrode connecting TEG wiring 7 are provided on the uppermost layer (fourth interlayer insulating layer 270) of the interlayer insulating layer 200. Thereby, in a test | inspection process, a stylus can be easily made and contact resistance can be made low.

  A passivation film 500 is formed on the fourth interlayer insulating layer 270 and the fourth wiring 400. An opening is formed in the dicing region 3 in the passivation film 500. Thereby, a part of the electrode pad 9a and the TEG wiring 7 for electrode connection is exposed.

  For example, Cu is used as the first wiring 320, the second wiring 340, and the third wiring 360 described above. On the other hand, as the first via 310, the second via 330, and the third via 350, for example, W or Cu is used.

  Next, the TEG element 8 according to the first embodiment will be described with reference to FIG. FIG. 5 is an enlarged view of the TEG element 8 according to the first embodiment. FIG. 5A is a plan view of the TEG element 8. FIG. 5B is a sectional view taken along line BB ′ in FIG. In the following, “TEG element 8” is used as a general term for the TEG element 8a and the like. The same applies to other embodiments.

  As shown in FIG. 5A, the TEG element 8 includes a resistor as described above. The resistance is, for example, a wiring resistance. The wiring resistance of the first embodiment is formed by bending the first wiring 320 many times in plan view.

  As shown in FIG. 5B, the TEG element 8 is provided as the first wiring 320 in the first wiring formation insulating layer 220. Thereby, the resistance value of a specific wiring layer in the semiconductor chip 2 can be predicted. Here, the resistance value of the first wiring 320 can be predicted.

  Next, a method for manufacturing the semiconductor device 10 according to the first embodiment will be described with reference to FIGS. FIG. 6 is a flowchart showing a method for manufacturing the semiconductor device 10 according to the first embodiment. The manufacturing method of the semiconductor device 10 according to the first embodiment includes a step of forming a multilayer wiring including the interlayer insulating layer 200 on the semiconductor substrate 100 separated into a plurality of semiconductor chips 2. In the step of forming the multilayer wiring, the seal ring 5 is formed in the interlayer insulating layer 200 along the peripheral edge of the semiconductor chip 2, one end is connected to the seal ring 5, and the other end is the outer periphery of the semiconductor chip 2. A TEG wiring 7 extending toward the end face of is formed. Details will be described below.

  As shown in FIG. 6, first, a multilayer wiring including the interlayer insulating layer 200 is formed on the semiconductor substrate 100 separated into a plurality of semiconductor chips 2 (multilayer wiring forming step: S110). The process for forming the multilayer wiring includes the following processes. The following steps are not limited to the order of description, and can be arbitrarily changed depending on the stacking order or the like.

  In the step of forming the multilayer wiring, the seal ring 5 is formed in the interlayer insulating layer 200 along the peripheral edge of the semiconductor chip 2.

  In addition, a TEG wiring 7 a having one end connected to the seal ring 5 and the other end extending toward the outer peripheral end surface of the semiconductor chip 2 is formed.

  Further, in the dicing region 3 outside the seal ring 5 in a plan view, electrode pads 9a and the like connected to the TEG wirings 7 for electrode connection are formed so as to be in contact with the uppermost layer of the interlayer insulating layer 200.

  Further, the TEG element 8 connected to the seal ring 5 is formed on the semiconductor substrate 100 or the interlayer insulating layer 200 via the TEG wiring 7b for element connection.

  The above steps are performed in the step of forming the multilayer wiring described above. In this way, the semiconductor device 10 including the TEG pattern 6a is formed.

  Next, a voltage is applied to the TEG pattern 6a from the electrode pad 9a or the like to inspect the TEG element 8 (inspection step: S120).

  In the first embodiment, as shown in FIG. 1, the resistance value of the TEG element 8a can be measured by applying a voltage to the electrode pads 9a and 9b and measuring the current value. Thereby, the resistance value of the first wiring 320 in the semiconductor chip 2a can be predicted.

  Further, by performing the same measurement as the electrode pads 9a and 9c, the electrode pads 9a and 9d, etc., the resistance value obtained by averaging the TEG elements 8a to 8g can be measured.

  The contents of the inspection may vary depending on the TEG element 8. Different voltages may be applied between the electrode pads 9a and 9b, between 9b and 9c, and the like.

  In the inspection step, when the TEG element 8 is defective (S130 YES), it is determined that a semiconductor element (not shown) in the semiconductor chip 2 (eg, the semiconductor chip 2a) near the TEG pattern 6a is defective. . On the other hand, when there is no defect in the TEG element 8 (NO in S130), it is determined that the semiconductor element in the semiconductor chip 2 near the TEG pattern 6a is not defective and can be shipped.

  Next, after the inspection step (S120), a dicing step is performed in which the dicing region 3 including the electrode pads 9a and the like is diced in the semiconductor substrate 100 to be singulated into a plurality of semiconductor chips 2. At this time, a dicing blade is used for dicing. The semiconductor substrate 100 is divided by scribing a dicing blade over the cutting region 3.

  At this time, if the TEG element 8 is defective in the previous inspection step (S120) (YES in S130), dicing is performed and the semiconductor chip 2 (for example, the semiconductor chip 2a) determined to be defective is removed ( S150).

  On the other hand, if there is no defect in the TEG element 8 in the previous inspection step (S120) (NO in S130), dicing is performed and all the semiconductor chips 2 can be shipped (S140).

  Next, the effect of the first embodiment will be described.

  First, as a comparative example, consider a case where, for example, the seven TEG elements 8a to 8g shown in FIG. 3 each have two electrode pads (not shown). At this time, a total of 14 electrode pads are required. Thus, when many electrode pads are arrange | positioned in the dicing area | region 3, the generation | occurrence | production of a chipping and a crack becomes obvious by the metal of the electrode pad adhering to a dicing blade. In particular, when chipping or cracking that breaks the seal ring occurs, moisture absorption from the end of the dicing reaches the inside of the chip, and the dielectric constant of the low dielectric constant interlayer insulating layer 200 changes over time. Defects may occur.

  On the other hand, according to the first embodiment, as shown in FIG. 1, the seal ring 5 formed along the periphery of the semiconductor chip 2 is used as a common wiring of the TEG pattern 6a. Thereby, the number of electrode pads required for the TEG pattern 6a can be reduced. Specifically, as shown in FIG. 1, the seven TEG elements 8a to 8g can be measured with the eight electrode pads 9a to 9h.

  By reducing the number of electrode pads in this way, the amount of metal cutting during dicing can be reduced, and the occurrence of chipping and cracks can be suppressed.

  As mentioned above, according to 1st Embodiment, the semiconductor device 10 which suppressed the defect at the time of dicing using the semiconductor substrate which has the TEG pattern 6a can be provided.

(Second Embodiment)
FIG. 7 is an enlarged view of the TEG element 8 according to the second embodiment. FIG. 7A is a plan view of the TEG element 8 according to the second embodiment. Moreover, FIG.7 (b) is CC 'sectional view taken on the line in Fig.7 (a). The second embodiment is the same as the first embodiment except for the configuration of the TEG element 8. Details will be described below.

  As shown in FIG. 7A, the TEG element 8 of the second embodiment is a wiring resistance, as in the first embodiment. However, in the second embodiment, the wiring resistance includes a plurality of vias (second vias 330) provided in the interlayer insulating layer 200. As a result, a wiring resistance can be formed across a large number of interlayer insulating layers 200. Further, by providing a plurality of vias (not shown), the TEG element 8 can be connected to the electrode pads 9b to 9h. Here, the first wiring 320, the second via 330, and the second wiring 340 form the TEG element 8 having a wiring resistance that is bent in an S shape in plan view.

  Further, as shown in FIG. 7B, the TEG element 8 is formed to be bent a plurality of times in the cross-sectional direction from the first wiring 320 to the second wiring 340 via the second via 330. . Thereby, the resistance value of the second via 330 can be predicted.

(Third embodiment)
FIG. 8 is an enlarged view of the TEG element 8 according to the third embodiment. FIG. 8A is a plan view of the TEG element 8 according to the third embodiment. FIG. 8B is a cross-sectional view taken along the line DD ′ in FIG. The third embodiment is the same as the first embodiment except for the configuration of the TEG element 8. Details will be described below.

  As shown in FIG. 8A, the TEG element 8 of the third embodiment is a resistor as in the first embodiment. However, in the third embodiment, the resistance is the diffusion resistance layer 148 in which impurities are introduced into the semiconductor substrate 100. The diffusion resistance layer 148 is ion-implanted with the same amount by the same impurities as the diffusion layer 140 in the semiconductor chip 2. Thereby, the resistance value of the diffusion layer 140 in the semiconductor chip 2 can be predicted. Here, the TEG element 8 is formed by the first via 310, the first wiring 320, and the diffusion resistance layer 148. The diffused resistance layer 148 has an H shape in plan view, and a portion sandwiched between regions where the first vias 310 are formed serves as a measurement region.

  As shown in FIG. 8B, a diffusion resistance layer 148 is formed in the opening of the element isolation region 160. The first via 310 is provided so as to be in contact with the diffusion resistance layer 148 and is connected to the first wiring 320. The left first wiring 320 in FIG. 8B extends in the direction of the seal ring 5a and is connected to the seal ring 5a. On the other hand, the first wiring 320 on the right side in FIG. 8B is connected to a via (not shown) connected to the electrode pad 9b and the like. The resistance value of the diffusion resistance layer 148 can be measured by applying a voltage between electrode pads (not shown) connected to the first wiring 320 at both ends and measuring the current value.

(Fourth embodiment)
A semiconductor device 10 according to the fourth embodiment will be described with reference to FIGS. 9 to 11. The fourth embodiment is the same as the first embodiment except that the TEG element 8 includes a transistor. Details will be described below.

  FIG. 9 is a plan view showing the configuration of the semiconductor device 10 according to the fourth embodiment. As will be described later, in the fourth embodiment, the TEG element 8h and the TEG element 8i include, for example, a transistor such as an FET (Field Effect Transistor). Of the TEG element 8h, the well terminal is connected to the seal ring 5a via the TEG wiring 7. Of the TEG element 8h, the gate terminal, the source terminal, and the drain terminal are connected to the electrode pad 9a, the electrode pad 9b, and the electrode pad 9c, respectively. Similarly, for the TEG element 8i, the well terminal, the gate terminal, the source terminal, and the drain terminal are connected to the seal ring 5a, the electrode pad 9g, the electrode pad 9e, and the electrode pad 9f, respectively.

  The electrode pad 9d is directly connected to the seal ring 5a. Further, the resistance TEG element 8a is connected to the seal ring 5a and the electrode pad 9h.

  FIG. 10 is an equivalent circuit diagram of the TEG pattern 6b according to the fourth embodiment. As shown in FIG. 10, the electrode pad 9d is connected to the well terminals of the TEG element 8h and the TEG element 8i through the seal ring 5a. Therefore, the well potential of the TEG element 8h and the TEG element 8i can be controlled by controlling the common electrode pad 9d during the inspection process.

  FIG. 11 is an enlarged view of the TEG element 8 according to the fourth embodiment. FIG. 11A is a plan view of the TEG element 8 according to the fourth embodiment. Moreover, FIG.11 (b) is the EE 'sectional view taken on the line in Fig.11 (a). The TEG element 8 in FIG. 11 is the TEG element 8h or the TEG element 8i in FIGS. The TEG element 8a is the same as that in the first embodiment.

  As shown in FIG. 11A, a source region 142 and a drain region 144 are formed on both sides of the gate terminal 312. A diffusion layer 140 is formed in a region that does not overlap with the source / drain region 142 and the drain region 144 in plan view, and functions as a well terminal.

  As shown in FIG. 11B, a source region 142 and a drain region 144 are formed in the opening of the element isolation region 160. Furthermore, a diffusion layer 140 as a well terminal is formed in the opening of the element isolation region 160 spaced from the source region 142 and the drain region 144. A gate terminal 312 is formed on a channel region (not shown) sandwiched between the source region 142 and the drain region 144. A first via 310 is formed on each of the source region 142 and the drain region 144.

  According to the fourth embodiment, the TEG element 8 including the transistor as described above is formed. Thereby, the characteristics of the transistor in the semiconductor chip 2 can be predicted by inspecting the TEG pattern 6b.

  Further, as a comparative example, when the common wiring is not used, in order to measure the TEG element 8h and the TEG element 8i of the two transistors described above, eight transistors for the well, gate, source, and drain in each transistor are used. An electrode pad is required.

  On the other hand, according to the fourth embodiment, the well terminal of the two TEG elements 8h and TEG element 8i is connected to the seal ring 5a. As a result, the seal ring 5a can be used as a common wiring for the well terminals. Therefore, there are seven electrode pads for measuring the TEG element 8h and the TEG element 8i. That is, the number of electrode pads can be reduced. Further, the number of TEG elements can be increased with the same number of electrode pads, for example, by connecting a resistive TEG element 8a to the surplus electrode pad 9h.

(Fifth embodiment)
A semiconductor device 10 according to the fifth embodiment will be described with reference to FIGS. The fourth embodiment is the same as the first embodiment except that the two seal rings 5a and 5b are used as common wiring and that the TEG element 8 includes a short check element. Details will be described below.

  FIG. 12 is a plan view showing the configuration of the semiconductor device 10 according to the fifth embodiment. As shown in FIG. 12, the electrode pad 9a is directly connected to the seal ring 5a. On the other hand, the electrode pad 9b is connected to the seal ring 5b at a position facing the seal ring 5a with the dicing region 3 in between. Therefore, in the fifth embodiment, the two seal rings 5a and 5b are used as a common wiring.

  The dicing region 3 is provided with resistance TEG elements 8a to 8f. The resistance TEG elements 8a to 8f are directly connected to the seal ring 5a. Furthermore, the dicing region 3 is provided with TEG elements 8j to 8o which are short confirmation elements as will be described later. The TEG elements 8j to 8o, which are short confirmation elements, are directly connected to the seal ring 5b.

  In addition, electrode pads 9c to 9h are provided between the TEG elements 8a to 8f of resistance and the TEG elements 8j to 8o, which are short check elements, via TEG wirings 7, respectively.

  FIG. 13 is an equivalent circuit diagram of the TEG pattern 6c according to the fifth embodiment. The TEG elements 8j to 8o, which are short confirmation elements, are shown as capacitors. As described above, the seal ring 5a and the seal ring 5b are common wirings on both sides in FIG. Details of the inspection process of the TEG pattern 6c will be described later.

  FIG. 14 is an enlarged view of the TEG element 8 according to the fifth embodiment. FIG. 14A is a plan view of the TEG element 8 according to the fifth embodiment. Moreover, FIG.14 (b) is the FF 'sectional view taken on the line in Fig.14 (a). Note that the TEG elements 8 in FIG. 14 are the TEG elements 8j to 8o in FIGS. Further, the TEG elements 8a to 8f are the same as in the first embodiment.

  As shown in FIG. 14A, the TEG element 8 includes a short check element in which wirings (first wirings 320) are alternately provided in a comb shape.

  As shown in FIG. 14B, the first wiring 320 of the TEG element 8 is provided in the same first wiring formation insulating layer 220. The first wirings 320 that are alternately spaced apart by the TEG elements 8 are provided, for example, at the same interval as the wiring pitch in the first wiring 320 such as the semiconductor chip 2a. Thus, in the inspection process, it is possible to predict whether or not a short circuit due to the patterning failure has occurred in the first wiring 320 such as the semiconductor chip 2a by inspecting the leakage current of the TEG element 8.

  Next, returning to FIG. 13 again, the inspection process of the TEG pattern 6c will be described. In the inspection process of the TEG pattern 6c, the TEG element 8a and the TEG element 8j connected to the electrode pad 9c will be described as an example.

  The electrode pad 9a and the electrode pad 9b are fixed to the GND potential. As described above, the electrode pad 9a and the electrode pad 9b are connected to the seal ring 5a and the seal ring 5b, respectively. For this reason, the seal ring 5a and the seal ring 5b are also fixed to the GND potential.

  Next, a voltage is applied to the electrode pad 9c to which the TEG element 8a and the TEG element 8j are connected. At this time, the current value flowing out from the electrode pad 9a and the electrode pad 9b is measured. Thereby, the resistance value can be measured by the TEG element 8a. On the other hand, when a current flows from the electrode pad 9b, it can be determined that a short circuit has occurred in the TEG element 8j. That is, in the semiconductor chip 2a and the like, it can be determined that a short circuit has occurred in a portion having the same wiring pitch.

  According to the fifth embodiment, the TEG element 8 including the short check element as described above is formed. Thereby, the presence or absence of a short circuit in the semiconductor chip 2 can be predicted by inspecting the TEG pattern 6c.

  Further, according to the fifth embodiment, the two seal rings 5a and 5b are used for the common wiring. As a result, more TEG elements 8 can be provided in the dicing region 3.

(Sixth embodiment)
A semiconductor device 10 according to the sixth embodiment will be described with reference to FIGS. 15 and 16. The sixth embodiment is the same as the fourth embodiment except that two seal rings 5a and 5b are used as common wiring. Details will be described below.

  FIG. 15 is a plan view showing the configuration of the semiconductor device 10 according to the sixth embodiment. As will be described later, in the fourth embodiment, the TEG element 8h and the TEG element 8i are, for example, FETs. Of the TEG element 8 h and the TEG element 8 i, the well terminal is connected to the seal ring 5 a via the TEG wiring 7. On the other hand, the gate terminal of the TEG element 8 h and the TEG element 8 i is connected to the seal ring 5 b via the TEG wiring 7. Therefore, in the sixth embodiment, the seal ring 5a is a common wiring for the well terminals, while the seal ring 5b is a common wiring for the gate terminals.

  Further, in the TEG element 8h, the source terminal and the drain terminal are connected to the electrode pad 9a and the electrode pad 9b, respectively. Similarly, for the TEG element 8i, the source terminal and the drain terminal are connected to the electrode pad 9e and the electrode pad 9f, respectively.

  The electrode pad 9c and the electrode pad 9d are directly connected to the seal ring 5a. Further, the resistance TEG element 8a is connected to the seal ring 5a and the electrode pad 9h. Similarly, the resistance TEG element 8b is connected to the seal ring 5a and the electrode pad 9g.

  FIG. 16 is an equivalent circuit diagram of the TEG pattern 6b according to the sixth embodiment. As shown in FIG. 16, the electrode pad 9c is connected to the well terminals of the TEG element 8h and the TEG element 8i through the seal ring 5a. Therefore, the well potential of the TEG element 8h and the TEG element 8i can be controlled by controlling the common electrode pad 9c during the inspection process.

  On the other hand, the electrode pad 9d is connected to the gate terminals of the TEG element 8h and the TEG element 8i through the seal ring 5b. Therefore, the gate potentials of the TEG element 8h and the TEG element 8i can be controlled by controlling the common electrode pad 9d during the inspection process.

  According to the sixth embodiment, the same effect as in the fourth embodiment can be obtained.

  Specifically, according to the sixth embodiment, of the two TEG elements 8h and TEG elements 8i, the well terminal is connected to the seal ring 5a. Furthermore, the gate terminal is connected to the seal ring 5b. As a result, the seal ring 5a can be used as a common wiring for the well terminals, and the seal ring 5b can be used as a common wiring for the gate terminals. Therefore, the number of electrode pads for measuring the TEG element 8h and the TEG element 8i is six. That is, the number of electrode pads can be reduced. Further, the number of TEG elements can be increased with the same number of electrode pads, such as connecting the TEG elements 8a and TEG elements 8b having resistance to the surplus electrode pads 9g and electrode pads 9h.

(Seventh embodiment)
A semiconductor device 10 according to the seventh embodiment will be described with reference to FIG. The seventh embodiment is the same as the first embodiment except for the following points. The semiconductor substrate 100 is not separated. At least one TEG wiring (7d) is connected to each seal ring 5 (seal ring 5a and seal ring 5c) of a plurality of semiconductor chips 2 (semiconductor chip 2a and semiconductor chip 2c) adjacent to each other. Yes. Details will be described below.

  FIG. 17 is a plan view showing the configuration of the semiconductor device according to the seventh embodiment. The semiconductor substrate 100 is not separated. Here, the semiconductor chip 2a, the semiconductor chip 2b, the semiconductor chip 2c, and the semiconductor chip 2d are adjacent to each other without being separated.

  The TEG wiring 7d is connected to the seal ring 5a and the seal ring 5b of the semiconductor chip 2a and the semiconductor chip 2c adjacent to each other. The “TEG wiring 7d” here is formed, for example, in the same layer as the TEG wiring 7a for electrode connection described above. That is, the TEG wiring 7 d is provided so as to be in contact with the uppermost layer of the interlayer insulating layer 200.

  Thus, in the seventh embodiment, the TEG pattern 6e is provided across the plurality of semiconductor chips 2 adjacent to each other.

  Next, effects of the seventh embodiment will be described.

  When a large number of TEG elements 8 are arranged, there is a possibility that they cannot be arranged simply by connecting to the seal ring 5a of one semiconductor chip 2a as in the first embodiment.

  On the other hand, according to the seventh embodiment, the TEG wiring 7d is connected to each seal ring 5 of the plurality of semiconductor chips 2 adjacent to each other. Thereby, the TEG pattern 6e can be provided in a wider range by connecting to the seal rings 5 of the plurality of semiconductor chips 2.

  In the seventh embodiment, the case where the TEG wiring 7d is connected to the two seal rings 5 has been described. However, the other TEG wiring 7 may be used to connect to the plurality of seal rings 5. Good.

(Eighth embodiment)
A semiconductor device 10 according to the eighth embodiment will be described with reference to FIGS. 18 and 19. The eighth embodiment is the same as the first embodiment except for the following points. The TEG elements 8a to 8g are provided inside the seal ring 5a in plan view. One end of the TEG wiring 7d is connected to the TEG elements 8a to 8g, and the other end is not in contact with the seal ring 5a and extends toward the end face of the outer periphery of the semiconductor chip 2a beyond the seal ring 5a. is doing. Further, the TEG wiring 7e for element connection has one end connected to the TEG elements 8a to 8g and the other end connected to the seal ring 5a. Details will be described below.

  FIG. 18 is a plan view showing the configuration of the semiconductor device 10 according to the eighth embodiment. As shown in FIG. 18, the TEG elements 8a to 8g are provided inside the seal ring 5a in a plan view. Here, “inside the seal ring 5a” means the inside of the seal ring 5a in the semiconductor chip 2a in plan view.

  Here, inside the seal ring 5a, an electrode pad 50 connected to an internal circuit (not shown) in the semiconductor chip 2a is provided. The distance between the electrode pad 50 and the seal ring 5a in the semiconductor chip 2a is, for example, about 10 μm. This suppresses cracks in the passivation film 500 and deformation of Al constituting the electrode pad 50 due to thermal stress received in the manufacturing process of the semiconductor device 10.

  The TEG elements 8a to 8g are provided in a region between the electrode ring 50 connected to an internal circuit (not shown) in the semiconductor chip 2a and the seal ring 5a. Thereby, the dead space in the semiconductor chip 2a can be effectively used for arranging the TEG elements 8a to 8g.

  One end of the TEG wiring 7d is connected to the TEG elements 8a to 8g, and the other end is not in contact with the seal ring 5a and extends toward the end face of the outer periphery of the semiconductor chip 2a beyond the seal ring 5a. is doing. Here, for example, the other end of the TEG wiring 7d is connected to the electrode pads 9b to 9h.

  Further, in the eighth embodiment, there may be a TEG wiring 7 having one end connected to the seal ring 5a and the other end extending toward the outer peripheral end surface of the semiconductor chip 2a and connected to the electrode pad 9a. .

  Further, the TEG wiring 7e for element connection has one end connected to the TEG elements 8a to 8g and the other end connected to the seal ring 5a. That is, the TEG wiring 7e for element connection is also provided on the inner side of the seal ring 5a in a plan view like the TEG elements 8a to 8g. Therefore, the TEG elements 8a to 8g and the TEG wiring 7e for element connection remain in the semiconductor chip 2a even after dicing.

  FIG. 19 is a cross-sectional view showing the configuration of the semiconductor device according to the eighth embodiment. FIG. 19 is a cross-sectional view taken along the line GG ′ in FIG.

  As shown in FIG. 19, the fourth wiring 400 including the electrode pad 9 b is provided so as to be in contact with the uppermost layer of the interlayer insulating layer 200. The TEG wiring 7d is a via provided in the same layer as a part of the fourth wiring 400, the third wiring 360, the third via 350, the second wiring 340, the second via 330, and the first wiring 320 (FIG. 19). In the middle, a portion indicated by an arrow 7d) is connected to the TEG element 8a.

  The above-mentioned state that “the other end of the TEG wiring 7d does not come into contact with the seal ring 5a” means that the TEG wiring 7d and the seal ring are provided at a distance. That is, the TEG wiring 7d and the seal ring 5a are insulated by the fourth interlayer insulating layer 270.

  Further, the above-mentioned state that “the TEG wiring 7d has the other end beyond the seal ring 5a” means that the TEG wiring 7d is further above the fourth interlayer insulating layer 270 provided on the seal ring 5a, for example. It means the state that is provided.

  Further, as described above, the fourth interlayer insulating layer 270 is, for example, SiN. For this reason, even when the TEG wiring 7 as described above is provided, moisture does not propagate through the fourth interlayer insulating layer 270.

  According to the eighth embodiment, the TEG element 8 is provided inside the seal ring 5 in plan view. Thereby, the TEG wiring 7 etc. in the dicing area 3 can be reduced. Therefore, the amount of metal cutting during dicing can be further reduced.

(Ninth embodiment)
A semiconductor device 10 according to the ninth embodiment will be described with reference to FIG. The ninth embodiment is the same as the first embodiment except for the following points. The electrode pad 9 and the TEG wiring 7a for electrode connection contain Cu. The TEG wiring 7a for electrode connection is located below the uppermost layer of the interlayer insulating layer 200, and is provided on the semiconductor chip 2 side of the dicing region 3 from the region cut by the dicing blade (cutting region 4). A wiring portion (third wiring 362). Details will be described below.

  FIG. 20 is a cross-sectional view showing the configuration of the semiconductor device according to the ninth embodiment. In the ninth embodiment, the electrode pad 9 and the TEG wiring 7a for electrode connection are, for example, Cu. Here, the “TEG wiring 7a for electrode connection” has a plurality of layers (a part of the third wiring 362 and the fourth wiring 400) through the fourth via 402 in the interlayer insulating layer 200, as will be described later. And is connected to the seal ring 5a. Accordingly, the cross-sectional configuration is different from that of the first embodiment as described below.

  As shown in FIG. 20, the configuration up to the third via formation insulating layer 250 is the same as that of the first embodiment. On the third via forming insulating layer 250, a third wiring forming insulating layer 260, a fourth via forming insulating layer 272, a fourth wiring forming insulating layer 280, and a fifth interlayer insulating layer 290 are formed. The fourth via forming insulating layer 272 and the fourth wiring forming insulating layer 280 are, for example, low dielectric constant layers. The fifth interlayer insulating layer 290 has a protective film function and is, for example, SiN.

  A fourth wiring 400 including the electrode pad 9 is formed on the fourth wiring formation insulating layer 280. Furthermore, the fourth wiring 400 includes a part of the TEG wiring 7a for electrode connection.

  Further, the TEG wiring 7a for electrode connection includes a fourth via 402, for example. A part of the TEG wiring 7 a for electrode connection in the fourth wiring 400 is connected to a third wiring 362 described later through the fourth via 402. The fourth via 402 may be a part of the fourth wiring 400.

  The electrode connecting TEG wiring 7 a includes a wiring portion located below the uppermost layer of the interlayer insulating layer 200. In the ninth embodiment, the wiring portion is the third wiring 362. The third wiring 362 is provided on the semiconductor chip 2 side of the dicing area 3 with respect to the area cut by the dicing blade (cutting area 4). That is, the wiring portion is provided so that the end face is not exposed when dicing. Thereby, the wiring part of the TEG wiring 7a for electrode connection is not oxidized. Note that the wiring portion is not limited to the same layer as the third wiring 360, and may be provided in another wiring formation insulating layer below.

  Here, the 3rd wiring 362 which is an above-mentioned wiring part may be connected to seal ring 5a.

  In the ninth embodiment, the electrode connecting TEG wiring 7 a is connected to the seal ring 5 a in the same layer as the electrode pad 9. Here, the TEG wiring 7a for electrode connection is connected to the seal ring 5a in the fourth wiring 400 by connecting to the fourth wiring 400 that is the same layer as the electrode pad 9 through the fourth via 402 again. is doing. Accordingly, even if the third wiring 362 is exposed due to chipping during dicing, the propagation of moisture can be delayed.

  Next, effects of the ninth embodiment will be described.

  When wiring containing Cu is exposed when dicing, the wiring containing Cu is oxidized by moisture absorption or the like. When this oxidation propagates to the seal ring 5 or the semiconductor chip 2, there is a possibility that defects such as cracks may occur.

  On the other hand, according to the ninth embodiment, the TEG wiring 7 a for electrode connection containing Cu is located below the uppermost layer of the interlayer insulating layer 200, and the semiconductor chip is lower than the cutting region 4 in the dicing region 3. The wiring part provided in the 2 side is provided. Thereby, when dicing, the wiring part containing Cu is not exposed. Therefore, the wiring portion of the TEG wiring 7a for electrode connection is not oxidized, and defects such as cracks can be suppressed.

(Tenth embodiment)
The semiconductor device 10 according to the tenth embodiment will be described with reference to FIG. The tenth embodiment is the same as the first embodiment except that the electrode pad 9a or the like or the TEG element 8a or the like is arranged closer to the semiconductor chip 2a than the end of the cutting region 4. Details will be described below.

  FIG. 21 is a plan view showing the configuration of the semiconductor device 10 according to the tenth embodiment. FIG. 21A and FIG. 21B show different arrangements of the electrode pads 9a or the like or the TEG elements 8a or the like. FIG. 21A and FIG. 21B are diagrams before dicing.

  As shown in FIG. 21A, the electrode pads 9 a to 9 d are arranged closer to the semiconductor chip 2 a than the end of the cutting region 4. When the semiconductor substrate 100 is diced, the semiconductor device 10 is obtained in which the TEG wiring 7 connected to the seal ring 5a and part of the electrode pads 9a to 9d remain as the semiconductor chip 2a.

  As shown in FIG. 21B, the electrode pads 9 a to 9 d and the TEG elements 8 a to 8 c are arranged on the semiconductor chip 2 a side from the end of the cutting region 4. When the semiconductor substrate 100 is diced, the semiconductor device 10 in which the TEG wiring 7 connected to the seal ring 5a, part of the electrode pads 9a to 9d, and part of the TEG elements 8a to 8c remain as the semiconductor chip 2a. Is obtained.

  According to the tenth embodiment, the electrode pad 9 a or the like or the TEG element 8 a or the like is arranged on the semiconductor chip 2 a side from the end of the cutting region 4. Thereby, the semiconductor device 10 in which the electrode pad 9a or the like or the TEG element 8a or the like partially remains inside the cutting region 4 in a plan view is obtained. Even in such a case, the amount of metal cutting during dicing can be reduced, and the occurrence of chipping and cracks can be suppressed.

  Note that the TEG element 8a and the like described in the above embodiments may include a plurality of different elements described in the first to ninth embodiments. In addition to the above-described TEG element 8a and the like, an inductor or a capacitor may be used.

  As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.

DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 2, 2a-2d Semiconductor chip 3 Dicing area | region 4 Cutting area | region 5, 5a-5d Seal ring 6a-6f TEG pattern 7, 7a-7e TEG wiring 8, 8a-8i TEG element 9a-9h Electrode pad 10 Semiconductor device 50 Electrode pad 100 Semiconductor substrate 120 Well 140 Diffusion layer 142 Source region 144 Drain region 148 Diffusion resistance layer 160 Element isolation region 200 Interlayer insulation layer 210 First via formation insulation layer 220 First wiring formation insulation layer 230 Second via formation insulation layer 240 Second wiring formation insulating layer 250 Third via formation insulation layer 260 Third wiring formation insulation layer 270 Fourth interlayer insulation layer 272 Fourth via formation insulation layer 280 Fourth wiring formation insulation layer 290 Fifth interlayer insulation layer 310 First Via 312 Gate terminal 320 First wiring 330 Second via 340 Second wiring 35 0 third via 360 third wiring 362 third wiring 400 fourth wiring 402 fourth via 500 passivation film

Claims (23)

A semiconductor chip separated into semiconductor chips by dicing, or a semiconductor substrate separated into pieces;
An interlayer insulating layer formed on the semiconductor substrate;
A seal ring provided in the interlayer insulating layer and formed along a peripheral edge of the semiconductor chip;
TEG wiring having one end connected to the seal ring and the other end extending toward the outer peripheral end surface of the semiconductor chip;
A semiconductor device comprising: The semiconductor device according to claim 1,
A semiconductor device further comprising a TEG element provided on the semiconductor substrate or the interlayer insulating layer and connected to the seal ring via the TEG wiring for element connection. A semiconductor chip separated into semiconductor chips by dicing, or a semiconductor substrate separated into pieces;
An interlayer insulating layer formed on the semiconductor substrate;
A seal ring provided in the interlayer insulating layer and formed along a peripheral edge of the semiconductor chip;
A TEG element provided inside the seal ring in plan view;
TEG wiring having one end connected to the TEG element and the other end not contacting the seal ring and extending toward the outer peripheral end surface of the semiconductor chip beyond the seal ring;
TEG wiring for element connection, one end connected to the TEG element and the other end connected to the seal ring;
A semiconductor device comprising: The semiconductor device according to claim 2 or 3,
The TEG element is a semiconductor device including a resistor. The semiconductor device according to claim 4,
The semiconductor device is a wiring resistor. The semiconductor device according to claim 4,
The semiconductor device is a diffusion resistance layer in which an impurity is introduced into the semiconductor substrate. In the semiconductor device according to any one of claims 2 to 6,
The TEG element is a semiconductor device including a short check element in which wirings are alternately provided in a comb shape. In the semiconductor device according to any one of claims 2 to 7,
The TEG element is a semiconductor device including a transistor. In the semiconductor device according to any one of claims 2 to 8,
The TEG element is a semiconductor device including a plurality of vias provided in the interlayer insulating layer. The semiconductor device according to any one of claims 1 to 9,
A semiconductor device that is disposed in a dicing region outside the seal ring in plan view, is provided so as to be in contact with the uppermost layer of the interlayer insulating layer, and further includes an electrode pad that is connected to the TEG wiring for electrode connection . The semiconductor device according to claim 10.
The semiconductor device provided so that the electrode pad and the TEG wiring for electrode connection are made of Al and are in contact with the uppermost layer of the interlayer insulating layer. The semiconductor device according to claim 10.
The electrode pad and the TEG wiring for electrode connection include Cu,
The TEG wiring for electrode connection is located below the uppermost layer of the interlayer insulating layer, and includes a wiring portion provided on the semiconductor chip side of the dicing region from a region cut by a dicing blade. Semiconductor device. The semiconductor device according to claim 12,
The semiconductor device in which the TEG wiring for electrode connection is connected to the seal ring in the same layer as the electrode pad. In the semiconductor device according to any one of claims 10 to 13,
The width | variety of the said electrode pad is a semiconductor device smaller than the dicing blade width | variety at the time of dicing the said semiconductor substrate. The semiconductor device according to any one of claims 1 to 14,
The semiconductor substrate is not singulated,
The semiconductor device in which at least one or more of the TEG wirings are connected to the seal rings of the plurality of adjacent semiconductor chips. The semiconductor device according to any one of claims 1 to 15,
The semiconductor device includes a diffusion layer provided at a portion in contact with the seal ring and into which an impurity having a conductivity type opposite to that of the semiconductor substrate is introduced. The semiconductor device according to claim 1,
The semiconductor device in which the seal ring is a ground wire. The semiconductor device according to any one of claims 1 to 17,
The interlayer insulating layer is a semiconductor device including a low dielectric constant layer having a relative dielectric constant of 3 or less. A step of forming a multilayer wiring including an interlayer insulating layer on a semiconductor substrate separated into a plurality of semiconductor chips,
In the step of forming the multilayer wiring,
In the interlayer insulating layer, forming a seal ring along the peripheral edge of the semiconductor chip,
A method for manufacturing a semiconductor device, wherein one end is connected to the seal ring and the other end forms a TEG wiring extending toward an outer peripheral end face of the semiconductor chip. In the manufacturing method of the semiconductor device according to claim 19,
In the step of forming the multilayer wiring, an electrode pad connected to the TEG wiring for electrode connection is disposed in a dicing region outside the seal ring in a plan view so as to be in contact with the uppermost layer of the interlayer insulating layer. A method for manufacturing a semiconductor device to be formed. In the manufacturing method of the semiconductor device according to claim 19 or 20,
A method of manufacturing a semiconductor device, wherein, in the step of forming the multilayer wiring, a TEG element connected to the seal ring is formed on the semiconductor substrate or the interlayer insulating layer via the TEG wiring for element connection. In the manufacturing method of the semiconductor device according to claim 21,
An inspection step of inspecting the TEG element by applying a voltage to the electrode pad;
In the inspection step, when the TEG element is defective, it is determined that the semiconductor element in the semiconductor chip is defective. When the TEG element is not defective, the TEG element is not defective. A method of manufacturing a semiconductor device, in which a semiconductor element is determined to be free of defects and can be shipped. In the manufacturing method of the semiconductor device according to claim 22,
A manufacturing method of a semiconductor device comprising a dicing step of dicing into a plurality of the semiconductor chips by dicing the dicing region including the electrode pads in the semiconductor substrate after the inspection step.

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