JP5428001B2 - Resistance evaluation wafer and resistance evaluation method - Google Patents

Description

  According to the present invention, a semiconductor wafer using a low dielectric constant (low-k) material having a dielectric constant k of generally 3 or less as an insulating film, or each cell of the semiconductor wafer is individually diced. The present invention relates to a resistance evaluation wafer and a resistance evaluation method for evaluating the pressure resistance of an insulating film due to an external load in divided semiconductor chips. In particular, a force applied by the probe needle (hereinafter referred to as probe load) or a bonding process when the probe needle is applied to the bonding pad of each cell of the semiconductor wafer and an electrical test is performed on each cell in the wafer test process. Relates to a wafer for resistance evaluation and a resistance evaluation method for evaluating a pressure resistance of an insulating film by a force (hereinafter, referred to as a bonding load) applied through a bonding tool when bonding a wire to a bonding pad of a semiconductor chip. .

  In recent years, low dielectric constant (low-k) materials have been used as insulating films (interlayer insulating films, inter-wiring insulating films) that insulate between adjacent wirings in a semiconductor chip in order to increase the speed of next-generation semiconductor devices. Applied technology is used.

  This insulating film using a low dielectric constant (low-k) material (hereinafter referred to as a low-k insulating film) is porous and has a weak mechanical strength, so that a semiconductor chip is mounted. In doing so, the laminated film is broken or peeled off, causing the wiring inside the semiconductor chip to break.

  For this reason, when developing and manufacturing a semiconductor chip, it is important to evaluate in advance the pressure resistance of the low-k insulating film assuming an external load applied to the low-k insulating film in the assembly process (post-process). It is a requirement.

On the other hand, the conventional bonding resistance evaluation element has a form in which the fragile wiring layer in the lower structure of the bonding pad is replaced with a metal film, and the number of metal films in the fragile wiring layer to be evaluated or Using the size as a variable, bonding resistance is evaluated based on the rate of occurrence of peeling in the number of metal film layers under the pad (see, for example, Patent Document 1).
JP 2007-227815 A

  However, the evaluation of bonding resistance using a conventional bonding resistance evaluation element is based on the calculation of the peeling occurrence rate in the number of metal film layers under the pad. It is considered that the part (number) of occurrence of the peeling phenomenon is visually detected by observing with a microscope.

For this reason, the evaluation of bonding resistance using a conventional element for evaluating bonding resistance takes a long time, is not necessarily accurate, and there is a problem that a portion where a peeling phenomenon occurs may be overlooked.
The present invention has been made to solve the above-described problems, and provides a resistance evaluation wafer and a resistance evaluation method capable of accurately evaluating the pressure resistance of an insulating film due to an external load in a short time. To do.

In the tolerance evaluation wafer according to the present invention, a pair of wirings disposed opposite to each other via a low-k insulating film on a substrate, and one of the pair of wirings is connected via a via. A first connection pad disposed on the uppermost layer, a second connection pad disposed on the uppermost layer, connected to the other wiring of the pair of wirings via a via, and a flat surface on the uppermost layer. are several arranged as a terminal, and a pressure pad that is pressed with a predetermined load, said pressing pad and the pair of wires, it is in the electrically floating state via the insulating film, the substrate On the other hand, when the perspective projection is performed in the vertical direction, the pressing pad is disposed so as to be superimposed on a part of the one wiring and / or another wiring or to be disposed between the one wiring and the other wiring. and has, double that is formed by the said pair of wires and the pressing pad Capacitance of, are connected in parallel, by a change in the capacitance and / or the combined capacitance of the plurality of electrostatic capacitance, it is to evaluate the withstanding pressure of the low-k dielectric film.

  In the tolerance evaluation wafer according to the present invention, the first connection pad, the second connection pad, and the pressing pad are collectively formed by patterning the conductive thin film in the same layer. .

In the tolerance evaluation wafer according to the present invention, a pair of wirings disposed opposite to each other via a low-k insulating film on a substrate, and one of the pair of wirings is connected via a via. A first connection pad disposed on the uppermost layer, a second connection pad disposed on the uppermost layer, connected to the other wiring of the pair of wirings via a via, and a flat surface on the uppermost layer. are several arranged as a terminal, and a pressure pad that is pressed with a predetermined load, said pressing pad and the pair of wires, it is in the electrically floating state via the insulating film, the substrate On the other hand, when the perspective projection is performed in the vertical direction, the pressing pad is disposed so as to be superimposed on a part of the one wiring and / or another wiring or to be disposed between the one wiring and the other wiring. and has, double that is formed by the said pair of wires and the pressing pad The capacitance are connected in parallel, by a change in the capacitance and / or the combined capacitance of the plurality of capacitance, by evaluating the pressure resistance of the low-k insulating film, pressing Based on a change in capacitance between one wiring and another wiring by applying a predetermined pressure to the pad from the outside, the pressure resistance of the low-k insulating film due to the bonding load is accurately evaluated in a short time. be able to.

  Moreover, in the wafer for resistance evaluation according to the present invention, the first connection pad, the second connection pad, and the press pad are collectively formed by patterning the conductive thin film of the same layer, The manufacturing cost of the tolerance evaluation wafer can be reduced without increasing the number of wafer processing steps.

(First embodiment of the present invention)
FIG. 1A is a plan view showing a schematic configuration of a resistance evaluation wafer according to the first embodiment, and FIG. 1B is an enlarged view of one cell in the resistance evaluation wafer shown in FIG. FIG. 2 (a) is an enlarged view, FIG. 2 (a) is a plan view showing a schematic configuration of the resistance evaluation structure disposed in the cell shown in FIG. 1 (b), and FIG. 2 (b) is the resistance evaluation structure shown in FIG. 2 (a). 3A is an end view of the resistance evaluation structure shown in FIG. 2A, and FIG. 3B is an end view of the resistance evaluation structure shown in FIG. 2A. FIG. 4A is a plan view showing a schematic configuration of another resistance evaluation structure arranged in the cell shown in FIG. 1B, FIG. 4B. ) Is a sectional view taken along the line DD of the resistance evaluation structure shown in FIG. 4 (a), FIG. 5 (a) is an end view taken along the line EE of the resistance evaluation structure shown in FIG. 4 (a), FIG. 5 (b) is shown in FIG. 4 (a). FIG. 6A is a plan view showing a schematic configuration of still another tolerance evaluation structure disposed in the cell shown in FIG. 1B. FIG. b) is a sectional view taken along line GG of the resistance evaluation structure shown in FIG. 6A, and FIG. 7A is an end view taken along line HH of the resistance evaluation structure shown in FIG. 7 (b) is an end view taken along the line II of the resistance evaluation structure shown in FIG. 6 (a), and FIG. 8 (a) is another resistance arranged in the cell shown in FIG. 1 (b). FIG. 8B is a plan view showing a schematic configuration of the evaluation structure, FIG. 8B is a cross-sectional view taken along line JJ of the resistance evaluation structure shown in FIG. 8A, and FIG. FIG. 9B is an end view of the resistance evaluation structure taken along the line KK, FIG. 9B is an end view of the resistance evaluation structure shown in FIG. 8A, and FIG. b) Schematic structure of another resistance evaluation structure disposed in the cell shown in b) FIG. 10 (b) is a plan view showing a schematic configuration of still another resistance evaluation structure disposed in the cell shown in FIG. 1 (b), and FIG. 11 (a) is shown in FIG. 1 (b). The top view which shows schematic structure of the other tolerance evaluation structure arrange | positioned at the cell shown, FIG.11 (b) shows schematic structure of the further another tolerance evaluation structure arrange | positioned at the cell shown in FIG.1 (b). It is a top view.

  The wafer 100 for durability evaluation is obtained by arranging test patterns such as predetermined wirings, pads, and circuit elements in each cell by a wafer processing process (pre-process) on a wafer manufactured through a wafer manufacturing process. There are at least one cell 110 shown in FIG. Each cell of the tolerance evaluation wafer 100 is an area corresponding to one semiconductor chip formed by dividing the tolerance evaluation wafer 100 individually by dicing.

As shown in FIG. 1B, the cell 110 is provided with a plurality of pads 111 along the periphery, and a resistance evaluation structure 10 described later is provided in a predetermined region.
In addition, although the tolerance evaluation structure 10 which concerns on this embodiment has shown the example arrange | positioned so that the approximate center of the edge | side which the cell 110 opposes may be crossed as shown in FIG.1 (b), it mentions later. As long as a predetermined number of the pressing pads 9 can be arranged, the position is not limited to this position.

  Further, the cell 110 may be provided with various resistance patterns such as a daisy chain, a via chain, a spelled pattern, and a comb tooth pattern (not shown) as a TEG (test element group).

  As shown in FIGS. 2 and 3, the resistance evaluation structure 10 includes a pair of wirings (here, the first wiring 3 and the first wirings) disposed on the substrate 1 with the low-k insulating film 2 facing each other. 2 wiring 4) and one wiring (hereinafter referred to as the first wiring 3) of the pair of wirings via vias (hereinafter referred to as the first via 5), and disposed in the uppermost layer. A connection pad (hereinafter referred to as a first connection pad 6) and a via (hereinafter referred to as a second via 7) to another wiring (hereinafter referred to as a second wiring 4) of the pair of wirings. Of the first wiring 3 and the second wiring 4 in the direction perpendicular to the substrate 1, and the connection pads (hereinafter referred to as the second connection pads 8) disposed on the uppermost layer. A plurality of planar terminals are arranged in an electrically floating state on the top layer through an insulating film (here, low-k insulating film 2), overlapping with a part. Is, a, a pressing pad 9 which is pressed with a predetermined load.

As the substrate 1, a general Si substrate (silicon wafer) is used as a semiconductor wafer.
The low-k insulating film 2 is disposed in a plurality of layers corresponding to the internal wiring of the cell 110. In FIG. 2B, the first low-k insulating film serving as a base film of the first wiring 3 is used. The film 2 a, the second low-k insulating film 2 b serving as a base film for the second wiring 4, and the third low-k insulating film 2 c serving as a protective film for the second wiring 4 are provided.

In addition, since the tolerance evaluation structure 10 according to the present embodiment is a structure for measuring the capacitance between the first wiring 3 and the second wiring 4, the first wiring 3 and the second wiring. For example, a low-k insulating film 2 may be used in at least one layer positioned lower than the fourth low-k insulating film 2. For example, instead of the third low-k insulating film 2 c, a general SiO ₂ film as an insulating film may be used. A SiO film, a SiN film, a SiCN film, or the like may be used.

As shown in FIG. 2, the first wiring 3 is a metal wiring (here, a copper wiring) disposed in parallel and linearly with respect to the second wiring 4.
The first wiring 3 is formed by forming a wiring groove in the first low-k insulating film 2a which is a base by a damascene method and embedding a wiring material (here, copper).

  In the damascene method, after a wiring groove pattern is formed in advance in a base insulating film (here, low-k insulating film 2), a metal thin film (here, copper thin film) is formed on the entire surface. Then, it is a wiring formation method in which metal wiring (here, copper wiring) embedded in the groove portion is polished by CMP (chemical mechanical polish) from above.

  This damascene method has an advantage that the step of the wiring is eliminated and the surface can be flattened, and that the metal wiring is completely embedded in the insulating film, so that highly reliable wiring can be easily realized. In addition, the damascene method is effective in realizing copper wiring having superior resistance value and reliability than aluminum wiring.

  Similarly to the first wiring 3, the second wiring 4 is formed by forming a wiring groove in the second low-k insulating film 2 b which is a base by a damascene method, and using a wiring material (here, copper). It is a metal wiring (in this case, a copper wiring) that is embedded and arranged in parallel and linearly with respect to the first wiring 3.

  The first wiring 3 and the second wiring 4 according to the present embodiment use Cu (copper) as a wiring material, but is not limited to a copper wiring and is a general wiring material. Al (aluminum), Ni (nickel), W (tungsten), Ag (silver), Au (gold), or the like may be used. Further, the first wiring 3 and the second wiring 4 may be formed using different wiring materials.

The wiring formation method of the first wiring 3 and the second wiring 4 is not limited to the damascene method, and may be formed by an etching method.
Further, the first wiring 3 and the second wiring 4 according to the present embodiment are arranged as separate layers (first metal layer and second metal layer) as shown in FIGS. However, the first wiring 3 and the second wiring 4 may be arranged in the same layer. For example, as shown in FIGS. 4 and 5, the first wiring 3 and the second wiring 4 are connected to the first wiring 3. By disposing as one metal layer, the number of wafer processing steps can be reduced, and the manufacturing cost of the tolerance evaluation wafer 100 can be reduced.

  In addition, the first wiring 3 and the second wiring 4 according to the present embodiment are arranged in parallel and linear to each other as shown in FIGS. 2 to 5, for example, FIG. 6 and FIG. 7. As shown in FIG. 5, the first wiring 3 and the second wiring 4 may be comb-shaped, and may be arranged to be engaged with each other without contacting each other. Thereby, the area where the 1st wiring 3 and the 2nd wiring 4 mutually oppose can be enlarged, and the electrostatic capacitance between the 1st wiring 3 and the 2nd wiring 4 can be earned.

  In addition, the first wiring 3 and the second wiring 4 according to the present embodiment are arranged without overlapping in the direction perpendicular to the substrate 1 as shown in FIGS. 8 and 9, they may be arranged so as to overlap each other in a direction perpendicular to the substrate 1, respectively.

  As described above, for the first wiring 3 and the second wiring 4, various wiring materials, wiring formation methods, and laminated structures can be considered, but wiring materials used in actual products of semiconductor chips (here, In addition to being able to evaluate the pressure resistance of the low-k insulating film 2 in a multilayer structure close to an actual product, it is possible to evaluate the existing wafer by using a damascene method with a multilayer structure (in this case, a separate layer). Since a processing process (pre-process) can be utilized, it is preferable.

  As shown in FIG. 2A, the first connection pad 6, the second connection pad 8, and the pressure pad 9 are formed by etching after forming a metal thin film (here, an aluminum thin film) by photolithography. It is formed in a substantially rectangular shape.

The first connection pad 6, the second connection pad 8, and the pressure pad 9 can be formed in a lump in a wafer processing step (previous step) for forming the pad 111 of the cell 110. This is preferable because the manufacturing cost of the tolerance evaluation wafer 100 can be reduced without increasing the resistance.
In particular, the first wiring 3 and the second wiring 4 may be extended to just below the pad 111 of the cell 110, respectively, and the pad 111 may be substituted for the first connection pad 6 and the second connection pad 8. .

  Further, in the tolerance evaluation structure 10 according to the present embodiment, as shown in FIGS. 2 to 9, the first connection pad 6 is disposed on one end side of the first wiring 3 and the second wiring 4. The two connection pads 8 are arranged on the other end side of the first wiring 3 and the second wiring 4, but as shown in FIG. 10, the first connection pad 6 and the second connection pad 8 may be arranged on one end side of the first wiring 3 and the second wiring 4.

The pressing pad 9 is preferably set to have a planar size and number in consideration of the measurement resolution (about 2 pF) of a measuring device that measures the capacitance between the first wiring 3 and the second wiring 4.
That is, for example, if the pressing pad 9 is a rectangular shape of 40 μm square of 0.108 pF so that the capacitance between the first wiring 3 and the second wiring 4 is 10 pF, 93 pressing pads 9 are arranged in parallel. In the case of a 120 μm square rectangular shape of 0.224 pF, 45 pieces are arranged side by side. In addition, the space | interval of the adjacent press pad 9 is arbitrarily set so that it can respond to arrangement | positioning of the various probe needles of the automatic test | inspection apparatus mentioned later.

  In addition, as shown in FIGS. 2 to 10, the pressing pad 9 according to the present embodiment is superimposed on a part of the first wiring 3 and the second wiring 4 when perspectively projected in the vertical direction with respect to the substrate 1. However, the position is not limited to this position as long as an external force can be applied between the first wiring 3 and the second wiring 4.

  For example, as shown in FIG. 11A, it may be superimposed on either the first wiring 3 or the second wiring 4, or as shown in FIG. And between the second wirings 4. In particular, as shown in FIG. 11 (a), in the case of overlapping with either the first wiring 3 or the second wiring 4, it is considered that the bonding load acts on the center portion of the bonding pad. The pressing pad 9 is preferably disposed so that the center of the pressing pad 9 is between the first wiring 3 and the second wiring 4.

  The first via 5 is a connection line for connecting the first wiring 3 and the first connection pad 6. In FIGS. 2 and 3, the second wiring 4 is formed by a dual damascene method. Via hole portion 5a and relay portion 5b formed by embedding copper of the copper thin film for the purpose, and via hole formed by embedding aluminum of the aluminum thin film for forming the first connection pad 6 by the etching method It is comprised with the part 5c.

  The second via 7 is a connection line for connecting the second wiring 4 and the second connection pad 8. In FIG. 2, aluminum for forming the second connection pad 8 by etching is used. It is formed by embedding a thin film of aluminum.

Next, a method for evaluating the pressure resistance of the low-k insulating film 2 will be described.
First, in the tolerance evaluation wafer 100, a probe of a measuring device (not shown) is brought into contact with the first connection pad 6 and the second connection pad 8, and the pair of the first wiring 3 and the second wiring 4 are paired. The capacitance is measured (first step S1). As a measuring device, an existing measuring device such as a Q meter, an LCR meter, or an impedance analyzer is used.

The tolerance evaluation wafer 100 is put into an automatic test equipment (ATE) (not shown) that tests the semiconductor and electronic component mounting boards.
The automatic inspection apparatus applies a probe load to the pressure pad 9 by performing an operation for an electrical test of the cell 110 by applying a probe needle to the pressure pad 9 of the cell 110 of the wafer for durability evaluation 100. (Second Step S2).

Further, the resistance evaluation wafer 100 has a first wiring 3 and a second wiring 4 which are paired by contacting the first connection pad 6 and the second connection pad 8 with the probe of the automatic inspection device or the measurement device. The capacitance between them is measured (third step S3).
And the measured value of the capacitance before the probe load is applied to the pressing pad 9 of the wafer 100 for durability evaluation, and the measurement of the capacitance after the probe load is applied to the pressing pad 9 of the wafer 100 for durability evaluation The values are compared (fourth step S4).

  Here, before and after the probe load is applied, if the capacitance is equal to the measured value, the low-k insulating film 2 of the wafer for durability evaluation 100 is not deformed in the laminated structure such as destruction or peeling. Then, it is determined that the probe load by the automatic inspection apparatus is durable (fifth step S5a).

  On the other hand, if the measured capacitance values are different before and after the probe load is applied, the low-k insulating film 2 of the wafer for durability evaluation 100 is deformed in the laminated structure such as destruction or peeling. Then, it is determined that there is no durability against the probe load by the automatic inspection device (fifth step S5b).

  As described above, by comparing the measured capacitance values between the first wiring 3 and the second wiring 4 that make a pair before and after the probe load is applied to the pressing pad 9 of the wafer 100 for durability evaluation. The durability of the low-k insulating film 2 can be accurately evaluated in a short time with respect to the probe load by the automatic inspection apparatus.

  The third step S3 described above is performed between the first wiring 3 and the second wiring 4 that form a pair in a state where a probe load is applied to the pressing pad 9 of the wafer for durability evaluation 100 in the second step S2. In this step, the state of the low-k insulating film 2 with the probe load applied (presence or absence of deformation of the laminated structure) may be evaluated.

  Further, in the evaluation method according to the present embodiment, in the above-described second step S2, the resistance evaluation wafer 100 is loaded into the automatic inspection apparatus, and the low-k insulating film 2 against the probe load by the probe needle of this automatic inspection apparatus. However, a predetermined load may be applied to the pressing pad 9 by using any pressing tool without using an automatic inspection device.

  In this case, the load on the pressing pad 9 is changed stepwise, and the capacitance between the first wiring 3 and the second wiring 4 in each step is measured. Then, by detecting a stage that has changed from a certain measured value of capacitance among the measured values of capacitance at each stage, the magnitude of the load in the previous stage of the corresponding stage is determined as the low-k insulating film 2. It can be evaluated as a withstand pressure.

  In the evaluation method according to the present embodiment, a probe load is simultaneously applied to the plurality of pressing pads 9 or a probe load is sequentially applied to each pressing pad 9 in the plurality of pressing pads 9. Alternatively, it may be possible to apply a probe load to the same pressing pad 9 a plurality of times.

When a probe load is sequentially applied to each of the plurality of pressing pads 9, the influence of the low-k insulating film 2 due to the difference in the position in the cell 110 of the durability evaluation wafer 100 is evaluated. can do.
In addition, when a probe load is applied to the same pressing pad 9 a plurality of times, the influence of the low-k insulating film 2 due to the number of times the probe needle is brought into contact can be evaluated.

In the above description, the resistance evaluation wafer 100 is evaluated for the pressure resistance of the low-k insulating film 2 due to the probe load, but the resistance evaluation wafer 100 is divided into individual pieces by dicing. The pressure resistance of the low-k insulating film 2 due to the bonding load may be evaluated for one resistance evaluation chip 110a formed as described above.
In this case, in the method for evaluating the pressure resistance of the low-k insulating film 2, the resistance evaluation wafer 100 and the cell 110 are replaced with the resistance evaluation chip 110a, and the probe load is replaced with the bonding load.
In particular, in the above-described second step S2, the automatic inspection apparatus is read as a bonding apparatus.
That is, the tolerance evaluation chip 110a is put into a bonding apparatus (not shown).

  Then, the bonding apparatus applies a bonding load to the pressure pad 9 by pressing the pressure pad 9 and the bonding wire of the resistance evaluation chip 110a to each other and applying heat and / or ultrasonic vibration to bond the pressure pad 9 to the pressure pad 9 ( Second step S2).

  In the above description, the case of evaluating the pressure resistance of the low-k insulating film 2 by the probe load or the bonding load has been described. However, the case of evaluating the resistance of the wafer 100 for resistance evaluation by backside polishing (back grinding). It can also be applied to. In this case, it is not necessary to apply a load to the pressing pad 9, and the capacitance between the first wiring 3 and the second wiring 4 is measured before and after the backgrinding process, and the static electricity before and after the backgrinding process is measured. By comparing the measured capacitance values, the resistance of the resistance evaluation wafer 100 can be evaluated.

  In addition, when the resistance evaluation chip 110a is transferred by the chip mounter, that is, when the resistance evaluation chip 110a is individually separated and adsorbed from the diced resistance evaluation wafer 100, the resistance evaluation chip 110a is transferred. The present invention can also be applied to evaluating the resistance of the chip 110a for resistance evaluation by pushing up a tip (needle) that pushes a needle-like pin (needle) from the back side.

  Further, the resistance evaluation chip 110a during the transfer of the resistance evaluation chip 110a from the resistance evaluation wafer 100 to the bonding position of the package or when the resistance evaluation chip 110a is mounted (chip mounted) at the bonding position of the package. The present invention can also be applied to the case where the resistance of the tip for resistance evaluation 110a by the transfer collet that is the suction holding tool is evaluated. In particular, it is possible to evaluate the degree of damage of the resistance evaluation chip 110a due to the difference in the shape of the transfer collet.

  In the resistance evaluation structure according to the present embodiment, the resistance of the resistance evaluation wafer 100 or the resistance evaluation chip 110a is evaluated by measuring the capacitance between the first wiring 3 and the second wiring 4. However, it is also conceivable to evaluate the resistance of the resistance evaluation wafer 100 or the resistance evaluation chip 110a by measuring the insulation resistance between the first wiring 3 and the second wiring 4. That is, when the low-k insulating film 2 of the resistance evaluation wafer 100 or the resistance evaluation chip 110a is deformed in a laminated structure such as breakage or peeling, the first wiring 3 and the second wiring 4 are separated. This also means that a capacitor that is a capacitance is destroyed, and a leakage current is generated, so that the insulation resistance can also be measured.

(A) is a top view which shows schematic structure of the wafer for tolerance evaluation which concerns on 1st Embodiment, (b) is the elements on larger scale which expanded one cell in the wafer for tolerance evaluation shown to Fig.1 (a). . (A) is a top view which shows schematic structure of the tolerance evaluation structure arrange | positioned at the cell shown in FIG.1 (b), (b) is the arrow AA line of the tolerance evaluation structure shown to Fig.2 (a). It is sectional drawing. (A) is an end view of the arrow BB line of the tolerance evaluation structure shown in FIG. 2 (a), and (b) is an end view of the arrow CC line of the tolerance evaluation structure shown in FIG. 2 (a). is there. (A) is a top view which shows schematic structure of the other tolerance evaluation structure arrange | positioned at the cell shown in FIG.1 (b), (b) is arrow view DD of the tolerance evaluation structure shown to Fig.4 (a). It is sectional drawing of a line. 4A is an end view of the resistance evaluation structure shown in FIG. 4A, taken along the line EE, and FIG. 4B is an end view of the resistance evaluation structure shown in FIG. is there. (A) is a top view which shows schematic structure of the further another tolerance evaluation structure arrange | positioned at the cell shown in FIG.1 (b), (b) is the arrow G- of the tolerance evaluation structure shown to Fig.6 (a). It is sectional drawing of a G line. (A) is an end view of an arrow H-H line of the resistance evaluation structure shown in FIG. 6 (a), and (b) is an end view of an arrow II line of the resistance evaluation structure shown in FIG. 6 (a). is there. (A) is a top view which shows schematic structure of the other tolerance evaluation structure arrange | positioned at the cell shown in FIG.1 (b), (b) is arrow JJ of the tolerance evaluation structure shown to Fig.8 (a). It is sectional drawing of a line. FIG. 8A is an end view of the resistance evaluation structure shown in FIG. 8A taken along the line KK, and FIG. 8B is an end view of the resistance evaluation structure shown in FIG. 8A taken along the line LL. is there. (A) is a top view which shows schematic structure of the other tolerance evaluation structure arrange | positioned at the cell shown in FIG.1 (b), (b) is still another arrange | positioned at the cell shown in FIG.1 (b). It is a top view which shows schematic structure of tolerance evaluation structure. (A) is a top view which shows schematic structure of the other tolerance evaluation structure arrange | positioned at the cell shown in FIG.1 (b), (b) is still another arrange | positioned at the cell shown in FIG.1 (b). It is a top view which shows schematic structure of tolerance evaluation structure.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate 2 Low-k insulating film 2a 1st low-k insulating film 2b 2nd low-k insulating film 2c 3rd low-k insulating film 3 1st wiring 4 2nd wiring 5 1st via | veer 5a Via hole portion 5b Relay portion 5c Via hole portion 6 First connection pad 7 Second via 8 Second connection pad 8 Second connection pad 9 Press pad 10 Resistance evaluation structure 100 Resistance evaluation wafer 110 Cell 110a For resistance evaluation Chip 111 pad

Claims (6)

A pair of wirings arranged opposite to each other with a low-k insulating film on the substrate;
A first connection pad connected to one wiring of the pair of wirings via a via and disposed on the uppermost layer;
A second connection pad that is connected to the other wiring of the pair of wirings via a via and disposed on the uppermost layer;
Are several arranged in a plane terminal in the uppermost layer, a pressure pad that is pressed with a predetermined load,
With
The pressing pad and the pair of wirings are in an electrically floating state through an insulating film, and when projected in a perpendicular direction with respect to the substrate, the one wiring and / or a part of the other wiring is formed. The pressing pad is disposed so as to be superimposed or disposed between the one wiring and the other wiring ,
For each of the plurality of pressing pads, a plurality of capacitances formed by the pressing pad, the pair of wirings, and the insulating film are connected in parallel.
A resistance evaluation wafer , wherein a pressure resistance of the low-k insulating film is evaluated based on a change in each of the plurality of capacitances and / or a combined capacitance . In the tolerance evaluation wafer according to claim 1,
The wafer for durability evaluation, wherein the first connection pad, the second connection pad, and the pressing pad are collectively formed by patterning a conductive thin film in the same layer. In the tolerance evaluation method using the tolerance evaluation wafer according to claim 1 or 2,
A first step of measuring a capacitance between the one wiring and the other wiring by bringing a probe of a measuring device into contact with the first connection pad and the second connection pad, respectively;
A second step of applying a predetermined load from the outside to the pressing pad after the first step;
During or after the second step, the probe of the measuring device is brought into contact with the first connection pad and the second connection pad, respectively, and the capacitance between the one wiring and the other wiring is determined. A third step of measuring;
A fourth step of comparing the measured capacitance value obtained in the first step with the measured capacitance value obtained in the third step;
The tolerance evaluation method characterized by comprising. In the tolerance evaluation method according to claim 3,
The tolerance evaluation method, wherein the third step is performed in a state where an external force is applied in the second step. In the tolerance evaluation method according to claim 3 or 4,
The second step is performed by gradually changing the load on the pressing pad,
The tolerance evaluation method, wherein the third step measures a capacitance between the one wiring and the other wiring in each stage. In the tolerance evaluation method according to any one of claims 3 to 5,
The tolerance evaluation method characterized by performing said 2nd step and 3rd step with respect to each press pad in said several press pad, respectively.

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