JP2006084191A - Semiconductor device and its inspection method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To inspect simply a failure generated on wiring and a connection part of a semiconductor device at the mounting time. <P>SOLUTION: An insulating film laminate 8 wherein the first insulating film 1 to the sixth insulating film 6 are laminated is formed on a substrate, and the first layer internal wire 21 comprising copper electrically insulated from the substrate is formed inside the second insulating film 2. On the surface of the insulating film laminate 8, a bonding pad 31 is formed just above the first layer internal wire 21, and a pair of probing pads 32 connected electrically to both ends of the first layer internal wire 21 is formed. After making wire bonding to the bonding pad 31, a probe is connected to the probing pads 32, and the conduction state of the first layer internal wire 21 is measured, to thereby enable easy inspection of a failure generated on the wiring or the like of the semiconductor device at the mounting time. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device for inspecting reliability at the time of mounting in a semiconductor device having an interlayer insulating film having a low dielectric constant, and an inspection method thereof.

In recent years, due to high performance of semiconductor devices and increase in storage capacity, the density, miniaturization, and multilayering of wirings are remarkable. Accordingly, in order to reduce the capacitance between the wirings, so-called Low-, which is an insulating film having a low dielectric constant, replaces silicon oxide (SiO ₂ : dielectric constant 4) which has been conventionally used for the insulating film between the wirings. k membranes have been used. As low-k films, organic polymers such as fluorine-added silica (SiOF), carbon-added silica (SiOC), or plasma-polymerized benzocyclobutene (BCB) are known.

  In addition, since vacuum shows the lowest dielectric constant, it is generally adopted and put into practical use to introduce pores of 10 nm or less into the insulating film for the purpose of reducing the dielectric constant of the insulating film. . Further, a structure in which an insulating film is not present between the wirings has been studied.

  The mechanical strength of the insulating film in which holes are present is much lower than that of the insulating film in which holes are not present. Therefore, when a semiconductor device is manufactured using an insulating film having voids as an interlayer insulating film or the like, the mechanical strength of the semiconductor device is very low.

  A mechanical shock is directly applied to a pad to which an input / output signal is applied from the outside to the semiconductor device when a wire bonding or a solder bump is mounted. For this reason, in the case of a semiconductor device using an interlayer insulating film in which a hole with low mechanical strength exists, the portion directly under the pad is destroyed by a mechanical shock, and the wiring is disconnected or short-circuited with other wiring. In addition, there is a very high risk that defects will occur in the semiconductor device.

Such defects also occur in conventional interlayer insulating films using SiO ₂ or the like, and in order to solve this, studies such as devising a mounting method such as wire bonding and a pad structure have been made. .

  For example, in Patent Document 1, an insulating film is formed between wirings provided immediately under a pad to prevent a short circuit from occurring between a plurality of wirings provided immediately under the pad. Further, in Patent Document 2, an insulating film made of an elastic buffer material such as borophosphosilicate glass (BPSG) is formed between the wirings provided immediately below the pads, and a semiconductor device at the time of mounting such as bonding To prevent destruction.

  On the other hand, as inspection methods for inspecting defects at the time of mounting, a method of observing the number of occurrences of macroscopic mechanical destruction such as peeling or deformation of a pad with a microscope, a method of measuring bonding strength by pulling a wire, or a pad Destructive inspection such as a method of removing the respective layers formed in the lower part of the substrate sequentially from the upper part and searching for a defective portion is performed.

  However, these inspection methods are complicated, and when there are many inspection objects, the time required for the inspection becomes enormous. In addition, it may not be possible to determine whether a defect detected in the destructive inspection is a defect caused by an impact at the time of mounting or a defect generated when preparing a sample for inspection.

  Therefore, as a conventional example, an inspection method for electrically determining a defect as described below is shown (see Patent Document 3).

  FIG. 12 shows a semiconductor device used in a conventional inspection method. As shown in FIG. 12, a P-type semiconductor region 211 and an N-type semiconductor region 221 are formed on a semiconductor substrate 111 immediately below the bonding pad 131, and a PN junction is formed. A bias voltage application pad 132 is electrically connected to the P-type semiconductor region 211 and the N-type semiconductor region 221, and a predetermined reverse bias voltage is applied to the PN junction.

  On the other hand, when bonding, such as crystal dislocation, occurs in the PN junction region formed in the substrate immediately below the bonding pad, the crystal dislocation distorts the crystal structure and creates a level in the band gap. . When this level is present in the depletion layer, they act as a carrier recombination center, and a carrier recombination current is observed in the reverse characteristics of the PN junction. Therefore, a leak current is generated by the reverse bias voltage applied to the PN junction. By detecting this leakage current, it is possible to non-destructively inspect the damage that occurs in the semiconductor device during bonding.

  However, in the conventional inspection method, damage that affects the semiconductor substrate 111 can be detected, but damage that does not affect the semiconductor substrate 111 cannot be detected. For example, in a semiconductor device having a multilayer wiring structure in which a plurality of interlayer insulating films using low-k films are provided and wiring is formed in each interlayer insulating film, bonding formed above the multilayer wiring structure It has been reported that when bonding is performed to a pad for use, the peeling of the wiring occurs at the interface between the interlayer insulating film and the wiring (see, for example, Non-Patent Document 1). Such peeling of the wiring causes disconnection of the wiring and a short circuit between the wirings, leading to destruction of the semiconductor device. However, it is impossible to detect such a failure factor that does not damage the semiconductor substrate by a conventional inspection method. In addition, in a multilayer wiring structure, it cannot be specified which layer has a defect. Furthermore, it is not possible to specify a disconnection in a connection portion such as a via that connects the wirings.

Therefore, in particular, in a semiconductor device having a multilayer wiring structure using a low-k film as an interlayer insulating film, as described above, in order to evaluate damage caused to the semiconductor device when a mechanical shock such as bonding is applied to the pad. Destructive inspection is necessary. However, the destructive inspection has a complicated inspection method and it is difficult to perform a sufficient number of inspections. For this reason, damage is evaluated by inspecting at most about several tens of pads.
JP-A-8-236706 Japanese Patent Laid-Open No. 2003-100756 JP 2000-269281 A M. Inohara et al., “High Performance Copper and Low-k Interconnect Technology Fully Compatible to 90nm-node SOC application (CMOS4)”, International ELECTRON DEVICES meeting 2002 Technical Digest, USA, IEEE, 2002, p. 77-80

  However, since there are thousands of pads for a semiconductor device per chip, the optimum bonding method and the structure of pads and pads are selected based on the result of destructive inspection of several tens of pads. There is a problem that it is very difficult to do.

  In order to solve the above-described conventional problems, an object of the present invention is to make it possible to easily inspect defects that occur during mounting on wiring and connection portions of a semiconductor device.

  In order to achieve the above object, the present invention provides a semiconductor device comprising a test pattern, a bonding pad, and a probing pad connected to the test pattern, whereby the semiconductor device is subjected to mechanical shock. The defects occurring in the above are electrically detected using a probe connected to the probing pad.

  Specifically, a semiconductor device according to the present invention is directed to a semiconductor device that is inspected for resistance to mechanical shock during mounting of the semiconductor device, and includes a substrate and a plurality of insulating films stacked on the substrate. A film stack, at least one test pattern made of a conductor that is electrically insulated from the substrate and embedded in the insulating film stack, and a mechanical impact on the test pattern formed on the insulating film stack A bonding pad for performing wire bonding, and a probing pad formed on the insulating film laminate and electrically connected to the inspection pattern.

  According to the semiconductor device of the present invention, the bonding pad is formed on the insulating film stack, and the inspection pattern is embedded in the insulating film stack, so that bonding is performed on the bonding pad. Thus, a mechanical impact can be applied to the inspection pattern. If the inspection pattern provided on the lower side of the bonding pad is damaged by this mechanical impact, disconnection occurs in the inspection pattern, and if there are multiple inspection patterns, the inspection pattern A short circuit occurs between them. The disconnection in the inspection pattern and the short circuit between the inspection patterns can be electrically detected by applying an electrical signal to the inspection pattern using a probe electrically connected to the probing pad. Therefore, it is possible to evaluate the damage caused to the inspection pattern without performing destructive inspection such as cross-sectional analysis. As a result, it is possible to easily evaluate many pad structures and wire bond conditions. It becomes. Further, since the inspection pattern is insulated from the substrate, when an element such as a transistor is formed on the substrate, it is generated in the inspection pattern provided on the lower side of the bonding pad so as to be separated from the defect generated in the transistor. It is possible to evaluate damaged damage.

  The semiconductor device of the present invention preferably further includes a probing-dedicated pad formed on the insulating film stack, formed on the insulating film stack, and electrically connected to the probing pad. With such a configuration, even when the probing pad is damaged, the damage of the inspection pattern can be evaluated without an inspection error.

  In the semiconductor device of the present invention, it is preferable that there are a plurality of probing pads. With such a configuration, the inspection pattern can be reliably evaluated.

  In the semiconductor device of the present invention, it is preferable that the inspection pattern is composed of an intra-layer wiring provided on at least one of the plurality of insulating films. In addition, the intra-layer wiring includes a plurality, and is preferably provided so as to be insulated from each other by any one of the plurality of insulating films, and may be provided in different insulating films of the plurality of insulating films. With such a configuration, damage caused to the semiconductor device can be reliably evaluated.

  In the semiconductor device of the present invention, the inspection pattern is provided with a plurality of first in-layer partial wirings provided in any one of the plurality of insulating films, and a first in-layer partial wiring among the plurality of insulating films. A plurality of second layer partial wirings provided on the insulating film excluding the insulating film, and the inspection pattern includes a plurality of first layer partial wirings and a plurality of second layer partial wirings. Preferably, the via chain is alternately and electrically connected in series with each other via. By adopting such a configuration, it is possible to reliably detect damage occurring in the vias connecting the partial wirings.

  Further, it is preferable that the via chain includes a plurality of via chains which are insulated from each other by different insulating films. Thereby, it is possible to reliably detect damage caused in any of the plurality of vias provided.

  In the semiconductor device of the present invention, the bonding pad is preferably formed in a region above the inspection pattern on the insulating film laminate. As a result, it is possible to evaluate the damage that the mechanical impact applied to the bonding pad exerts on the inspection pattern provided immediately below the bonding pad.

  The bonding pad is preferably formed above the periphery of the inspection pattern on the insulating film stack. By adopting such a configuration, it is possible to evaluate the damage that the mechanical impact applied to the bonding pad exerts on the inspection pattern provided around the bonding pad.

  In the semiconductor device of the present invention, the inspection pattern is formed below the bonding pad, and electrically connects the plurality of intra-layer wirings provided on at least two of the plurality of insulating films and the plurality of intra-layer wirings. It is preferable that the via is connected to the stacked via. With such a configuration, it is possible to easily evaluate damage generated in the stacked via formed below the bonding pad without performing a destructive inspection. This makes it possible to easily evaluate the correlation between the increase / decrease in the number of connection parts per unit cross-sectional area or the increase / decrease in the wiring area and the frequency of disconnection or short-circuiting of the wiring and connection parts. It becomes possible.

  In this case, it is preferable that two or more probing pads are provided, and each probing pad is electrically connected to a different in-layer wiring. This makes it possible to specify which via of the plurality of vias has been damaged.

  The bonding pad is preferably electrically connected to the stack via and also serves as a probing pad. As a result, one probing pad can be omitted.

  The method for inspecting a semiconductor device according to the present invention includes a step of preparing the semiconductor device of the present invention, a step of applying a mechanical impact to the bonding pad, and an inspection pattern by applying an electrical signal to the probing pad. Damage caused to the inspection pattern by electrically connecting the probe for inspecting the continuity state to the probing pad and electrically inspecting the continuity state of the inspection pattern using the probe connected to the probing pad And a step of evaluating.

  In addition, even if the process of evaluating the damage caused to the inspection pattern is a process of inspecting the presence or absence of the disconnection in the inspection pattern by the probe, the process of evaluating the inspection pattern is performed by the probe of the short circuit between the inspection patterns. It may be a step of inspecting presence / absence.

  Furthermore, it is preferable that the step of applying a mechanical impact to the bonding pad is a step of wire bonding to the bonding pad.

  According to the semiconductor device and the inspection method thereof according to the present invention, a defect such as a disconnection or a short circuit generated in a connection portion such as a wiring or a via of the semiconductor device due to a mechanical shock during mounting can be easily performed by a non-destructive method. Can be inspected.

(First embodiment)
Hereinafter, a semiconductor device and an inspection method thereof according to the first embodiment of the present invention will be described in detail with reference to FIG.

  FIG. 1A shows a planar configuration of the semiconductor device of this embodiment, and FIG. 1B shows a cross-sectional structure taken along line Ib-Ib in FIG.

As shown in FIGS. 1A and 1B, a first film made of silicon oxide (SiO ₂ ) having a thickness of 0.25 μm is formed on a substrate (not shown) made of silicon (Si). Insulating film 1, second insulating film 2, third insulating film 3, fourth insulating film 4 and fifth insulating film 5 made of polyallyl ether each having a thickness of 0.60 μm and a thickness of 1. A sixth insulating film 6 made of SiO _{2 having a} thickness of 0 μm is sequentially laminated to form an insulating film stacked body 8. Between the first insulating film 1 and the second insulating film 2, between the second insulating film 2 and the third insulating film 3, and between the third insulating film 3 and the fourth insulating film 4. And between the fourth insulating film 4 and the fifth insulating film 5, a first barrier layer 11 made of carbon-doped silicon nitride (SiCN) having a thickness of 0.05 μm, a second barrier layer 12, A third barrier layer 13 and a fourth barrier layer 14 are formed. Between the fifth insulating film 5 and the sixth insulating film 6, a first layer made of silicon nitride (SiN) having a thickness of 0.10 μm is formed. 5 barrier layers 15 are formed.

  A first in-layer wiring 21 (width = about 0.14 μm, thickness = 250 nm) made of copper (Cu) electrically insulated from the substrate is embedded as an inspection pattern in the second insulating film 2. A bonding pad 31 made of aluminum (Al) (a square shape with a side of 80 μm, thickness = 500 nm) is formed on the surface of the insulating film laminate 8 above the first intra-layer wiring 21. ing. Further, a pair of first probing pads 32 (a square shape with a side of 80 μm, thickness = 500 nm) each made of Al are provided at both ends of the first in-layer wiring 21, and stacked vias 9 made of Cu and It is electrically connected via a connection portion 51 made of Al.

  A seventh insulating film 19 made of SiN having a thickness of 1.00 μm is formed on the sixth insulating film 6, the bonding pad 31, and the first probing pad 32. Further, an eighth insulating film 40 made of polyimide having a thickness of 2.00 μm is formed on the seventh insulating film 19.

  Next, a semiconductor device inspection method using the semiconductor device of this embodiment will be described.

  By performing wire bonding on the bonding pad 31, a vertical mechanical impact is applied to the semiconductor device. When damage such as vertical or horizontal deformation or destruction occurs in the insulating film laminate 8 and the first in-layer wiring 21 formed below the bonding pad 31 due to this mechanical impact, The first intra-layer wiring 21 is disconnected. The disconnection generated in the first intra-layer wiring 21 can be easily detected by evaluating the conduction state between the first probing pads 32 with a probe.

The probe may be any probe that can apply a voltage of 3V to 8V and detect a current lower limit of 1 × 10 ⁻⁷ A to 1 × 10 ⁻⁸ A in order to detect a short circuit of the inspection pattern. . Further, in order to detect the degree of conduction by measuring the resistance of the inspection pattern, it is preferable to use one that can be measured by passing a current of about 0.1 mA to 1 mA.

  As described above, by using the semiconductor device and the inspection method thereof according to the present embodiment, the state of the insulating film stack 8 and the first in-layer wiring 21 after an impact such as wire bonding is applied. Evaluation can be performed without performing destructive inspection such as cross-sectional analysis. Therefore, it is possible to easily perform many evaluations on the pad structure of the semiconductor device, the wire bonding conditions, and the like.

  Further, since the first intra-layer wiring 21 is insulated from the substrate, it is formed below the bonding pad 31 so as to be separated from the defect generated in the transistor when an element such as a transistor is formed on the substrate. It is possible to evaluate the damage generated in the insulating film laminate 8 and the first in-layer wiring 21.

  In the present embodiment, the first intra-layer wiring 21 is formed in the second insulating film 2, but may be provided in the other insulating film.

(First modification of the first embodiment)
A semiconductor device and an inspection method thereof according to a first modification of the first embodiment of the present invention will be described below with reference to FIG. In FIG. 2, the same components as those shown in FIG.

  FIG. 2A shows a planar configuration of the semiconductor device according to this modification, and FIG. 2B shows a cross-sectional structure taken along line IIb-IIb in FIG. 2A. FIG. 2 shows a cross-sectional structure taken along line IIc-IIc in FIG. Hereinafter, differences of the semiconductor device of this modification from the semiconductor device of the first embodiment will be described.

  In the present modification, unlike the first embodiment, the second in-layer wiring 22 and the first in-layer wiring 21 are provided in the second insulating film 2 below the bonding pad 31 in parallel with the first in-layer wiring 21. A third intra-phase wiring 23 is embedded. The first in-layer wiring 21 and the second in-layer wiring 22, and the first in-layer wiring 21 and the third in-layer wiring 23 are formed with an interval of about 0.14 μm, respectively. The first in-layer wiring 21 to the third in-layer wiring 23 are arranged in parallel in the horizontal plane of the second insulating film 2 and are electrically insulated from each other. The first in-layer wiring 21 to the third in-layer wiring 23 are electrically insulated from the substrate.

  A pair of second probing pads 33 made of Al are connected to both ends of the second layer wiring 22 and the third layer wiring 23 through a stack via 9 made of Cu and a connecting portion 51 made of Al, respectively. And a pair of third probing pads 34 are electrically connected.

  Next, a semiconductor device inspection method using the semiconductor device of this embodiment will be described.

  By performing wire bonding on the bonding pad 31, a vertical mechanical impact is applied to the semiconductor device. Due to this mechanical shock, the insulating film laminate 8 formed below the bonding pad 31 and the first in-layer wiring 21 to the third in-layer wiring 23 are deformed or broken vertically or horizontally. When damage occurs, a disconnection or a short circuit occurs from the first intra-layer wiring 21 to the third intra-layer wiring 23. The disconnection or short circuit generated from the first in-layer wiring 21 to the third in-layer wiring 23 is evaluated by the probe between the first probing pad 32 and the third probing pad 34. Can be easily detected.

  Specifically, the disconnection of the first in-layer wiring 21 indicates whether or not there is conduction between the first probing pads 32, and the disconnection of the second in-layer wiring 22 indicates conduction between the second probing pads 33. Whether or not the third in-layer wiring 23 is disconnected is evaluated based on the presence or absence of conduction between the third probing pads 34. In addition, the short circuit between the first in-layer wiring 21 and the second in-layer wiring 22 indicates whether there is conduction between the first probing pad 32 and the second probing pad 33, the first in-layer wiring. The short circuit between 21 and the third in-layer wiring 23 is evaluated by the presence / absence of conduction between the first probing pad 32 and the third probing pad 34.

  As described above, according to the semiconductor device and the inspection method thereof according to this modification, many evaluations can be easily performed without performing a destructive inspection such as a cross-sectional analysis on the structure of the pad of the semiconductor device and the wire bond condition. Can be performed. Further, since the first in-layer wiring 21 to the third in-layer wiring 23 are insulated from the substrate, when an element such as a transistor is formed on the substrate, it is separated from the defect generated in the transistor for bonding. It is possible to evaluate the damage caused to the third in-layer wiring 23 from the insulating film stack 8 and the first in-layer wiring 21 formed below the pad 31.

  In this modification, the first in-layer wiring 21 to the third in-layer wiring 23 are formed in the insulating film 2, but may be provided in the other insulating film.

  In this modification, three intra-layer wirings are provided. However, if there are two or more intra-layer wirings, both the disconnection in the wiring caused by the mechanical shock and the short circuit between the wirings can be similarly evaluated.

(Second modification of the first embodiment)
Hereinafter, a semiconductor device and an inspection method thereof according to a second modification of the first embodiment of the present invention will be described with reference to FIG. In FIG. 3, the same components as those shown in FIG.

  3A shows a planar configuration of a semiconductor device according to this modification, FIG. 3B shows a cross-sectional structure taken along line IIIb-IIIb in FIG. 3A, and FIG. 3C shows FIG. The cross-section in the IIIc-IIIc line of a) is shown. Hereinafter, differences of the semiconductor device of this modification from the semiconductor device of the first embodiment will be described.

  As shown in FIGS. 3A to 3C, the semiconductor device of the present modification is different from the semiconductor device of the first embodiment, in addition to the first in-layer wiring 21, the third insulating film. 3, the second intra-layer wiring 22 is embedded, and the fourth insulating film 4 is embedded in the third intra-layer wiring 23. The first in-layer wiring 21 to the third in-layer wiring 23 are aligned in parallel to the stacking direction of the second insulating film 2 to the fourth insulating film 4 and below the bonding pad 31, respectively. Are arranged as follows. Further, the first in-layer wiring 21 to the third in-layer wiring 23 are electrically insulated from each other and also electrically insulated from the substrate.

  A pair of second probing pads made of Al with a stack via 9 made of Cu and a connecting portion 51 made of Al interposed at both ends of the second in-layer wiring 22 and the third in-layer wiring 23, respectively. 33 and a pair of third probing pads 34 are electrically connected.

  Next, a method for inspecting a semiconductor device using the semiconductor device of this modification will be described.

  By performing wire bonding on the bonding pad 31, a vertical mechanical impact is applied to the semiconductor device. Due to this mechanical shock, the insulating film laminate 8 formed below the bonding pad 31 and the first in-layer wiring 21 to the third in-layer wiring 23 are deformed or broken vertically or horizontally. When damage occurs, a disconnection or a short circuit occurs from the first intra-layer wiring 21 to the third intra-layer wiring 23. The disconnection or short circuit generated from the first in-layer wiring 21 to the third in-layer wiring 23 is evaluated by the probe between the first probing pad 32 and the third probing pad 34. Can be easily detected.

  Specifically, the disconnection of the first in-layer wiring 21 indicates whether or not there is conduction between the first probing pads 32, and the disconnection of the second in-layer wiring 22 indicates conduction between the second probing pads 33. Whether or not the third in-layer wiring 23 is disconnected is evaluated based on the presence or absence of conduction between the third probing pads 34. Further, the short-circuit between the first in-layer wiring 21 and the second in-layer wiring 22 is caused by the presence or absence of conduction between the first probing pad 32 and the second probing pad 33, the second in-layer wiring. The short circuit between the wiring 22 and the third intra-layer wiring 23 is evaluated by the presence or absence of conduction between the second probing pad 33 and the third probing pad 34.

  As described above, according to the semiconductor device and the inspection method thereof according to this modification, many evaluations can be easily performed without performing a destructive inspection such as a cross-sectional analysis on the structure of the pad of the semiconductor device and the wire bond condition. Can be performed. Further, since the first in-layer wiring 21 to the third in-layer wiring 23 are insulated from the substrate, when an element such as a transistor is formed on the substrate, it is separated from the defect generated in the transistor for bonding. It is possible to evaluate the damage caused to the third in-layer wiring 23 from the insulating film stack 8 and the first in-layer wiring 21 formed below the pad 31.

  In the present modification, the first in-layer wiring 21 to the third in-layer wiring 23 are formed inside the second insulating film 2 to the fourth insulating film 4, respectively. It may be provided.

  In this modification, three intra-layer wirings are provided. However, if there are two or more intra-layer wirings, both the disconnection in the wiring caused by the mechanical shock and the short circuit between the wirings can be similarly evaluated.

(Second Embodiment)
Hereinafter, a semiconductor device and an inspection method thereof according to the second embodiment of the present invention will be described in detail with reference to FIG.

  4A shows a planar configuration of a semiconductor device according to the second embodiment of the present invention, FIG. 4B shows a cross-sectional structure taken along line IVb-IVb in FIG. 4A, and FIG. ) Shows a cross-sectional structure taken along line IVc-IVc in FIG.

  As shown in FIGS. 4A to 4C, a first insulating film 1 to a sixth insulating film 6 are stacked on an Si substrate (not shown), and an insulating film stack 8 Is formed. A plurality of first in-layer partial wirings 41 having a length of 1.0 μm are formed inside the second insulating film 2, and a length of 1.0 μm is formed inside the third insulating film 3. A plurality of second in-layer partial wirings 42 are formed.

  One end of the first in-layer partial wiring 41 and one end of the second in-layer partial wiring 42 are electrically connected alternately by vias 43 (diameter 0.14 μm) made of Cu. A first via chain 47 that is an inspection pattern connected in series is formed. A pair of first probing pads 32 are connected to both ends of the first via chain 47 with the stack via 9 and the connecting portion 51 interposed therebetween.

  With the configuration of the semiconductor device according to the present embodiment, a defect generated in at least one of the plurality of vias 43 can be detected. The first insulating film 1 to the sixth insulating film 6, the first barrier layer 11 to the fourth barrier layer 14, the fifth barrier layer 15, the seventh insulating film 19, and the eighth insulating film 40. Is the same configuration as in the first embodiment, and the first via chain 47 is insulated from the substrate.

  Next, a semiconductor device inspection method using the semiconductor device of this embodiment will be described.

  By performing wire bonding on the bonding pad 31, a vertical mechanical impact is applied to the semiconductor device. When damage such as deformation or destruction in the vertical direction or horizontal direction occurs in the insulating film laminate 8 and the first via chain 47 formed below the bonding pad 31 due to this mechanical impact, 1 via chain 47 breaks. The disconnection generated in the first via chain 47 can be easily detected by evaluating the conduction state between the first probing pads 32 with a probe.

  As described above, by using the semiconductor device and the inspection method thereof according to the present embodiment, the states of the insulating film stack 8 and the first via chain 47 after an impact such as wire bonding is applied are shown in cross section. Evaluation can be easily performed without performing destructive inspection such as analysis. In particular, in the present embodiment, it is possible to detect damage that has occurred in at least one of the vias 43 constituting the first via chain 47. Therefore, it is possible to easily perform many evaluations on the pad structure of the semiconductor device, the wire bonding conditions, and the like.

  In addition, since the first via chain 47 is insulated from the substrate, when an element such as a transistor is formed on the substrate, the insulation is formed below the bonding pad 31 so as to be separated from the defect generated in the transistor. It is possible to evaluate the damage that has occurred in the film stack 8 and the first via chain 47.

  In the present embodiment, the first via chain 47 is formed inside the second insulating film 2 and the third insulating film 3, but may be provided inside the other insulating film.

(One Modification of Second Embodiment)
A semiconductor device and an inspection method thereof according to a modification of the second embodiment of the present invention will be described below with reference to FIG. In FIG. 5, the same components as those shown in FIG. Hereinafter, differences of the semiconductor device of the present modification from the semiconductor device of the second embodiment will be described.

  FIG. 5A shows a planar configuration of a semiconductor device according to this modification, FIG. 5B shows a cross-sectional structure taken along line Vb-Vb in FIG. 5A, and FIG. 5C shows FIG. The cross-section in Vc-Vc of a) is shown.

  As shown in FIG. 5, in this modification, unlike the second embodiment, in addition to the first via chain 47 formed in the second insulating film 2 and the third insulating film 3, A second via chain 48 that is electrically insulated from the first via chain 47 is formed inside the fourth insulating film 4 and the fifth insulating film 5. A pair of second probing pads 33 are electrically connected to both ends of the second via chain 48 with the stack via 9 and the connecting portion 51 interposed therebetween. The first via chain 47 and the second via chain 48 are formed to be aligned vertically below the bonding pad 31. The first via chain 47 and the second via chain 48 are respectively It is electrically insulated from the substrate.

  Next, a method for inspecting a semiconductor device using the semiconductor device of this modification will be described.

  In this modification, a disconnection or the like that occurs in the second via chain 48 is measured by measuring the presence or absence of conduction between the second probing pads 33, thereby causing a disconnection that occurs in the first via chain 47. It can be evaluated independently from such defects.

  In this modification, the second via chain 48 is formed in the fourth insulating film 4 and the fifth insulating film 5, but in addition to the second insulating film 2 to the fifth insulating film 5, polyaryl ether is used. By stacking the insulating films to be formed, other insulating films may be formed. Three or more via chains may be provided.

(Third embodiment)
Hereinafter, a semiconductor device and an inspection method using the same according to the third embodiment of the present invention will be described in detail with reference to FIG.

  6A shows a planar configuration of a semiconductor device according to the second embodiment of the present invention, FIG. 6B shows a cross-sectional structure taken along line VIb-VIb in FIG. 6A, and FIG. ) Shows a cross-sectional structure taken along line VIc-VIc in FIG.

As shown in FIGS. 6A to 6C, a first insulating film 1 made of SiO ₂ having a thickness of 0.25 μm is formed on a substrate made of Si (not shown). The second insulating film 2, the third insulating film 3, the fourth insulating film 4 and the fifth insulating film 5 made of polyallyl ether having a thickness of 0.60 μm and the second insulating film made of SiO _{2 having a} thickness of 1.0 μm. 6 insulating films 6 are sequentially stacked to form an insulating film stack 8. Between the first insulating film 1 and the second insulating film 2, between the second insulating film 2 and the third insulating film 3, and between the third insulating film 3 and the fourth insulating film 4. And between the fourth insulating film 4 and the fifth insulating film 5, a first barrier layer 11 made of carbon-doped silicon nitride (SiCN) having a thickness of 0.05 μm, a second barrier layer 12, A third barrier layer 13 and a fourth barrier layer 14 are formed, and a fifth barrier layer made of SiN having a thickness of 0.10 μm is formed between the fifth insulating film 5 and the sixth insulating film 6. 15 is formed.

  Inside the second insulating film 2, a first intra-layer wiring 21 (width = about 0.14 μm, thickness = 250 nm) made of Cu is formed. Further, in the third insulating film 3 to the fifth insulating film 5, a second in-layer wiring 22 made of Cu having a side length of 1.0 μm and a thickness of 250 nm is formed. In-layer wiring 23 and fourth in-layer wiring 24 are formed.

  A probing pad 35 made of Al is electrically connected to one end of the first in-layer wiring 21 with a stack via 9 made of Cu and a connection portion 51 made of Al interposed. The other end of the first intra-layer wiring 21 and the second intra-layer wiring 22, the second intra-layer wiring 22, the third intra-layer wiring 23, and the third intra-layer wiring 23 and the intra-layer wiring 24, respectively. A first via 44, a second via 45, and a third via 46, each made of Cu having a diameter of 0.14 μm, are formed so as to be aligned in a straight line directly below the bonding pad 31. . The fourth intra-layer wiring 24 and the bonding pad 31 are electrically connected by a connection portion 54 made of Al, and a stack via 49 for electrically connecting the bonding pad 31 and the probing pad 35. Is formed.

  In the present embodiment, each of the first via 44 to the third via 46 that connects the first intra-layer interconnect 21 to the fourth intra-layer interconnect 24 is provided. A plurality of vias connected to each other may be provided.

  A seventh insulating film 19 made of SiN having a thickness of 1.00 μm is formed on the sixth insulating film 6, the bonding pad 31 and the probing pad 35. Further, an eighth insulating film 40 made of polyimide having a thickness of 2.00 μm is formed on the seventh insulating film 19.

  Next, a semiconductor device inspection method using the semiconductor device of this embodiment will be described.

  By performing wire bonding to the bonding pad 31, a vertical mechanical impact is applied to the semiconductor device. Due to this mechanical shock, the insulating film laminate 8 formed below the bonding pad 31, the first intra-layer wiring 21 to the fourth intra-layer wiring 24, and the first via 44 to the third via 46. When damage such as deformation or destruction in the vertical direction or horizontal direction occurs, defects such as disconnection from the first via 44 to the third via 46 occur. The defect generated from the first via 44 to the third via 46 can be evaluated by measuring the presence or absence of conduction between the bonding pad 31 and the probing pad 35 with a probe.

  Therefore, the correlation between the number or wiring area per unit cross-sectional area of each of the first via 44 to the third via 46 and the defect generated in the first via 44 to the third via 46 is easily evaluated. And the pad structure can be optimized. In addition, since the stack via 49 is insulated from the substrate, when an element such as a transistor is formed on the substrate, the insulating film stack formed under the bonding pad 31 is separated from the defect generated in the transistor. It is possible to evaluate the damage caused from the eighth via 1 and the first via 44 to the third via 46.

  In this embodiment, a stacked via composed of four layers of intra-layer wiring is formed. However, if a via stack is formed of two or more intra-layer wirings, the same evaluation can be performed.

  Further, although the in-layer wiring 24 is connected to the bonding pad 31, a probing pad connected to the in-layer wiring 24 may be provided separately from the bonding pad 31.

(One Modification of Third Embodiment)
A semiconductor device and an inspection method using the same according to a modification of the third embodiment of the present invention will be described below with reference to FIG. In FIG. 7, the same components as those shown in FIG. Hereinafter, differences of the semiconductor device of the present modification from the semiconductor device of the third embodiment will be described.

  7A shows a planar structure of the semiconductor device according to this modification, FIG. 7B shows a cross-sectional structure taken along line VIIb-VIIb in FIG. 7A, and FIG. 7C shows FIG. The cross-section in VIIc-VIIc of a) is shown. The semiconductor device shown in FIG. 7 is different from the semiconductor device shown in FIG. 6 in that one end of the third in-layer wiring 23 provided in the fourth insulating film 4 has a stack via 9 made of Cu. And a connection part 51 made of Al is electrically connected to the probing pad 36 made of Al.

  Next, a method for inspecting a semiconductor device using the semiconductor device of this modification will be described.

  In this modification, a defect of the third via 46 provided between the third in-layer wiring 23 and the fourth in-layer wiring 24 is caused by the first via provided in the other in-layer wiring. It can be inspected independently of the defect of the via 44 or the second via 45. As a specific example, when there is no conduction between the bonding pad 31 and the probing pad 35 and there is conduction between the probing pad 35 and the probing pad 36, the inside of the third layer It can be determined that the third via 46 provided between the wiring 23 and the fourth intra-layer wiring 24 is disconnected.

  Further, a probing pad connected to the second in-layer wiring 22 may be provided. In this case, detailed inspection for each via can be performed.

(Fourth embodiment)
Hereinafter, a semiconductor device and an inspection method using the same according to the fourth embodiment of the present invention will be described in detail with reference to FIGS.

  FIG. 8A shows a planar configuration of a semiconductor device according to the fourth embodiment of the present invention, and FIG. 8B is a cross-sectional view taken along line VIIIb-VIIIb in FIG.

As shown in FIGS. 8A to 8B, a first insulating film 1 made of SiO ₂ having a thickness of 0.25 μm is formed on a substrate made of Si (not shown). The second insulating film 2, the third insulating film 3, the fourth insulating film 4 and the fifth insulating film 5 made of polyallyl ether having a thickness of 0.60 μm and the second insulating film made of SiO _{2 having a} thickness of 1.0 μm. 6 insulating films 6 are sequentially stacked to form an insulating film stack 8. Between the first insulating film 1 and the second insulating film 2, between the second insulating film 2 and the third insulating film 3, and between the third insulating film 3 and the fourth insulating film 4. And between the fourth insulating film 4 and the fifth insulating film 5, a first barrier layer 11 made of carbon-doped silicon nitride (SiCN) having a thickness of 0.05 μm, a second barrier layer 12, A third barrier layer 13 and a fourth barrier layer 14 are formed, and a fifth barrier layer 15 made of SiN having a thickness of 0.10 μm is formed between the fifth insulating film 5 and the sixth insulating film 6. Is formed.

  A first bonding pad 38 and a second bonding pad 39 are formed on the surface of the insulating film laminated body 8 at an interval of 5 μm, and the first bonding pad 38 and the second bonding pad 39 are formed. Below the pad 39, the first in-layer wiring 21 made of Cu having a width of about 0.14 μm and a thickness of 250 nm electrically insulated from the substrate is formed inside the second insulating film 2. It is formed. A pair of probing pads 32 each made of Al are electrically connected to both ends of the first intra-layer wiring 21 with a stack via 9 made of Cu and a connection portion 51 made of Al interposed.

  A seventh insulating film 19 made of SiN having a thickness of 1.00 μm is formed on the sixth insulating film 6, the first bonding pad 38, the second bonding pad 39, and the probing pad 32. ing. Further, an eighth insulating film 40 made of polyimide having a thickness of 2.00 μm is formed on the seventh insulating film 19.

  Next, a semiconductor device inspection method using the semiconductor device of this embodiment will be described.

  By performing wire bonding on at least one of the first bonding pad 38 or the second bonding pad 39, a vertical mechanical impact is applied to the semiconductor device. Due to this mechanical impact, the insulating film laminate 8 and the first in-layer wiring 21 formed below between the first bonding pad 38 and the second bonding pad 39 are vertically or horizontally oriented. When damage such as deformation or destruction occurs, the first in-layer wiring 21 is disconnected. The disconnection generated in the first intra-layer wiring 21 can be easily detected by evaluating the conduction state between the probing pads 32 with a probe.

  According to the semiconductor device and the inspection method thereof of the present embodiment, many evaluations can be easily performed on the pad and its peripheral structure and the wire bonding conditions. The first bonding pad 38 and the second bonding pad 39 can be used. And the mechanical strength of the first bonding pad 38 and the peripheral portion of the second bonding pad 39 can be easily evaluated.

  In addition, since the first intra-layer wiring 21 is insulated from the substrate, when an element such as a transistor is formed on the substrate, the first bonding pad 38 and the second bonding pad 38 are separated from the defects generated in the transistor. It is possible to evaluate the damage caused to the insulating film laminate 8 and the first in-layer wiring 21 formed between the bonding pads 39.

  In the present embodiment, the first intra-layer wiring 21 is formed in the second insulating film 2, but may be provided in the other insulating film. Further, although two bonding pads are provided, the same evaluation can be performed with only one bonding pad, and three or more bonding pads may be provided.

(First Modification of Fourth Embodiment)
A semiconductor device and an inspection method thereof according to a first modification of the fourth embodiment of the present invention will be described below with reference to FIG. In FIG. 9, the same components as those shown in FIG. Hereinafter, differences of the semiconductor device of this modification from the semiconductor device of the first embodiment will be described.

  FIG. 9A shows a planar configuration of a semiconductor device according to this modification, and FIG. 9B shows a cross-sectional structure taken along line IXb-IXb in FIG. 9A.

  In the present modification, unlike the fourth embodiment, the first intra-layer wiring is provided inside the second insulating film 2 below between the first bonding pad 38 and the second bonding pad 39. In parallel with 21, a second in-layer wiring 22 and a third in-layer wiring 23 are formed. The first in-layer wiring 21 and the second in-layer wiring 22, and the second in-layer wiring 22 and the third in-layer wiring 23 are formed with an interval of about 0.14 μm. The first intra-layer wiring 21 to the third intra-layer wiring 23 are arranged in parallel in the horizontal plane of the second insulating film 2 and are electrically insulated from each other. The first in-layer wiring 21 to the third in-layer wiring 23 are electrically insulated from the substrate.

  A pair of second probing pads made of Al with a stack via 9 made of Cu and a connection portion 51 made of Al interposed at both ends of the second in-layer wiring 22 and the third in-layer wiring 23, respectively. 33 and a pair of third probing pads 34 are electrically connected.

  Next, a semiconductor device inspection method using the semiconductor device of this embodiment will be described.

  By performing wire bonding on at least one of the first bonding pad 38 and the second bonding pad 39, a vertical mechanical impact is applied to the semiconductor device. Due to this mechanical shock, the insulating film laminate 8 and the first in-layer wiring 21 formed below the first bonding pad 38 and the second bonding pad 39 change from the first in-layer wiring 21 to the third in-layer wiring 23. When damage such as deformation or destruction in the vertical direction or horizontal direction occurs, a disconnection or a short circuit occurs from the first in-layer wiring 21 to the third in-layer wiring 23. The disconnection or short circuit generated from the first in-layer wiring 21 to the third in-layer wiring 23 is evaluated by the probe between the first probing pad 32 and the third probing pad 34. Can be easily detected.

  Specifically, the disconnection of the first in-layer wiring 21 indicates whether or not there is conduction between the first probing pads 32, and the disconnection of the second in-layer wiring 22 indicates conduction between the second probing pads 33. Whether or not the third in-layer wiring 23 is disconnected is evaluated based on the presence or absence of conduction between the third probing pads 34. Further, the short-circuit between the first in-layer wiring 21 and the second in-layer wiring 22 is caused by the presence or absence of conduction between the first probing pad 32 and the second probing pad 33, the second in-layer wiring. The short circuit between the wiring 22 and the third intra-layer wiring 23 is evaluated by the presence or absence of conduction between the second probing pad 33 and the third probing pad 34.

  According to the semiconductor device and the inspection method thereof of the present embodiment, many evaluations can be easily performed on the pad and its peripheral structure and the wire bonding conditions. The first bonding pad 38 and the second bonding pad 39 can be used. And the mechanical strength of the first bonding pad 38 and the peripheral portion of the second bonding pad 39 can be easily evaluated.

  In addition, since the first intra-layer wiring 21 is insulated from the substrate, when an element such as a transistor is formed on the substrate, the first bonding pad 38 and the second bonding pad 38 are separated from the defects generated in the transistor. It is possible to evaluate the damage caused to the insulating film laminate 8 and the first in-layer wiring 21 formed between the bonding pads 39.

  In this modification, the first in-layer wiring 21 to the third in-layer wiring 23 are formed in the second insulating film 2, but may be provided in the other insulating film.

  In this modification, three intra-layer wirings are provided. However, if there are two or more intra-layer wirings, both the disconnection in the wiring caused by the mechanical shock and the short circuit between the wirings can be similarly evaluated.

(Second modification of the fourth embodiment)
A semiconductor device and an inspection method thereof according to a second modification of the fourth embodiment of the present invention will be described below with reference to FIG. In FIG. 10, the same components as those shown in FIG. Hereinafter, differences of the semiconductor device of this modification from the semiconductor device of the first embodiment will be described.

  FIG. 10A shows a planar configuration of a semiconductor device according to this modification, and FIG. 10B shows a cross-sectional structure taken along line Xb-Xb in FIG.

  In this modification, unlike the fourth embodiment, in addition to the first in-layer wiring 21, the third insulating film below the first bonding pad 38 and the second bonding pad 39 is provided. 3, the second intra-layer wiring 22 is embedded, and the fourth insulating film 4 is embedded with the intra-layer wiring 31. The first in-layer wiring 21 to the third in-layer wiring 23 are aligned in parallel to the stacking direction of the second insulating film 2 to the fourth insulating film 4 and in the direction perpendicular to the substrate, respectively. Are arranged as follows. The first in-layer wiring 21 to the third in-layer wiring 23 are electrically insulated from each other and electrically insulated from the substrate.

  A pair of second probing pads made of Al with a stack via 9 made of Cu and a connecting portion 51 made of Al interposed at both ends of the second in-layer wiring 22 and the third in-layer wiring 23, respectively. 33 and a pair of third probing pads 35 are electrically connected.

  Next, a semiconductor device inspection method using the semiconductor device of this embodiment will be described.

  By performing wire bonding on at least one of the first bonding pad 38 and the second bonding pad 39, a vertical mechanical impact is applied to the semiconductor device. Due to this mechanical shock, the insulating film laminate 8 and the first in-layer wiring 21 formed below the first bonding pad 38 and the second bonding pad 39 change from the first in-layer wiring 21 to the third in-layer wiring 23. When damage such as deformation or destruction in the vertical direction or horizontal direction occurs, a disconnection or a short circuit occurs from the first in-layer wiring 21 to the third in-layer wiring 23. The disconnection or short circuit generated from the first in-layer wiring 21 to the third in-layer wiring 23 is evaluated by the probe between the first probing pad 32 and the third probing pad 34. Can be easily detected.

  Specifically, the disconnection of the first in-layer wiring 21 indicates whether or not there is conduction between the first probing pads 32, and the disconnection of the second in-layer wiring 22 indicates conduction between the second probing pads 33. Whether or not the third in-layer wiring 23 is disconnected is evaluated based on the presence or absence of conduction between the third probing pads 34. Further, the short-circuit between the first in-layer wiring 21 and the second in-layer wiring 22 is caused by the presence or absence of conduction between the first probing pad 32 and the second probing pad 33, the second in-layer wiring. The short circuit between the wiring 22 and the third intra-layer wiring 23 is evaluated by the presence or absence of conduction between the second probing pad 33 and the third probing pad 34.

  According to the semiconductor device and the inspection method thereof of the present embodiment, many evaluations can be easily performed on the pad and its peripheral structure and the wire bonding conditions. The first bonding pad 38 and the second bonding pad 39 can be used. And the mechanical strength of the first bonding pad 38 and the peripheral portion of the second bonding pad 39 can be easily evaluated.

  In addition, since the first intra-layer wiring 21 is insulated from the substrate, when an element such as a transistor is formed on the substrate, the first bonding pad 38 and the second bonding pad 38 are separated from the defects generated in the transistor. It is possible to evaluate the damage caused to the insulating film laminate 8 and the first in-layer wiring 21 formed between the bonding pads 39.

  In this modification, the first in-layer wiring 21 to the third in-layer wiring 23 are formed in the second insulating film 2, but may be provided in the other insulating film.

  In this modification, three inspection wirings are provided. However, if there are two or more inspection wirings, both the disconnection in the wiring and the short circuit between the wirings caused by mechanical shock can be evaluated in the same manner.

(Fifth embodiment)
The semiconductor device and the inspection method thereof according to the fifth embodiment of the present invention will be described below in detail with reference to FIG. In FIG. 11, the same components as those shown in FIG. Hereinafter, differences of the semiconductor device of this modification from the semiconductor device of the first embodiment will be described.

  FIG. 11 shows a planar configuration of a semiconductor device according to the fifth embodiment of the present invention.

  As shown in FIG. 11, the semiconductor device of this embodiment is different from the semiconductor device of the first embodiment in that a probing pad 71 is electrically connected to each of a pair of first probing pads 32 with a wiring 81 interposed therebetween. Connected.

  According to the semiconductor device of the present embodiment, it is possible to accurately evaluate the damage caused to the semiconductor device due to the mechanical impact applied to the probing pad 32. When wire bonding is performed on the probing pad 32, the probing pad 32 may be damaged by a mechanical impact during wire bonding. When such damage occurs, a measurement error or the like occurs when performing an inspection with a probe. Since the semiconductor device of this embodiment is provided with the probing pad 71 separately from the probing pad 32, no measurement error occurs in such a case.

  The semiconductor device according to the present embodiment has a configuration in which the probing dedicated pad 71 is provided in the semiconductor device according to the first embodiment. It is also possible to provide a dedicated pad for probing.

  In the first to fifth embodiments of the present invention and the modifications thereof, the insulating film laminate 8 is composed of six insulating films. However, the present invention is not limited to this.

  Further, in the first to fifth embodiments and the modifications thereof, the bonding pad 31, the first bonding pad 38, the second bonding pad 39, and the first probing pad 32 to the third are used. The probing pad 34, the probing pad 35, the probing pad 36, the connection part 51 and the connection part 54 are formed using aluminum, but gold, copper, platinum or a conductive material mainly composed of these is used. Also good.

  Further, in the first to fifth embodiments and the modifications thereof, the second insulating film 2 to the fifth insulating film 5 are formed of polyallyl ether, but these depend on the insulating film to be evaluated. What is necessary is just to form, and it forms with SiOF, SiOC, plasma polymerization BCB, tetraethyl orthosilicate (TEOS), methyl silsesquioxane, hydrogen silsesquioxane (HSQ) or fluorine resin, or those in which pores are introduced. do it.

  Further, in the first to fifth embodiments and the modifications thereof, the first intra-layer wiring 21 to the fourth intra-layer wiring 24, the first intra-layer partial wiring 41, and the second intra-layer portion. Although Cu is used as the material of the wiring 42, a conductive material mainly composed of Cu, gold, aluminum, platinum, silver, or a conductive material mainly composed of these materials may be used.

  In the first to fifth embodiments and the modifications thereof, Cu is used as the material of the via 43, the first via 44 to the third via 46, and the stack via 9. However, Cu is the main component. Alternatively, a conductive material such as tungsten, gold, aluminum, platinum, silver, or a conductive material containing these as a main component may be used.

  According to the semiconductor device and the inspection method thereof according to the present invention, a defect such as a disconnection or a short circuit generated in a connection portion such as a wiring or a via of the semiconductor device due to a mechanical shock during mounting can be easily performed by a non-destructive method. Since it can be inspected, it is particularly useful for a semiconductor device for inspecting reliability of a semiconductor device having a low dielectric constant interlayer insulating film with low mechanical strength, an inspection method thereof, and the like.

(A) And (b) shows the semiconductor device which concerns on the 1st Embodiment of this invention, (a) is a top view, (b) is sectional drawing in the Ib-Ib line | wire of (a). (A) to (c) shows a semiconductor device according to a first modification of the first embodiment of the present invention, (a) is a plan view, and (b) is a line IIb-IIb in (a). It is sectional drawing, (c) is sectional drawing in the IIc-IIc line | wire of (a). (A) to (c) shows a semiconductor device according to a second modification of the first embodiment of the present invention, (a) is a plan view, and (b) is a IIIb-IIIb line in (a). It is sectional drawing, (c) is sectional drawing in the IIIc-IIIc line | wire of (a). (A) to (c) shows a semiconductor device according to a second embodiment of the present invention, (a) is a plan view, (b) is a sectional view taken along line IVb-IVb in (a), (C) is sectional drawing in the IVc-IVc line | wire of (a). (A)-(c) shows the semiconductor device which concerns on the modification of the 2nd Embodiment of this invention, (a) is a top view, (b) is the cross section in the Vb-Vb line | wire of (a). (C) is sectional drawing in the Vc-Vc line | wire of (a). (A) to (c) shows a semiconductor device according to a third embodiment of the present invention, (a) is a plan view, (b) is a sectional view taken along line VIb-VIb in (a), (C) is sectional drawing in the VIc-VIc line | wire of (a). (A)-(c) shows the semiconductor device which concerns on the modification of the 3rd Embodiment of this invention, (a) is a top view, (b) is the cross section in the VIIb-VIIb line | wire of (a) It is a figure, (c) is sectional drawing in the VIIc-VIIc line of (a). (A) And (b) shows the semiconductor device which concerns on the 4th Embodiment of this invention, (a) is a top view, (b) is sectional drawing in the VIIIb-VIIIb line | wire of (a). (A) And (b) shows the semiconductor device which concerns on the 1st modification of the 4th Embodiment of this invention, (a) is a top view, (b) is in the IXb-IXb line | wire of (a). It is sectional drawing. (A) And (b) shows the semiconductor device which concerns on the 2nd modification of the 4th Embodiment of this invention, (a) is a top view, (b) is in the Xb-Xb line | wire of (a). It is sectional drawing. These are top views which show the semiconductor device which concerns on the 5th Embodiment of this invention. It is a figure which shows the semiconductor device based on a prior art invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 1st insulating film 2 2nd insulating film 3 3rd insulating film 4 4th insulating film 5 5th insulating film 6 6th insulating film 8 Insulating-film laminated body 9 Stack via | veer 11 1st barrier layer 12 2nd barrier layer 13 3rd barrier layer 14 4th barrier layer 15 5th barrier layer 19 7th insulating film 21 1st in-layer wiring 22 2nd in-layer wiring 23 In 3rd layer Wiring 24 Fourth in-layer wiring 31 Bonding pad 32 First probing pad 33 Second probing pad 34 Third probing pad 35 Probing pad 36 Probing pad 38 First bonding pad 39 First Second bonding pad 40 Eighth insulating film 41 First in-layer partial wiring 42 Second in-layer partial wiring 43 Via 44 First via 45 Second via 46 Third via 47 First via chain 48 Second via chain 49 Stack via 51 Connection section 54 Connection section 71 Probing dedicated pad 81 Connection wiring

Claims (17)

A semiconductor device for inspecting resistance to mechanical shock during mounting of a semiconductor device,
A substrate,
An insulating film laminate in which a plurality of insulating films are laminated on the substrate;
At least one inspection pattern made of a conductor electrically insulated from the substrate and embedded in the insulating film stack; and
A bonding pad that is formed on the insulating film laminate and performs wire bonding that applies a mechanical impact to the inspection pattern;
A semiconductor device comprising: a probing pad formed on the insulating film stack and electrically connected to the inspection pattern.   The semiconductor device according to claim 1, further comprising a probing-dedicated pad formed on the insulating film stack and electrically connected to the probing pad.   The semiconductor device according to claim 1, wherein the probing pad includes a plurality of pads.   4. The semiconductor device according to claim 3, wherein the inspection pattern includes an intra-layer wiring provided on at least one of the plurality of insulating films.   The semiconductor device according to claim 4, wherein the intra-layer wiring includes a plurality, and is provided so as to be insulated from each other by any one of the plurality of insulating films.   The semiconductor device according to claim 4, wherein the intra-layer wiring includes a plurality of wirings, and is provided in two or more insulating films among the plurality of insulating films. The inspection pattern includes a plurality of first in-layer partial wirings provided on any one of the plurality of insulating films, and the first in-layer partial wirings among the plurality of insulating films. A plurality of second layer partial wirings provided in the insulating film excluding the insulating film,
The inspection pattern is a via chain in which each of the first in-layer partial wirings and each of the second in-layer partial wirings are alternately and electrically connected in series by a plurality of vias. The semiconductor device according to claim 3.   The semiconductor device according to claim 7, wherein the via chain includes a plurality of via chains, and the via chains are insulated from each other by different insulating films of the plurality of insulating films.   9. The semiconductor device according to claim 3, wherein the bonding pad is formed in a region above the inspection pattern on the insulating film stacked body.   9. The semiconductor device according to claim 3, wherein the bonding pad is formed above the periphery of the inspection pattern on the insulating film stack. The inspection pattern is:
A plurality of in-layer wirings formed under at least two of the plurality of insulating films, and vias electrically connecting the plurality of in-layer wirings, are formed below the bonding pads. The semiconductor device according to claim 1, wherein the semiconductor device is a stacked via.   12. The semiconductor device according to claim 11, wherein two or more probing pads are provided, and each probing pad is electrically connected to a different intra-layer wiring.   The semiconductor device according to claim 11, wherein the bonding pad is electrically connected to the stack via and also serves as the probing pad. Preparing a semiconductor device according to any one of claims 1 to 13,
Applying a mechanical impact to the bonding pad;
Electrically connecting a probe for inspecting the conduction state of the inspection pattern to the probing pad by applying an electrical signal to the probing pad;
And a step of evaluating damage caused to the inspection pattern by electrically inspecting a conduction state of the inspection pattern using the probe connected to the probing pad. Inspection method.   The method for inspecting a semiconductor device according to claim 14, wherein the step of evaluating the damage generated in the inspection pattern is a step of inspecting the presence or absence of a break in the inspection pattern by the probe.   16. The method for inspecting a semiconductor device according to claim 14, wherein the step of evaluating damage generated in the inspection pattern is a step of inspecting the presence or absence of a short circuit between the inspection patterns by the probe. 17. The method for inspecting a semiconductor device according to claim 14, wherein the step of applying a mechanical impact to the bonding pad is a step of performing wire bonding on the bonding pad.

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