JP2012109402A - Semiconductor device, method of manufacturing semiconductor device, and method of inspecting semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect voids occurring in an interlayer insulating film with high sensitivity.SOLUTION: A semiconductor device comprises a multilayer wiring layer (not shown) and a first TEG pattern (not shown) formed in the multilayer wiring layer. The first TEG pattern includes: a plurality of first lower wiring lines 402 extending in parallel to each other; first vias 602 that penetrate an interlayer insulating film (not shown) and are located between the first lower wiring lines 402 in a plan view; a first terminal 762 that is formed on the top layer (not shown) of the multilayer wiring layer and is connected to the first vias 602; and a second terminal 764 that is formed on the top layer of the multilayer wiring layer and is connected to the first lower wiring lines 402.

Description

  The present invention relates to a semiconductor device, a semiconductor device manufacturing method, and a semiconductor device inspection method.

  In a semiconductor device having a multi-layer wiring in recent years, a defect of the semiconductor device may occur after shipment of the semiconductor device due to a void generated in the interlayer insulating film. Therefore, a method of inspecting the presence or absence of voids before the shipment of the semiconductor device is employed by providing a TEG (Test Element Group) pattern in the semiconductor device.

  For example, Patent Document 1 (Japanese Patent Laid-Open No. 2007-123755) proposes a method for detecting a void generated in a groove type element isolation region. According to Patent Document 1, when a void is generated on the surface of the groove type element isolation region, the conductor partially remains inside the void. Therefore, when the conductor remaining inside the void is electrically connected to a pair of adjacent electrodes, the pair of electrodes is electrically short-circuited. Therefore, it is described that if a voltage is applied between the electrodes, the presence or absence of voids in the grooved element isolation region can be determined by measuring the current value flowing at that time.

JP 2007-123755 A

  However, in the method described in Patent Document 1, it is impossible to detect a void unless at least two electrodes (contact regions) are formed on the void and a conductor is embedded in the void. For this reason, there is a problem that detection is particularly difficult for microvoids, and detection sensitivity is low.

According to the present invention,
A multilayer wiring layer, and a first TEG pattern formed in the multilayer wiring layer,
The first TEG pattern is:
A plurality of first lower layer wirings extending in parallel with each other;
A first via that penetrates the interlayer insulating film and is located between the first lower layer wirings in plan view;
A first terminal formed on the uppermost layer of the multilayer wiring layer and connected to the first via;
A second terminal formed on the uppermost layer and connected to the first lower layer wiring;
A semiconductor device is provided.

According to the present invention,
Forming a first TEG pattern in the multilayer wiring layer;
Inspecting the first TEG pattern;
With
The step of forming the first TEG pattern includes:
Forming a plurality of first lower layer wirings extending in parallel with each other;
Forming an interlayer insulating film between the first lower layer wiring and on the first lower layer wiring;
A via forming step of forming a first via that penetrates the interlayer insulating film and is located between the first lower layer wirings in plan view;
Forming a first terminal connected to the first via and a second terminal connected to the first lower layer wiring on the uppermost layer of the multilayer wiring layer;
With
In the step of inspecting the first TEG pattern,
Provided is a semiconductor device manufacturing method for determining that a void is generated between adjacent first lower-layer wirings in the interlayer insulating film when the first terminal and the second terminal are electrically connected. .

According to the present invention,
A method for inspecting a semiconductor device for detecting voids generated in an interlayer insulating film,
The semiconductor device includes a first TEG pattern in a multilayer wiring layer,
The first TEG pattern is:
A plurality of first lower layer wirings extending in parallel with each other;
A first via that penetrates the interlayer insulating film and is located between the first lower layer wirings in plan view;
A first terminal formed on the uppermost layer of the multilayer wiring layer and connected to the first via;
A second terminal formed on the uppermost layer and connected to the first lower layer wiring;
With
Provided is a semiconductor device inspection method for determining that the void has occurred between the adjacent first lower-layer wirings in the interlayer insulating film when the first terminal and the second terminal are electrically connected. The

  According to the present invention, the semiconductor device includes a first TEG pattern, and the first TEG pattern includes a first via that penetrates the interlayer insulating film and is positioned between the first lower-layer wirings in plan view. In the step of forming the first via, if a void exists between the adjacent first lower layer wirings, the etching gas penetrates into the void from the via hole, and the void is expanded. Next, the metal is embedded up to the expanded portion of the void, and the first via is short-circuited with the first lower layer wiring. Thereby, in the step of inspecting the first TEG pattern, when there is conduction between the first terminal and the second terminal, it is determined that a void is generated between the adjacent first lower layer wirings in the interlayer insulating film. I can do it. As described above, voids generated in the interlayer insulating film can be detected with high sensitivity.

  According to the present invention, voids generated in the interlayer insulating film can be detected with high sensitivity.

It is a top view which shows the structure of the semiconductor device of 1st embodiment. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device of 1st embodiment. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device of 1st embodiment. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device of 1st embodiment. It is a top view which shows the structure of the semiconductor device of 2nd embodiment. It is a top view which shows the structure of the semiconductor device of 3rd embodiment. It is a top view which shows the structure of the semiconductor device of 4th embodiment. It is a figure for demonstrating the effect of 4th embodiment. It is a figure for demonstrating the effect of 4th embodiment. It is a figure for demonstrating the effect of 4th embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

(First embodiment)
FIG. 1 is a plan view showing the configuration of the semiconductor device of the first embodiment. This semiconductor device includes a multilayer wiring layer (not shown, hereinafter omitted) and a first TEG pattern (not shown, omitted hereinafter) formed in the multilayer wiring layer. The first TEG pattern passes through a plurality of first lower layer wirings 402 extending in parallel with each other and an interlayer insulating film (second interlayer insulating film 500 described later), and is positioned between the first lower layer wirings 402 in plan view. The first via 602, the uppermost layer (not shown, hereinafter omitted) of the multilayer wiring layer, the first terminal 762 connected to the first via 602, and the same uppermost layer as described above, And a second terminal 764 connected to the lower layer wiring 402.

  As shown in FIG. 1, the semiconductor device includes a first TEG pattern. FIG. 1 shows only the first TEG pattern, and in addition, has a circuit pattern (not shown, hereinafter omitted) including a FET (Field Effect Transistor) (not shown, hereinafter omitted). A circuit pattern including the FET is formed in a chip region (not shown, hereinafter omitted) shipped as a product. On the other hand, the first TEG pattern is provided on a scribe line when the semiconductor substrate 100 is divided into semiconductor chips (not shown).

  As shown in FIG. 1, the first TEG pattern includes a plurality of first lower layer wirings 402 extending in parallel with each other. The first lower layer wirings 402 are arranged on the lower insulating film (described later, 200) formed on the surface of the semiconductor substrate 100 at equal intervals, for example, every width L and interval S.

  The first TEG pattern includes a first via 602 that passes through an interlayer insulating film (second interlayer insulating film 500 described later) and is located between the first lower layer wirings 402 in a plan view. Here, the first via 602 is preferably arranged in the center between the first lower layer wirings 402 in a plan view, that is, at a position of the distance S / 2 from the first lower layer wiring 402.

  As shown in FIG. 1, a plurality of first vias 602 may be provided. Specifically, the plurality of first vias 602 are arranged at regular intervals at regular intervals in the direction parallel to the direction in which the first lower layer wiring 402 extends between the first lower layer wirings 402 in plan view. May be. As a result, the probability that the first via 602 contacts the void 320 can be increased. That is, the detection sensitivity of the void 320 can be increased.

  The first terminal 762 is formed on the uppermost layer of the multilayer wiring layer. The first terminal 762 is electrically connected to the first via 602 via a first upper layer wiring 702 formed on the first via 602.

  Further, the plurality of first vias 602 described above may be connected to the same first terminal 762. Thereby, the process of inspecting the first TEG pattern to be described later can be shortened.

  As shown in FIG. 1, the contact 604 is formed on the first lower layer wiring 402. The second terminal 764 is formed in the uppermost layer of the multilayer wiring layer, and is electrically connected to the first lower layer wiring 402 via the second upper layer wiring 704 formed on the contact 604, for example. ing. In the present embodiment, the contacts 604 are arranged at regular intervals on the first lower layer wiring 402, but the arrangement is not limited thereto. For example, the second terminal 764 only needs to be electrically connected to the first lower layer wiring 402 by at least one contact 604.

  By providing the first TEG pattern having the above-described configuration, as described later, when the first terminal 762 and the second terminal 764 are electrically connected in the step of inspecting the first TEG pattern, the interlayer insulating film It can be determined that a void 320 is generated between adjacent first lower layer wirings 402 in the first interlayer insulating film 300 (described later).

  Next, a method for manufacturing the semiconductor device shown in FIG. 1 will be described with reference to FIGS. 2 to 4 are cross-sectional views for explaining the semiconductor device manufacturing method of the first embodiment. This method for manufacturing a semiconductor device includes a step of forming a first TEG pattern in a multilayer wiring layer and a step of inspecting the first TEG pattern. In the step of forming the first TEG pattern, first, a plurality of first lower layer wirings 402 extending in parallel with each other are formed. Next, a first interlayer insulating film 300 is formed between the first lower layer wirings 402, and a second interlayer insulating film 500 is formed on the first lower layer wiring 402. Next, a first via 602 that penetrates through the second interlayer insulating film 500 and is located between the first lower layer wirings 402 in a plan view is formed (via formation step). Next, a first terminal 762 connected to the first via 602 and a second terminal 764 connected to the first lower layer wiring 402 are formed in the uppermost layer of the multilayer wiring layer. In the step of inspecting the first TEG pattern, when the first terminal 762 and the second terminal 764 are electrically connected, the void 320 is formed between the adjacent first lower layer wirings 402 in the first interlayer insulating film 300. Is determined to have occurred. Details will be described below.

  Here, the semiconductor substrate 100 is, for example, a silicon substrate. In the semiconductor substrate 100, an FET or the like is formed in a region (chip region) not shown below.

  As shown in FIG. 2A, a lower insulating film 200 such as a silicon oxide film is formed on the semiconductor substrate 100. First, a first lower layer wiring 402, a barrier layer 422, and a barrier layer 442 are formed in a scribe region (not shown) on the lower insulating film 200.

  In this step, wiring (not shown, hereinafter omitted) connected to the FET is formed in the chip region. The wiring interval of this chip area is the same as the interval of the first lower layer wiring 402.

  The first lower layer wiring 402 is, for example, Al, and the barrier layer 422 and the barrier layer 442 are, for example, Ti and TiN. These are formed by sputtering, for example, and patterned by dry etching.

  Next, as shown in FIG. 2B, a first interlayer insulating film 300 is formed on the first lower layer wiring 402 and between the first lower layer wirings 402. The first interlayer insulating film 300 is, for example, a silicon oxide film. At this time, if the film formation conditions of the first interlayer insulating film 300 are inappropriate, voids 320 are generated between the first lower layer wirings 402.

  Next, as shown in FIG. 2C, the first interlayer insulating film 300 is planarized by CMP (Chemical Mechanical Polishing), and the second interlayer wiring 402 and the first interlayer insulating film 300 are formed on the second interlayer insulating film 300. An interlayer insulating film 500 is formed. The second interlayer insulating film 500 is, for example, a silicon oxide film.

  Next, as shown in FIG. 3A, a first via 602 that penetrates through the second interlayer insulating film 500 and is located between the first lower layer wirings 402 is formed (via formation step). At this time, the contact 604 may be formed on the first lower layer wiring 402 simultaneously with the formation of the first via 602. When a void 320 is generated between the first lower layer wirings 402, the first via 602 is connected to the void 320 in this via formation step. Here, the void 320 is extended to the first lower layer wiring 402 in the cross-sectional direction, and the first via 602 is short-circuited with the first lower layer wiring 402. The details of this via formation step will be described later.

  Next, as shown in FIG. 3B, the first upper layer wiring 702, the barrier layer 722, and the barrier layer 742 connected to the first via 602 are formed in the uppermost layer of the multilayer wiring layer. At this time, the first upper layer wiring 702 and the like are formed, and at the same time, the second upper layer wiring 704, the barrier layer 724, and the barrier layer 744 are formed on the contact 604. Although not shown in FIG. 3B, the first upper layer wiring 702 and the like are formed, and at the same time, the first terminal 762 is formed so as to be electrically connected to the first upper layer wiring 702. The second terminal 764 is formed to be electrically connected to the second upper layer wiring 704. The details of the short-circuit portion 662 in FIG. 3B will be described later.

  Next, details of the above-described via formation step when the void 320 occurs will be described. FIG. 4 shows an enlarged view of a portion B in FIG.

  FIG. 4A shows a state after the second interlayer insulating film 500 of FIG. 2C is formed. Here, as described above, the film formation conditions of the first interlayer insulating film 300 are inappropriate, and the void 320 is generated between the first lower layer wirings 402.

  As shown in FIG. 4B, via holes (not shown) for forming the first vias 602 are formed between the first lower layer wirings 402 using RIE (Reactive Ion Etching). Here, an etching gas enters the void 320 from a via hole (not shown), and the side wall of the void 320 is etched and expanded in the cross-sectional direction. At this time, when the void 320 is expanded, the reverse tapered portion 322 is generated. If the void 320 is not generated, the via hole (not shown) stops near the interface with the second interlayer insulating film 500 in the first interlayer insulating film 300 at this stage, and FIG. It does not expand in the cross-sectional direction.

  Next, as shown in FIG. 4C, a barrier layer 622 is formed on the inner wall of the via hole (not shown) and the side wall of the void 320. At this time, since the barrier layer 622 is difficult to be formed in the reverse tapered portion 322, the barrier layer defect portion 642 is formed in the barrier layer 622.

  Next, as shown in FIG. 4D, the metal of the first via 602 is embedded by CVD (Chemical Vapor Deposition). The material used for the first via 602 or the contact 604 is, for example, W (tungsten).

In this via formation step, the metal material used in CVD is, for example, fluoride. In particular, in the embodiment, for example, a WF _6.

  When this fluoride raw material is used, HF or the like is generated as a by-product gas during metal deposition. Thus, HF or the like enters from the barrier layer defect 642 while embedding the metal of the first via 602, and the first interlayer insulating film 300, which is a silicon oxide film, for example, is etched. Thereby, the void 320 is further expanded and expanded to the first lower layer wiring 402 in the cross-sectional direction. In this manner, the metal is buried up to the expanded portion (short-circuit portion 662) of the void 320, and the first via 602 is short-circuited with the first lower-layer wiring 402 via the short-circuit portion 662.

  As described above, even if the minute void 320 is generated, the void 320 is expanded by the etching such as HF described above. Thereby, the void 320 can be detected with high sensitivity.

  Next, a step of inspecting the first TEG pattern is performed. First, a voltage of about 1.5 V, for example, is applied between the first terminal 762 and the second terminal 764 shown in FIG. 1, and the current value flowing between the first terminal 762 and the second terminal 764 is measured. The conduction state of the first terminal 762 and the second terminal 764 is evaluated by comparing the measured current value with a reference current value for short-circuit determination that has been measured in advance. At this time, if the current value flowing between the first terminal 762 and the second terminal 764 is equal to or greater than the reference current value, that is, if the first terminal 762 and the second terminal 764 are electrically connected, the first interlayer It is determined that the void 320 is generated between the adjacent first lower layer wirings 402 in the insulating film 300.

  Next, the effect of this embodiment will be described. According to this embodiment, the semiconductor device includes the first TEG pattern, and the first TEG pattern penetrates the second interlayer insulating film 500 and is located between the first lower layer wirings 402 in a plan view. 602. In the step of forming the first via 602, if the void 320 exists between the adjacent first lower layer wirings 402, the etching gas enters the void 320 from the via hole (not shown), and the void 320 is expanded. Next, a metal is filled up to the expanded portion of the void 320, and the first via 602 is short-circuited with the first lower layer wiring 402. Accordingly, when the first terminal 762 and the second terminal 764 are electrically connected in the step of inspecting the first TEG pattern, a void is formed between the adjacent first lower layer wirings 402 in the first interlayer insulating film 300. It can be determined that 320 has occurred. As described above, the void 320 generated in the interlayer insulating film (first interlayer insulating film 300) can be detected with high sensitivity.

  If the void 320 is not detected in the step of inspecting the first TEG pattern, it is determined that the void 320 is not generated even in the chip region, and it is determined that the semiconductor chip (not shown) including the FET can be shipped. I can do it.

(Second embodiment)
FIG. 5 is a plan view showing the configuration of the semiconductor device of the second embodiment. This embodiment is the same as the first embodiment except for the shape of the first via 602 in plan view.

  As shown in FIG. 5, the first via 602 may have a slit shape in plan view. The slit direction of the first via 602 is preferably a direction parallel to the extending direction of the first lower layer wiring 402.

  According to this embodiment, the probability that the first via 602 contacts the void 320 can be increased. That is, the detection sensitivity of the void 320 can be increased.

(Third embodiment)
FIG. 6 is a plan view showing the configuration of the semiconductor device of the third embodiment. This embodiment is the same as the first embodiment except for the arrangement of the first lower layer wiring 402.

As shown in FIG. 6, the first lower layer wirings 402 may be arranged at different intervals. The four first lower-layer wirings 402 extending in parallel with each other may be arranged at intervals of S ₁ , S ₂ , S ₃ , for example. For example, the first lower layer wiring can be obtained by inspecting the continuity between the second terminal 764a and the second terminal 764b, between the second terminal 764b and the second terminal 764c, and between the second terminal 764c and the second terminal 764d. The probability of occurrence of void 320 at 402 different intervals can be investigated.

  In addition, the interval between any of the first lower layer wirings 402 described above can be made the same as the wiring interval in the chip region including the FET.

In general, the narrower the wiring interval of the multilayer wiring layers, the worse the coverage of the interlayer insulating film, and the more easily voids are generated. Therefore, for example, the minimum interval of wiring in the chip region is set to S ₂ (> S ₁ ). Thus, in consideration of safety, if a void 320 is detected in between the first lower layer wiring 402 intervals S ₁ of the first TEG pattern, the decision to allow shipping semiconductor chip (not shown) comprising a FET I can do it.

(Fourth embodiment)
FIG. 7 is a plan view showing the configuration of the semiconductor device of the fourth embodiment. This embodiment is the same as the first embodiment except that a second TEG pattern is provided.

As shown in FIG. 7, a second TEG pattern (not shown, hereinafter omitted) is provided in a region that does not overlap the first TEG pattern in plan view. The second TEG pattern includes a second lower layer wiring 404, a second via 606, and a third terminal 766. The second lower layer wiring 404 is formed in the same layer as the first lower layer wiring 402. The second via 606 has the same diameter as the first via 602 and is formed in the same layer as the first via 602. Furthermore, the second via 606 is provided at the same interval as the interval S ₄ between the first lower layer interconnect 402 and the center of the first via 602 with respect to the second lower layer interconnect 404 in plan view. The third terminal 766 is formed in the uppermost layer of the multilayer wiring layer and is connected to the second via 606. Details will be described below.

  The second TEG pattern is a TEG pattern for detecting a positional shift of the first via 602 or the like. The “positional deviation” referred to below refers to a positional deviation in a plan view of the first via 602 and the second via 606 formed in the same layer as the first via 602.

  As shown in FIG. 7, the second lower layer wiring 404 is formed in the same layer as the first lower layer wiring 402. On the second lower layer wiring 404, for example, a contact 608 is formed in the same layer as the first via 602. The contact 608 is electrically connected to the second terminal 764 by connecting to a fourth upper layer wiring 708 formed on the contact 608, for example. In addition to the second terminal 764, a terminal for the contact 608 having the second TEG pattern may be provided.

  Here, the second lower layer wiring 404 may be formed wider than the width of the first lower layer wiring 402. As a result, even if the first via 602 and the contact 608 are misaligned, the contact 608 is reliably connected to the second lower layer wiring 404. That is, even if the above-described misalignment occurs, the second TEG pattern can be reliably inspected.

As shown in FIG. 7, the second via 606 has the same diameter as the first via 602 and is formed in the same layer as the first via 602. Furthermore, the second via 606 is provided at the same interval as the interval S ₄ between the first lower layer interconnect 402 and the center of the first via 602 with respect to the second lower layer interconnect 404 in plan view.

  The first via 602 and the contact 604 in the first TEG pattern, and the second via 606 and the contact 608 in the second TEG pattern are formed using, for example, the same photomask. Thereby, when the first via 602 is misaligned, other second vias 606 and the like are simultaneously misaligned in the same direction as the first via 602.

  The third terminal 766 is formed in the uppermost layer of the multilayer wiring layer. The third terminal 766 is connected to the second via 606 by connecting to the third upper layer wiring 706 formed on the second via 606. The third upper layer wiring 706 may be formed wider than the width of the first upper layer wiring 702, for example. As a result, when the first via 602 and the second via 606 are misaligned, the probability that the second via 606 is connected to the third upper layer wiring 706 is increased. For this reason, even if the above-mentioned position shift occurs, the detection sensitivity of the second TEG pattern is increased.

Furthermore, as shown in FIG. 7, for example, on the opposite side of the second via 606, which is provided at the same spacing S ₄ to the second lower layer wiring 404, the second lower-layer wirings 404 are formed on the same spacing S ₄ Not. Thereby, the void 320 can be prevented from being formed in the second TEG pattern.

  In addition, as shown in FIG. 7, at least two or more sets of the second lower layer wiring 404 and the second via 606 are different from each other in the direction perpendicular to the extending direction of the first lower layer wiring 402 (reverse direction). ) May be formed. As a result, it is possible to detect the displacement of the first via 602 and the like in both the extending direction and the vertical direction of the first lower layer wiring 402. Alternatively, it is possible to detect misalignment of the first via 602 and the like by distinguishing different directions.

  The step of inspecting the second TEG pattern may be performed simultaneously with the step of inspecting the first TEG pattern.

  The effect of the fourth embodiment will be described with reference to FIGS. 8-10 is a figure for demonstrating the effect of 4th embodiment. According to this embodiment, the second TEG pattern described above is formed on the same semiconductor substrate 100 as the first TEG pattern. Thereby, when there is continuity in the step of inspecting the first TEG pattern, the second TEG pattern is inspected so that the continuity is caused by the generation of the void 320 or the first via 602 and the like are misaligned. It can be judged.

  First, with reference to FIGS. 8 and 9, the case where the first via 602 and the like are misaligned will be described.

  FIG. 8 shows a case where the first via 602 and the like are displaced to the first terminal 762 side. In the first TEG pattern, the first terminal 762 and the second terminal 764 are electrically connected due to the displacement of the first via 602 regardless of the presence or absence of the void 320. By simply inspecting the first TEG pattern, it cannot be determined whether the cause of the conduction is due to the occurrence of the void 320 or the positional deviation of the first via 602 or the like.

  On the other hand, as shown in FIG. 8, in the second TEG pattern, the second via 606 is displaced and connected to the second lower layer wiring 404 in the C portion. As a result, the second terminal 764 and the third terminal 766 are electrically connected in the second TEG pattern.

  The case of FIG. 8 is the situation of FIG. The first TEG pattern is conductive (Short) and the second TEG pattern is also conductive (Short), and it can be determined that the first via 602 and the like have been misaligned.

  FIG. 9 shows a case where the first via 602 and the like are displaced to the opposite side to the first terminal 762. As in the case of FIG. 8, in the first TEG pattern, regardless of the presence or absence of the void 320, the first terminal 762 and the second terminal 764 are electrically connected due to the displacement of the first via 602. By simply inspecting the first TEG pattern, it cannot be determined whether the cause of the conduction is due to the occurrence of the void 320 or the positional deviation of the first via 602 or the like.

  On the other hand, as shown in FIG. 9, in the second TEG pattern, the second via 606 is displaced and connected to the second lower layer wiring 404 in the D portion. As a result, the second terminal 764 and the third terminal 766 are electrically connected in the second TEG pattern.

  In the case of FIG. 9, the situation of FIG. 10A is the same as in the case of FIG. The first TEG pattern is conductive (Short) and the second TEG pattern is also conductive (Short), and it can be determined that the first via 602 and the like have been misaligned.

  8 and FIG. 9, FIG. 7 shows a case where the first via 602 and the like are not displaced and the void 320 is detected at the correct design position of the first via 602 and the like. That is, the first TEG pattern in FIG. 7 is the same situation as described in the first embodiment.

  When the void 320 is generated in the first TEG pattern, the first terminal 762 and the second terminal 764 are conductive. On the other hand, in the second TEG pattern, the second terminal 764 and the third terminal 766 are not conductive. Therefore, it can be seen that this situation is not due to the displacement of the first via 602 or the like, but is due to the occurrence of the void 320.

  In the case of FIG. 7, the situation is as shown in FIG. It can be determined that the first TEG pattern is conductive (short) and the second TEG pattern is insulated (open), and the void 320 is generated.

  10C, the first TEG pattern is open (Open), the second TEG pattern is also open (Open), the void 320 is generated, and the first via 602 is misaligned. It can be determined that nothing has happened. It should be noted that the situation where the first TEG pattern is open (Open) and the second TEG pattern is conductive (Short) does not occur in principle.

  As described above, according to the present embodiment, the second TEG pattern is formed on the same semiconductor substrate 100 as the first TEG pattern. Thereby, when there is continuity in the step of inspecting the first TEG pattern, the second TEG pattern is inspected so that the continuity is caused by the generation of the void 320 or the first via 602 and the like are misaligned. It can be judged.

  As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.

100 Semiconductor substrate 200 Lower layer insulating film 300 First interlayer insulating film 320 Void 322 Reverse taper portion 402 First lower layer wiring 404 Second lower layer wiring 422 Barrier layer 442 Barrier layer 500 Second interlayer insulating film 602 First via 604 Contact 606 Second via 608 Contact 622 Barrier layer 642 Barrier layer defect portion 662 Short-circuit portion 702 First upper layer wiring 704 Second upper layer wiring 706 Third upper layer wiring 708 Fourth upper layer wiring 722 Barrier layer 724 Barrier layer 742 Barrier layer 744 Barrier layer 762 First One terminal 764 Second terminal 764a Second terminal 764b Second terminal 764c Second terminal 764d Second terminal 766 Third terminal

Claims (11)

A multilayer wiring layer, and a first TEG pattern formed in the multilayer wiring layer,
The first TEG pattern is:
A plurality of first lower layer wirings extending in parallel with each other;
A first via that penetrates the interlayer insulating film and is located between the first lower layer wirings in plan view;
A first terminal formed on the uppermost layer of the multilayer wiring layer and connected to the first via;
A second terminal formed on the uppermost layer and connected to the first lower layer wiring;
A semiconductor device comprising: The semiconductor device according to claim 1,
A semiconductor device in which a plurality of the first vias are provided. The semiconductor device according to claim 2,
The plurality of first vias are semiconductor devices connected to the same first terminal. The semiconductor device according to claim 1,
The first via is a semiconductor device having a slit shape in plan view. In the semiconductor device according to any one of claims 1 to 4,
The semiconductor device in which the first lower layer wirings are arranged at different intervals. In the semiconductor device according to any one of claims 1 to 5,
And a second TEG pattern arranged in a region not overlapping with the first TEG pattern in plan view,
The second TEG pattern is:
A second lower layer wiring formed in the same layer as the first lower layer wiring;
The same diameter as the first via, formed in the same layer as the first via, and in plan view, with respect to the second lower layer wiring, between the first lower layer wiring and the center of the first via A second via provided at the same interval as the interval;
A third terminal formed in the uppermost layer and connected to the second via;
A semiconductor device comprising: The semiconductor device according to claim 6.
A semiconductor device in which the second lower layer wiring is not formed within the same interval on the opposite side of the second via provided at the same interval with respect to the second lower layer wiring. The semiconductor device according to claim 7,
A semiconductor device in which at least two or more sets of the second lower layer wiring and the second via are formed in different directions with respect to a direction perpendicular to the extending direction of the first lower layer wiring. Forming a first TEG pattern in the multilayer wiring layer;
Inspecting the first TEG pattern;
With
The step of forming the first TEG pattern includes:
Forming a plurality of first lower layer wirings extending in parallel with each other;
Forming an interlayer insulating film between the first lower layer wiring and on the first lower layer wiring;
A via forming step of forming a first via that penetrates the interlayer insulating film and is located between the first lower layer wirings in plan view;
Forming a first terminal connected to the first via and a second terminal connected to the first lower layer wiring on the uppermost layer of the multilayer wiring layer;
With
In the step of inspecting the first TEG pattern,
A method of manufacturing a semiconductor device, wherein when there is electrical connection between the first terminal and the second terminal, it is determined that a void is generated between adjacent first lower-layer wirings in the interlayer insulating film. In the manufacturing method of the semiconductor device according to claim 9,
The method for manufacturing a semiconductor device, wherein the metal raw material in the via forming step is fluoride. A method for inspecting a semiconductor device for detecting voids generated in an interlayer insulating film,
The semiconductor device includes a first TEG pattern in a multilayer wiring layer,
The first TEG pattern is:
A plurality of first lower layer wirings extending in parallel with each other;
A first via that penetrates the interlayer insulating film and is located between the first lower layer wirings in plan view;
A first terminal formed on the uppermost layer of the multilayer wiring layer and connected to the first via;
A second terminal formed on the uppermost layer and connected to the first lower layer wiring;
With
A method for inspecting a semiconductor device, wherein when the first terminal and the second terminal are electrically connected, it is determined that the void is generated between the adjacent first lower layer wirings in the interlayer insulating film.

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