JP2007194531A - Apparatus capable of estimating resistance property - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily and correctly estimate breakage of a chip due to impact force in bonding after stacking chips, when a fragile porous low-k material which has less bondability and is easily peeled is used as an insulating film and in a thin chip having a chip thickness of 100 μm or less. <P>SOLUTION: In an apparatus capable of estimating stack resistance by stacking to bond a chip B (upper chip) onto a chip A (lower chip); an element for evaluating the resistance is provided on the chip A, and the chip positions correspond to corners in a stacking range within a stacking range of the chips A and B and in a region inside of 50-1,000 μm from the outermost peripheral edge of the stacking range. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a technology capable of evaluating physical resistance of a chip in a package process of a semiconductor device.

  A semiconductor device has a structure in which a multilayer wiring film made of a metal wiring film sandwiched between inorganic or organic material insulating films is provided on a physically fragile semiconductor Si substrate. And the semiconductor device of the said structure is assembled according to a package process, and becomes a product.

  In this assembly process (package process), if the semiconductor device does not have a desired physical strength, the semiconductor device is damaged and becomes a defective product. Therefore, it is very important to evaluate whether the semiconductor device has a desired physical strength. Further, when viewed from the opposite viewpoint, if the physical strength cannot be secured, it is necessary to change the process so as to cope with it. For this reason, an electrical property is evaluated after a reliability test as a semiconductor product after passing through each process using a normal device.

  By the way, in the electrical measurement by a normal device, the electrical characteristics of the device itself may fluctuate, and it is difficult to grasp which characteristics of the device are changed. In addition, it is difficult to discriminate change data between the electrical characteristics of the chip before entering the assembly process and the electrical characteristics due to assembly process factors.

  By the way, if it is an evaluation that only changes the production line of a normal device a little, it can be judged that there is no problem if the change is within the standard as a product. On the other hand, when the device structure is newly changed, for example, when a novel porous low dielectric constant material (low-k material) is used as an insulating film, the low-k material is porous. Because of its fragility due to its quality, devices with multi-layered wiring films are physically vulnerable to wiring films (wiring layers) and are subject to various effects in the packaging process, and their electrical characteristics are affected by structural changes. It is very difficult to identify the cause of device failure.

Japanese Patent Application Laid-Open No. 2004-253609 discloses a semiconductor device in which three chips are stacked and the electrical characteristics of the chip can be evaluated with pads around the chip. And it is said that it is possible to evaluate the influence on the wiring layer in the back-end process of the previous process, which is to reduce the test cost.
Japanese Patent Laid-Open No. 2004-253609

  However, in the above proposal, there is a problem that it is necessary to perform wire bonding for the test and that the test cannot be performed unless the three chips are stacked. It has also been found that reliability evaluation such as temperature cycle test after die bonding or resin sealing is not sufficient. That is, in the assembly process and the reliability test after assembly, it is difficult to evaluate which process is damaging the electrical characteristics of the chip.

  Therefore, the problem to be solved by the present invention is to provide a technique that can easily and accurately evaluate packaging damage after die bonding. In particular, it is to provide a technique that can easily and accurately evaluate damage caused by chip stacking.

Now, it has been found that damage caused by stacking of chips is very important in the following cases. Of course, there have been talks about damage caused by the stacking of chips. However, in the conventional case where SiO ₂ is used as the interlayer insulating film and the thickness of the chip is large, this is not a big problem. However, as it is required to reduce the dielectric constant of the interlayer insulating film in order to improve the signal speed, a fragile porous low-k film is used as the interlayer insulating film, and the chip thickness is 100 μm or less. As it became thinner, damage caused by stacking became relatively large, and countermeasures and evaluation became important. In particular, the risk of damage to the chip due to the impact force generated during bonding after stacking has increased, and evaluation of its resistance has become increasingly important.

  Therefore, while proceeding with the examination from such a viewpoint, if TEG (Test Element Group) is skillfully established, chip breakage due to impact force at the time of bonding after chip stacking is easy, and I came to realize that it can be evaluated accurately.

  The present invention has been achieved based on such knowledge.

That is, the above-mentioned problem is an apparatus capable of evaluating stacking resistance in which chips B are stacked and bonded on the chip A,
Chip A is provided with an element for evaluating resistance,
Stacking tolerance evaluation is possible, characterized in that the arrangement position of the element is within the stacking range of chip A and chip B, and is an area 50 to 1000 μm inside from the outermost peripheral edge of the stacking range Solved by the device.

In particular, it is a device capable of evaluating the stacking resistance in which the chip B is stacked and bonded on the chip A,
Chip A is provided with an element for evaluating resistance,
The arrangement position of the element is within the stacking range of the chip A and the chip B, and is an area 50 to 1000 μm inside from the outermost peripheral edge of the stacking range, and further at the corner of the stacking range. It is solved by a stacking tolerance evaluable device characterized in that it corresponds.

  In the present invention described above, when the chip A and the chip B are bonded with an adhesive such as an epoxy adhesive, or when the element is configured by using a porous material, the dielectric constant is particularly large. Is particularly effective when an element is formed by using an insulating film of 3 or less in the wiring film portion, or when the thickness of the chip is 100 μm or less.

  The present invention in which a TEG (resistance evaluation element) is provided at a clever position can easily and accurately evaluate chip breakage due to impact force during bonding after chip stacking. In particular, when the chip A and the chip B are bonded by an adhesive such as an epoxy adhesive, or when a porous fragile insulating film having a dielectric constant of 3 or less is used, or When the thickness is 100 μm or less, chip breakage due to impact force during bonding after stacking chips can be easily and accurately evaluated.

  The stacking tolerance evaluation capable device according to the present invention is obtained by stacking and joining chips B on chips A. For example, chip A and chip B are bonded by an adhesive such as an epoxy adhesive or a polyimide adhesive. The stacking form is, for example, a + -shaped form, or a form in which only a part is stacked in steps, or because the upper chip is smaller than the lower chip, the upper chip is fully stacked. It may be in the form of being overlaid. The stacked form is preferably close to a form similar to the configuration of the semiconductor device to be evaluated. That is, if the form of the semiconductor device is, for example, the stacking form shown in FIG. 1, the stacking form of the stacking tolerance evaluation possible apparatus is also the stacking form as shown in FIG. If the form of the semiconductor device is, for example, the stacking form shown in FIG. 2, the stacking form of the stacking tolerance evaluation possible apparatus is also the stacking form as shown in FIG. The lower chip A is provided with an element (TEG) for evaluating resistance. The arrangement position is within the stacking range of the lower chip A and the upper chip B. And it is an area | region inside 50-1000 micrometers (especially 200 micrometers or more. 500 micrometers or less) from the outermost periphery of this stacking range. Furthermore, it is provided corresponding to the corner of the stacking range. The TEG includes a wiring film having a predetermined pattern. In particular, a porous material (in particular, a porous material having a dielectric constant of 3 or less) used as an interlayer insulating film in an actual semiconductor device is used. The thicknesses of the chips A and B are the same as the thickness of the actual semiconductor device. Since the thickness of the semiconductor device is 100 μm or less, particularly 50 μm or less, the thicknesses of the chips A and B are similarly 100 μm or less, particularly 50 μm or less. The lower limit of the thickness is actually 10 μm.

  This will be described in more detail.

  1-3 is explanatory drawing which shows the stacking and joining form of the lower chip | tip A and the upper chip | tip B in the stacking tolerance evaluation possible apparatus which becomes this invention.

  Evaluation of damage to the wiring film in the process where stress is applied to the lower chip A in the die bonding process, damage evaluation during wire bonding to the lower chip A when the upper chip B is overhanging, or reflow resistance, sealing An evaluation TEG (resistance evaluation element) arrangement structure used for package reliability evaluation in which stress is applied to the lower chip A due to a thermal history called a temperature cycle test after stopping is shown in FIGS. This evaluation TEG is provided in the lower chip A. However, as long as it is provided in the lower chip A, it does not mean that any number of places is acceptable. As can be seen from FIGS. 1, 2, and 3, the position of the TEG is within the stacking range of the lower chip A and the upper chip B. And it is in the area | region inside 50-1000 micrometers (especially 200 micrometers or more. 500 micrometers or less) from the outermost periphery of this stacking range. Since the chips A and B are rectangular, the shape of the stacking range of the lower chip A and the upper chip B is also rectangular. A TEG is provided corresponding to the position of the corner of the rectangle. Accordingly, in FIGS. 1, 2, and 3, the TEGs are provided at the four corners of the stacking range. In addition, it does not need to be provided in all four corners. However, it is preferable to arrange them at three locations in the four corners. That is, if it is disposed at least at three locations, it is possible to evaluate the chip inclination and bonding pressure distribution.

  In FIG. 1, the lower chip A and the upper chip B are both rectangular, and the short side of the rectangular upper chip B corresponds to the long side of the rectangular lower chip A (90 ° phase difference). It is a thing piled up. Therefore, this structure is suitable for evaluating the process influence due to overhang. And in the thing of such a form, since it becomes a form which the bonding pad exposed, wire bonding is easy. In FIG. 2, the lower chip A and the upper chip B are similar in size or size, and one chip is stacked while being shifted in one direction (horizontal). Therefore, this structure is suitable for simultaneously evaluating the presence or absence of the influence of overhang. And in the thing of such a form, since it becomes a form which the bonding pad exposed, wire bonding is easy. FIG. 3 shows the upper chips B that are smaller than the lower chips A stacked without protruding. Therefore, this structure is suitable for evaluating process influences such as die bonding and wire bonding to the upper chip.

  Chips A and B of the present invention, particularly the lower chip A, have a thickness of 100 μm or less. In particular, it is 50 μm or less. Thus, in the case where the wafer is thinly ground, its vulnerability becomes very large. That is, the influence appears greatly at the time of die bonding. Therefore, the evaluation according to the present invention is very effective. It is useful for evaluating a package in which a plurality of chips are stacked, such as a stacked CSP using such an ultrathin chip.

  In the present invention, the position where the TEG is disposed is in the region 50 to 1000 μm (particularly 200 μm or more and 500 μm or less) from the outermost peripheral edge of the stacking range of the chips A and B. This is because if the distance is too close to less than 50 μm, the TEG is likely to be destroyed by the die bonding process. On the other hand, if the distance exceeds 1000 μm, the sensitivity to die bonding is too low and accurate evaluation cannot be performed.

  Various resistance patterns (wiring films) constituting the measurement TEG can be used. For example, if a bend pattern and a via chain structure that bends between layers in a plane as shown in FIG. 4 are employed, it is possible to evaluate the change in resistance value using the measurement pads A1 to An. In addition, by providing a measurement terminal (for example, A2) in the middle of the pattern as a zigzag pattern having different distances from the chip cut surface, the degree of influence of the crack can be seen. Alternatively, when a zigzag pattern in the plane as shown in FIG. 5 and a via chain structure zigzag between layers are employed, the measuring pads B, C having the same number, for example, the measuring pad B1 and the measuring pad C1 are used. Thus, it is possible to evaluate the change in resistance value. In addition, the inter-wiring capacitance, short check, insulation withstand voltage, and leakage current can be measured using the same alphabetic measurement pads such as the measurement pad D1 and the measurement pad D2. Alternatively, when a zigzag pattern in a plane as shown in FIG. 6 and a via chain structure zigzag between layers are employed, the measurement pads D and E can be used to connect the wiring between measurement pads D1 and E, for example. It is possible to evaluate changes in capacitance, short check, withstand voltage, and leakage current. In addition, the resistance value can be measured using the same alphabetic measurement pads such as the measurement pad C1 and the measurement pad C2. The wiring width and via diameter in this pattern are preferably 80 to 1000 nm, more preferably 90 to 200 nm, and still more preferably 90 to 110 nm. This is because pattern formation is difficult if the wiring width is less than 80 nm, and conversely if the thickness exceeds 1000 nm, sufficient sensitivity is difficult to obtain. The total wiring length of the pattern is preferably 100 μm to 1 m, more preferably 1 to 100 mm. An appropriate selection is made according to the degree of influence of the failure mode. If the thickness is less than 100 μm, sufficient sensitivity is difficult to obtain, and if it exceeds 1 m, defects are likely to occur during pattern formation and measurement errors are likely to occur. The number of vias is preferably 100 to 10M, more preferably 1000 to 1M. If it is less than 100, sufficient sensitivity is difficult to obtain, and if it exceeds 10 M, defects are likely to occur during pattern formation and measurement errors are likely to occur. When there is a restriction on the area where the terminals are installed, a folded pattern in which a failure mode is expected to be generated may be arbitrarily bent. This is particularly effective at the corner of the chip.

  Further, the measurement TEG can be measured by selecting a suitable TEG from a reference TEG provided at a position where stress is difficult to be applied, for example, a central portion, and configuring a Wheatstone bridge. Resistors for input resistance adjustment, output adjustment, bridge balance, zero point compensation, sensitivity compensation can be inserted. In particular, when a Wheatstone bridge is formed using TEGs of the same pattern arranged at the four corners, a change due to the resistance change or the like can be easily detected.

  In the present embodiment, evaluation of damage to the low-k material after completion of the package, cracking of the thin chip, and the like can be evaluated without opening the package, and thus package reliability can be easily evaluated.

  Hereinafter, specific examples will be described.

[Example 1]
The TEG of the pattern shown in FIG. 4 using BD (Black Diamond) as a low-k material, as shown in FIG. 1, has four corners (from the stacking outer edge line) in the stacking range of chip A and chip B. A sample wafer having a two-layer wiring film in which a TEG having the same pattern is disposed at the center of the chip as a reference is prepared on the lower chip A corresponding to a portion corresponding to the inner side of 50 μm. The number of via chains constituting the TEG is 2M, and the via diameter is 110 nm. Then, the resistance value of each TEG is measured in advance to confirm that the TEG is a good product. Judgment was made when the resistance value was doubled or more. As the numerical standard, different numerical values can be used depending on the evaluation target.

  Next, the wafer was back-ground to a thickness of 50 μm by a glass support method, and diced using a dicing tape with DAF. The chip size is 8.6 mm × 5.4 mm. The resistance value was measured again after dicing, and it was confirmed that there was no defect. Pickup was performed by a needleless method using a CPS-3000 manufactured by NEC Machinery, and die bonding was performed on a glass epoxy substrate. Thereafter, DAF was cured.

  And after die-bonding only the lower chip | tip A, 15 chips | tips were measured, As a result, the defect of TEG in four places was not recognized. Of course, no defect was found in the reference TEG at the center of the chip.

  Thereafter, the upper chip B was stacked by die bonding. Then, the TEG of the lower chip was examined. As a result, the defect ratios of the four TEGs were 3/15, 8/15, 5/15, and 4/15, respectively. No defect was found in the reference TEG at the center of the chip.

  In other words, it can be seen that the lower chip is damaged by stacking the chips. However, it can be seen that the damage does not occur in the central part, but easily occurs in the peripheral part in the stacking region. Therefore, it can be seen that by using the present invention, defects due to chip stacking can be evaluated, and in particular, it can be used for improving die bonding work.

[Example 2]
The TEG of the pattern shown in FIG. 6 using BD (Black Diamond) as the low-k material is shown in FIG. 3 at four corners (from the stack outer edge line) of the stack range of chip A and chip B. A sample wafer having a two-layer wiring film in which a TEG having the same pattern is disposed at the center of the chip as a reference is prepared on the lower chip A corresponding to a portion corresponding to 50 μm inside. The number of via chains constituting the TEG is 2M, the via diameter is 110 nm, and the total facing length including the vias is 400 mm. Then, the resistance value of each TEG is measured in advance to confirm that the TEG is a good product. Judgment was made when the resistance value was doubled or more. As the numerical standard, different numerical values can be used depending on the evaluation target.

  Next, the wafer was back-ground to a thickness of 50 μm by a glass support method, and diced using a dicing tape with DAF. The chip size is 8.6 mm × 5.4 mm for the upper chip A and 8.6 mm × 8.6 mm for the lower chip B. The resistance value was measured again after dicing, and it was confirmed that there was no defect. Pickup was performed by a needleless method using a CPS-3000 manufactured by NEC Machinery, and die bonding was performed on a glass epoxy substrate. Thereafter, DAF was cured.

  And after die-bonding only the lower chip | tip A, the capacity | capacitance change of 15 chips | tips was measured, As a result, a change was not recognized in any of 4 TEGs. Of course, no change was observed in the reference TEG at the center of the chip. In other words, it can be seen that there was no influence from this die bonding.

  Thereafter, the upper chip B was stacked by die bonding. And the capacity | capacitance change was investigated about TEG of the lower stage chip | tip. As a result, the change rates in the four TEGs were 4%, 8%, 9%, and 11%, respectively. Note that no change was observed in the reference TEG at the center of the chip.

  In other words, it can be seen that the lower chip is damaged by stacking the chips. However, it can be seen that the damage does not occur in the central part, but easily occurs in the peripheral part in the stacking region. Therefore, it can be seen that by using the present invention, defects due to chip stacking can be evaluated, and in particular, it can be used for improving die bonding work.

  Note that only the main measurement TEG may be provided and used as a monitor for the occurrence of defects in the assembly process, or may be incorporated in an actual semiconductor device. By using the present invention, not only die bonding but also many processes from die bonding to package reliability evaluation after package assembly are possible. It is also possible to evaluate the influence of stress due to the mold resin after resin sealing, the influence of thermal stress in the package reliability test, and the like.

Explanatory drawing which shows the element position in the stacking tolerance evaluation possible apparatus of this invention Explanatory drawing which shows the element position in the stacking tolerance evaluation possible apparatus of this invention Explanatory drawing which shows the element position in the stacking tolerance evaluation possible apparatus of this invention Illustration of TEG pattern Illustration of TEG pattern Illustration of TEG pattern Illustration of TEG pattern

Explanation of symbols

TEG resistance evaluation element

Representative Katsumi Udaka

Claims (4)

It is a device capable of evaluating stacking resistance in which chip B is stacked and bonded on chip A,
Chip A is provided with an element for evaluating resistance,
Stacking tolerance evaluation is possible, characterized in that the arrangement position of the element is within the stacking range of chip A and chip B, and is an area 50 to 1000 μm inside from the outermost peripheral edge of the stacking range apparatus.   The device according to claim 1, wherein the element is provided corresponding to a corner of the stacking range.   3. The stacking tolerance evaluation apparatus according to claim 1, wherein the chip A and the chip B are joined with an adhesive. The device according to any one of claims 1 to 3, wherein the element is configured using a porous material.

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