TWI334490B - Test board - Google Patents

Description

1334490 ASEKI922-NEW-FINAL-TW-2〇〇7〇72〇9, invention description: [Technical field of the invention] The present invention relates to a kind of occupation, and the system is related to reliability for wafer bonding Tears,] test the test board. [Prior Art] ^Integrated circuits or crystals have been made, and no matter which stage is used, electrical testing of integrated circuits or wafers is a must. The mother's integrated circuit, whether it is in the wafer's type or ambiguity, determines whether it is good or not, and the electrical properties are more:::: The structure is becoming more and more complex, with high speed and accurate medium system. A top view of a test carrier is shown in Fig. 1 Α "° The carrier plate carries a cross-sectional view of a package component. Please refer to FIG. 1 and = 'X-type carrier 1' includes a dielectric layer m, a plurality of connections; - an acoustic pad 13G and a plurality of wires 140. The dielectric layer 110 has '2' and the surface U2 has a component land 112a in which the interface lightning is distributed within the element land 11b. The test cartridge 130 is disposed on the surface U2 of the continuation and is located outside the component land 112a. The green guide 14 is electrically connected to the pad 120 through a wire 140 disposed on the surface 112 of the dielectric layer 110. The package component 5 is electrically connected to the pads in the component bonding region U2a. The user can input a test signal from a portion of the test pad 13 to the package 1334490 ASEK1922-NEW-FINAL-TW-20070720 component 50 and read the test result from another portion of the test pad i3〇. Since the wires 14 of the conventional test carrier 100 are disposed on the surface 112 of the dielectric layer 110, it is easy to be subjected to structural stress concentration or external force after the package component 50 is bonded to the test carrier 1 . The wire H0 is caused to open in the stress concentration region 150. This will result in the failure to judge during the test that the measured error is caused by the joint f between the package component 5 and the test carrier, or by the test load. The board 1 is caused by the disconnection of itself. In other words, this poorly designed test carrier design will directly affect the accuracy of the test. SUMMARY OF THE INVENTION The connection board ''''''''''''''

It has a 'multi-layered version: the content of the Ming' is proposed here - a test carrier, 塾. The above-mentioned loading and unloading layer is electrically connected to the inner layer and the test piece is opposite to the test piece, and the second layer is used to carry the - seal body-surface layer, to a, and the test board comprises a plurality of dielectrics. Layer, test pad. The surface layer of the surface layer is “intermediate; multiple external pads and multiple adjacent dielectric gates are taken from the outside. The inner layer is located in the “area line!”. The interface can be bonded to the device, and the electrical properties of the pad are: on the circuit layer, and are arranged on the circuit layer and the inner circuit layer with the package test. From the inner layer of the circuit layer on the edge layer of the circuit board, and the test is connected to the part of the touch that is connected to it. 1334490 ASEKl 922-NEW-FINAL-TW-20070720 The above test carrier may further include a protective layer. It covers the surface circuit layer 'and exposes the pads and test flaws. In the embodiment of the present invention, the inner layer circuit layer includes a multi-H time-in-time test and a corresponding partial connection, and the surface circuit system may include a second wire, and the second wire is respectively

Another test carrier is provided, which is a single package; = I package component, the test carrier includes a dielectric layer, a plurality of pads, a connection line, a plurality of sides, and a plurality of sections. The dielectric iso-first surface and the second surface opposite thereto, the first surface, have a joint H for carrying the I-I element. The contacts may be arranged in an array on the 接合-engagement region (10) 表面-surface ′ (4) and the wrought component bonding connection line is located on at least one of the first surface and the second surface, and is connected to the pad. Test pad g: the first surface i placed outside the component joint area

on. The first wire is disposed on the second surface, and the test pads are electrically connected to the corresponding partial pads by the first wires.曰 The above test carrier may further include a protective layer covering the surface wiring layer ′ and exposing the pads and the test pads. In the present invention, the above-mentioned slab is further provided with a wire disposed at the first table and connected to the first wire in parallel between the test piece and its corresponding partial pad. 'Based on the above invention, the inner layer is electrically connected to the test pad' or the test carrier is a single layer, and the electric coil is connected to the test. Below. Therefore, 1334490 ASEK1922-NEW-FINAL-TW-20070720 avoids the occurrence of wire breakage caused by the stress between the wires connected to the pads and the test pads. In this way, the reliability of the η piece and the test can be avoided, and the test can be avoided during the test. The carrier board has poor bonding between the package component and the test carrier board, and the wire breakage is misjudged as accuracy. The above-described features and advantages of the present invention will be described in more detail in conjunction with the accompanying drawings. [Embodiment] n-Lin invention-implementation of the financial amount of the figure is a cross-sectional view of the test carrier carrying a package component in FIG. Please clamp the test carrier 2〇0 to be applied to the test-package component 50. The test carrier includes a dielectric layer 21G, a plurality of pads 22 (), a connection line 232, and a plurality of test pads 24 And a plurality of first-wires, the dielectric layer 210 has a first surface and a second surface 214, and the first surface 212 has a component bonding area for the package. The pads 22 are, for example, in an array configuration that is located on the first surface 212 within the component landing 212a for engagement with the package member 50. The pad connection line 232 is located on the first surface 212 and is electrically connected to the interface 22A. It is worth mentioning that, in the present embodiment, the connection line 232 is located on the first surface 212 as an example, but the pad connection line 232 may also be disposed at other locations, such as the second surface 214. The test pad 240 is disposed on the first surface 212 outside the component land 212a and the first wire 252 is disposed on the second surface 214, and the test pad 240 1334490 ASEK1922-NEW-FINAL-TW-20070720 = by the first wire 252 The electrical connection to the corresponding portion of the interface is electrically connected to the test pad 24 by the first wire 252 of the second surface 214 of the dielectric layer 210. When the 50 is bonded to the pad 220, the first wire 252 is less susceptible to stress caused by the bonding of the package component 50 and the test carrier 200 to cause disconnection. ^ This will help to improve the reliability of the test carrier 200, which in turn ensures the accuracy of the test. 2C is a cross-sectional view showing another configuration of the test carrier and the package component of FIG. 2A. Referring to FIG. 2A and FIG. 2C, the test carrier 2 can further include a protective layer 260 disposed on the dielectric layer 210. The test carrier 200 is protected to expose the pad 220 for bonding the package component 5 and exposes the test pad 240 for testing. Further, the test carrier 2 may further include a plurality of first wires 234, The first surface 212 is disposed on the first surface 212 and is respectively connected between the test pad 240 and the corresponding partial pads 22A of the first wire 252. Another embodiment of the present invention will be described below with reference to the drawings. In another embodiment of the present invention, a test carrier carries a package component, and FIG. 3B is a cross-sectional view of another configuration of the test carrier and the package component of FIG. 3A. First, the test carrier 2A and The above test carrier 200 is substantially the same, and in the above embodiments and the present embodiment, the same or similar component numbers denote the same or similar components. The differences between the two embodiments will be described in detail below, and the same is not the same. Let me repeat 3A, the test carrier 200a of the present embodiment is different from the test carrier 200 described above at 1334490 ASEK1922-NE W-FINAL-T W-20070720. The test carrier 200a includes a plurality of dielectric layers 210, and more The inner layer circuit layer 250 replaces the first wire 252 and replaces the pad connection line 232 (please refer to FIG. 2A) and the second wire 234 with a surface layer 230.

Specifically, the inner layer circuit layer 250 is disposed between the two adjacent dielectric layers 210, and electrically connected to the test pad 240 and its corresponding partial pads 220, wherein the inner layer circuit layer 250 is, for example, a plurality of the above-mentioned The first wire 252 is composed of. Further, the surface wiring layer 230 is located at the outermost side of the dielectric layer 210, and the surface wiring layer 230 is composed of, for example, a plurality of the above-mentioned pad connection lines 232 (please refer to FIG. 2A) and the second wires 234. It is to be noted that in the present embodiment, a plurality of inner layer wiring layers 250 are exemplified, but only one inner wiring layer 25 may be disposed, and the present invention is not limited thereto. In addition, as shown in FIG. 3B, the test carrier may or may not be provided with the second wire 234 and only the inner layer 250 is connected to the test pad 24 and its corresponding partial pad 220.

As noted above, the test carrier of the present invention has been placed on the ΐ 2 conductor by replacing the conventional test carrier with a second or inner wiring layer disposed on the dielectric layer. SUb, when the difficult component is connected to the test, the electrical connection between the two is not easy to gj package. ^ The accuracy of the i-type carrier is still measured. Although the present invention has been disclosed in the above embodiments by way of example, it is not intended to be used as a limitation. 1334490 ASEK1922-NE W-FINAL-T W-20070720 The present invention is generally known to those skilled in the art without departing from the invention. Within the spiritual domain, when some changes and run-ups can be made, the scope of the invention is determined by the definition of the towel. [Simplified illustration] FIG. 1A is a conventional test carrier. Top view.

Figure 1B is a cross-sectional view of the test carrier of Figure 1A carrying a split element. 2A is a top plan view of a test carrier in accordance with an embodiment of the present invention. Figure 2A shows the test carrier carrying capacity of Figure 2A. For (4) another board and package components

Figure 3A is a cross-sectional view of a test carrier assembly in accordance with another embodiment of the present invention. Take the package 7G as a cross-sectional view of the test carrier and package components in Figure 3A. Configuration side

[Main component symbol description] 50: package component 100: test carrier 110: dielectric layer 120: pad 13 〇 = test pad 140: wire c S > 11 1334490 ASEK1922-NEW-FINAL-TW-20070720 150 : stress Concentration zone 112: surface 112a: component bonding zone 200a, 200: test carrier 210: dielectric layer 212: first surface 212a: component bonding region 214: second surface 220: pad 230: surface wiring layer 232: pad Connection line 234: second wire 240: test pad 250: inner layer circuit layer 252: first wire 260: protective layer 12

Claims (1)

1334490 ASEK1922-NEW-FINAL-TW-20070720 X. Patent application: ^ _ test carrier, with -_ joint area, rib carrying a ^ ^ test component for testing, including: An electric layer; a surface circuit layer 'is located at the outermost side of the dielectric layers; and a second layer between the two adjacent dielectric layers, and is electrically connected to the surface layer of the surface layer of the component ^ 'for engaging with the mounting component, and connecting the electrical wiring layer and the inner wiring layer; and connecting the multi-sided test pad of the table, and the side test pad is disposed outside the component bonding area The pads are electrically connected to a portion of the pads. The test carrier board as described in item 1 of the patent scope, further includes - covering the surface layer of the surface layer, and exposing the plurality of joints and the three parts as described in the patent scope In the carrier board, the inner j layer includes a plurality of first-wires for separately connecting the test files and the corresponding portions thereof. The test carrier of the third aspect of the invention, wherein the circuit layer includes a second wire, and the second wires are respectively associated with the wires and the Corresponding miscellaneous pads 5, such as the test carrier described in claim 1 of the patent application, wherein the 13 ASEK1922-NEW-FINAL-TW-20070720 pads are arranged in an array. Included in the six test carrier plates for testing a package component, the test carrier has a dielectric layer having a first surface and opposite thereto - a second surface 'the surface having the component bonding area The core carries the sealing member, the plurality of pads, the first table disposed in the bonding region of the component is configured to be engaged with the packaging component; and the bonding pad connection line is located at the first surface and the second At least one of the surfaces is electrically connected to the pads; a plurality of test pads are disposed on the component landing zone; and _ a plurality of first-leading greens are disposed on the second surface, and the The plurality of junctions are electrically connected to portions of the county by the first-wires. A working board as described in claim 6 further comprising a protective layer disposed on the first surface and exposing the test pads. &8> as in the test carrier of the scope of the patent application, further comprising a plurality of wires, the wire is placed on the first surface, and is respectively connected to the test wires in parallel with the first wires and The corresponding part is between the joints. 9. The test carrier of claim 6, wherein the pads are in an array configuration. -