200905222 ASEK1922-Νϋ V/-FIN AL-TW-2〇〇7〇72〇 九、發明說明： 【發明所屬之技術領域】 種 本發明是有關於—種測試載板，且特别 用於晶片接合之可靠度測試的測試載板。 ； 【先前技術】 ^積體電路或W的製造雜巾，不管是 段的製程’ _體電路以肢行電性的輯 = 的。母一個積體電路不管是在晶圓的型態或是 顶 態，都必須加以測試以確定其是否為良品以及確定 特性。隨著雜電路的產量謂地提高，積的^ 測試需求就更加地迫切。 疋且精確的 圖1A為習知一種測試載板之俯視圖，圖 中測試載板承載一封裝元件之剖示圖。請參照圖U 2 圖1B，習知測試載板100包括一介電層11〇 m、多個職墊m以及多條導線14G。介電層⑽口= 二表面112 ’而表面112具有—請接合區112a，/中接 陣列分佈於純接合區112a内。測試墊13G配= =n:之表面112上，且位於元件接合區112叫置= ς塾130，、接墊120透過配置於介電層11〇之 導線140電性連接。 之 封衣兀件5〇與兀件接合區112a内之接墊120電性連 接。使用者可㈣份的職墊130輸人—_訊號至封裝 200905222 A^HKiy^-^^vvr-FINAL-TW-20070720 元件50，並由另一部份的測試墊13〇讀取測試結果。 由於習知測試载板1〇〇之導線14〇是配置於介電層 110之表面112上，因此容易在封裝元件5〇與測試載板 接合後冗到結構上之應力集中或是外力作用，而使得導線 140在應力集中區15〇形成斷路，如此將$致在測試 法判斷測得的錯誤是由封裝元件5G與職載板刚之間的' ，合不f所造成的或是由測試載板⑽本身之斷線所点 試時度此可#度不佳的測試載板設計將直接影響測 【發明内容】 、表姑f發明提供—種測試载板，其測試麵接墊間之$ 連接；不易斷開，而具有較高的可靠度盥測 其具有多層結構，並㈣’在此以—種測試栽板， 墊。上述測試载板具有件性連接接墊與·< 件，以對射_、件接合區’用財載-封举- -表層線路層、至少職載板包括多個介電層 :塾。表層線路層位於介;;個接塾以及〜 元件接合，路層上，用以輿_ =塾配置於元 層與内層線略層。 由内層線路層電性連接至其 且測、藉 200905222200905222 ASEK1922-Νϋ V/-FIN AL-TW-2〇〇7〇72〇9, invention description: [Technical Field] The present invention relates to a test carrier, and particularly for wafer bonding Test carrier for reliability testing. [Prior Art] ^Integrated circuit or W made of swarf, regardless of the process of the segment ' _ body circuit with the electrical line of the limb =. A master circuit, whether in the form of a wafer or in a top state, must be tested to determine if it is a good product and to determine its characteristics. As the production of hybrid circuits is said to increase, the need for product testing is even more urgent. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1A is a top plan view of a conventional test carrier in which the test carrier carries a packaged component. Referring to FIG. U 2 FIG. 1B , the conventional test carrier 100 includes a dielectric layer 11 〇 m, a plurality of pads m, and a plurality of wires 14G. The dielectric layer (10) port = two surfaces 112' and the surface 112 has - the junction region 112a, / the intermediate array is distributed within the pure junction region 112a. The test pad 13G is disposed on the surface 112 of the ==n: and is located at the component bonding region 112. The pad 120 is electrically connected to the wire 140 disposed on the dielectric layer 11A. The sealing member 5 is electrically connected to the pad 120 in the die engaging portion 112a. The user can enter (4) the job pad 130 - the signal to the package 200905222 A^HKiy^-^^vvr-FINAL-TW-20070720 component 50, and the test result is read by another part of the test pad 13〇. Since the wire 14A of the conventional test carrier 1 is disposed on the surface 112 of the dielectric layer 110, it is easy to delay the structural stress concentration or external force after the package component 5 is bonded to the test carrier. Therefore, the wire 140 is broken in the stress concentration region 15,, so that the error measured by the test method is caused by the combination of the package component 5G and the carrier board, or by the test. When the carrier board (10) itself is disconnected, the test time can be used. The test board design with poor degree will directly affect the measurement. [Invention content], the model of the invention provides a test carrier board, and the test surface pads are $ connection; not easy to disconnect, but with high reliability, it has a multi-layer structure, and (4) 'here to test the board, pad. The test carrier has a component connection pad and a <piece, for the radiation, the component bonding area is used for the package--the surface layer, and at least the carrier board comprises a plurality of dielectric layers: 塾. The surface layer is located at the interface; the interface and the component are bonded to the layer, and the 舆_=塾 is disposed on the layer and the inner layer. Electrically connected to the inner layer, and measured and borrowed 200905222
At>bK.iy//'Nhsv/-FINAL-TW-20070720 上述測試載板更可包括-保護層’其覆蓋表層線路 層’並暴露出接墊以及測試墊。 f本發明之-實施例中’上述内層線路層包括多條第 -導線’用以分別連接測試墊以及其所對應的部份接塾， 而表層線路層則可包括多條第二導線，且第二導線分別與 第一導線並聯於測試墊以及其所對應的部份接墊之間。/、 本發明另提出-種測試載板，其為—單層板，用以測 試一封裝元件，測試載板包括一介電層'多個接墊、一接 墊，接線路、多個測試墊以及多條第—導線。介電層具有 一第一表面以及與其相對之一第二表面，第—表面丄^ —几件接合區’用以承載封裝7C件。聽可呈陣列配置於 凡件接合區_第—表面上，用以與封|元件接合攀 連接線路位於第一表面與第二表面至少其中之—上，並 性連接至接墊。賴娜置於元件接合區外的第—表 i綠t導線配置於第二表面上，且測試塾分別藉由又第一 導線而電性連接至其所對應的部份接墊。 亡述測試載板更可包括-保護層，其覆蓋表層線路 層’並暴露出接墊以及測試墊。 ，本發明之—實關中，上述_敏更包括 =線’配置於第-表面上，並分別與第—導線並聯於測 式塾Μ及其所對應的部份接墊之間。 触基於述’本發賴㈣層魏層雜接墊與測 : 或疋在測5式載板為單層板的情況下，將電性連接 塾與測試墊之第一導線配、目,丨#與 I乐令踝配置於測試载板之下方。因此，可 200905222At>bK.iy//'Nhsv/-FINAL-TW-20070720 The above test carrier may further include a protective layer 'which covers the surface wiring layer' and exposes the pads and the test pads. In the embodiment of the present invention, the above-mentioned inner layer circuit layer includes a plurality of first-wires for respectively connecting the test pads and corresponding partial interfaces, and the surface circuit layer may include a plurality of second wires, and The second wires are respectively connected in parallel with the first wires between the test pads and their corresponding partial pads. The invention further proposes a test carrier board, which is a single layer board for testing a package component, the test carrier board comprises a dielectric layer 'multiple pads, one pad, connecting lines, multiple tests Pad and multiple first-wires. The dielectric layer has a first surface and a second surface opposite thereto, and the first surface is used to carry the package 7C. The audible array is disposed on the lands of the lands of the phantoms for engaging the sealing elements on at least one of the first surface and the second surface, and is connected to the pads. The lining of the lining is placed on the second surface, and the test 塾 is electrically connected to the corresponding partial pads by the first wire. The dead test carrier may further include a protective layer covering the surface wiring layer and exposing the pads and the test pads. In the practice of the present invention, the above-mentioned _min further includes a = line disposed on the first surface, and is respectively connected with the first wire in parallel with the test 塾Μ and its corresponding partial pads. According to the description of the 'Beifa Lai (four) layer Wei layer mat and test: or 疋 test 5 type carrier is a single layer, the electrical connection 塾 and the test lead of the first lead, the purpose, 丨#与伊乐令踝 is placed below the test carrier. Therefore, 200905222
Abtusa yzz-iMu nV-FINAL-TW-20070720 避免連接於接墊與測試墊之間的導後香 載板之間的應力作用而產生斷線。如t到，牛與測試 的可靠度，並可聽職時將高測試載板 封裝元件與測試載板之間的接合不斷線誤判為 準確度。 民而提鬲測試載板的 為讓本發明之上述特徵和優點能更明顯易懂，下文特 舉實施例，並配合所附圖式，作詳細說明如下。 【實施方式】 圖2A為本發明一實施例中測試載板之俯視圖，圖2b 為圖Μ中測試載板承載一封裝元件之剖示圖。請參照圖 2Α及圖2Β，測試載板200可應用於測試_封裝元件知， 測试載板200包括-介電層21〇、多個接墊22q、一接塾連 接線路232、多個測試墊240以及多條第—導線252。 承上述，介電層210具有一第一表面212以及與其相 對之-第二表面214 ’第—表面212上具有一元件接合區 212a，用以承載封裝元件5〇。接墊22〇例如呈陣列配置， 其位於元件接合區212a内的第一表面212上，用以與封裝 元件50接合。接墊連接線路232位於第—表面212上，並 電性連接至触220。贿—提的是，_在本實施例中 以接墊連接線路232位於第一表面212上為例說明，但接 墊連接線路232亦可配置於其他位置，例如第二表面214 上。測試墊240配置於元件接合區212a外的第一表面212 上，而第一導線252配置於第二表面214上，且測試墊24〇 200905222 Λοηιν l yzz-iNn v^-FINAL-TW-20070720 分別藉由第一導線252而電, 220。 ί·生連接至其所對應的部 份接墊 # =於本實施例藉由位於介電層21〇之第二表面2 弟一 ¥線252電性連接接墊22〇與測試墊24〇，因封 裝元件50與接墊220接合時，第一導線252不易受 j 7L件5〇與測試載板2〇〇接合後的應力作用而產生斷線。^Abtusa yzz-iMu nV-FINAL-TW-20070720 Avoids the stress caused by the connection between the rear and the slab between the pads and the test pad. For example, the reliability of the cow and the test can be misjudged as the accuracy of the joint between the high test carrier package component and the test carrier. The above features and advantages of the present invention will become more apparent from the following detailed description. 2A is a top view of a test carrier in an embodiment of the present invention, and FIG. 2b is a cross-sectional view of the test carrier carrying a package component in the drawing. Referring to FIG. 2A and FIG. 2A, the test carrier 200 can be applied to a test package. The test carrier 200 includes a dielectric layer 21, a plurality of pads 22q, an interface 232, and a plurality of tests. Pad 240 and a plurality of first conductors 252. In the above, the dielectric layer 210 has a first surface 212 and a second surface 214' opposite the surface 212 having an element land 212a for carrying the package component 5'. The pads 22 are, for example, in an array configuration on the first surface 212 within the component landing 212a for engagement with the package component 50. The pad connection line 232 is located on the first surface 212 and is electrically connected to the contact 220. The bribe is provided in the present embodiment as an example in which the pad connection line 232 is located on the first surface 212, but the pad connection line 232 may also be disposed at other locations, such as the second surface 214. The test pad 240 is disposed on the first surface 212 outside the component land 212a, and the first wire 252 is disposed on the second surface 214, and the test pad 24〇200905222 Λοηιν l yzz-iNn v^-FINAL-TW-20070720 respectively Powered by the first wire 252, 220. ί·生接接接接接接垫#= In this embodiment, the pad 22〇 and the test pad 24〇 are electrically connected by the second surface 2 of the dielectric layer 21〇 When the package component 50 is bonded to the pad 220, the first wire 252 is less susceptible to the stress caused by the bonding of the j 7L member 5〇 and the test carrier 2〇〇. ^
此’將有助於提高測試载板的可靠度，進而可確 行測試時的準確度。 ’、進 圖2C為圖2Α中測試載板與封裝元件之另—種配置方 式剖視圖。請參照圖2Α及圖2C，上述測試載板更可 包括一保護層260，配置於介電層21()上以保護測試載板 2〇γ，且暴露出接墊220以供封裝元件5〇接合，並暴露出 測試墊240以供測試。此外，測試載板2〇〇更可 第二導線234 ’配置於第—表面212上，並分別與第一導 線252並聯於測试塾240以及其所對應的部份接墊do之 間。 以下配合圖式說明本發明之另一實施例。圖3Α為本 發明另一實施例中測試載板承載一封裝元件之剖視圖，圖 3Β為圖3Α中測試載板與封裝元件之另一種配置方式剖視 圖。需先說明的是’測試載板2〇〇a與上述測試載板200 大致相同，且在上述實施例與本實施例中，相同或相似的 元件標號代表相同或相似的元件。以下將針對兩實施例不 同之處詳加說明’相同之處便不再贅述。請參照圖3A，本 實施例之測試載板200a與上述測試載板200之不同處在 200905222 .vV-FINAL-TW-20070720 於，測試載板200a包括多個介電層21〇，且以多個内層線 路層250取代第一導線252，並以一表層線路層23〇取代 接墊連接線路232 (請參照圖2A)以及第二導線234。 c 具體而言，内層線路層250配置於兩相鄰之介電層21〇 之間’其電性連接測試墊240及其所對應的部份接墊22〇， 其中内層線路層250例如由多條上述之第一導線252所組 成。另外，表層線路層230位於介電層21〇的最外側，其 中表層線路層230例如是由多條上述之接塾連接線路232 (請參照圖2A)與第二導線234所構成。 值得注意的是，在本實施例中雖以多個内層線路層 250為例說明’但亦可僅配置一内層線路層25〇，本發明並 =另外’如圖3B所示，測試載板萬亦可不 ^弟—¥線234而僅以内層線路層謂連接測試塾· 及其所對應的部份接墊22〇。 练上所述，本發明之測試載板以配置於介 表面的第-導線或内層線路層取代習知測試載板；置 =塾之間的電性連接不易因封裝元件與= 如此可提高接塾與測試墊之間之電性== 板較高。另外，由於測試載 ，線誤判為封;;件====板本身 兩測試載板的準確度。 不良，而提 雖然本發明已以實施例揭露如上，然其並非用以限定 200905222 .— '^-FINAL-TW-20070720 ^明’任何所屬技術領域中具有通常知識者，在不脫離 ^明之精神和範_，當可作些許之更動與潤飾，因此 ^明之域視後附之申料利範_界定者為 竿0 【圖式簡單說明】 圖為習知一種測試載板之俯視圖。 圖1B為圖1A中測試載板承載一封裝元件之剖視圖。 圖2A為本發明一實施例中測試載板之俯視圖。 圖2B為圖2A中測試載板承載一封裝元件之剖視圖。 圖2C為圖2A中測試载板與封裝元件之另—種配 式剖視圖。 置万 Ώ A為本發明另—實施例中測試載板承— 件之剖視圖。 圖3Β為圖3Α中測試載板與封裝元件之另—種配 式剖視圖^ 【主要元件符號說明】 5〇 :封裝元件 100 :測試载板 110 :介電層 120 :接墊 130 :測試墊 140 :導線 11 200905222 ./-FINAL-TW-20070720 150 ： 應力集中區 112 ： 表面 112a :元件接合區 200a 、200 .測試載板 210 ： 介電層 212 ： 第一表面 212a :元件接合區 214 ： 第二表面 220 ： 接墊 230 ： 表層線路層 232 ： 接墊連接線路 234 ： 第二導線 240 ： 測試墊 250 ： 内層線路層 252 ： 第一導線 260 ： 保護層 12This will help to improve the reliability of the test carrier and thus the accuracy of the test. Figure 2C is a cross-sectional view showing another configuration of the test carrier and package components of Figure 2A. Referring to FIG. 2A and FIG. 2C, the test carrier may further include a protective layer 260 disposed on the dielectric layer 21 () to protect the test carrier 2 〇 γ and expose the pad 220 for the package component 5 The test pads 240 are joined and exposed for testing. In addition, the test carrier 2 is further disposed on the first surface 212 and is respectively connected in parallel with the first conductive line 252 between the test cartridge 240 and its corresponding partial pad do. Another embodiment of the present invention will now be described with reference to the drawings. 3 is a cross-sectional view showing a test carrier carrying a package component in another embodiment of the present invention, and FIG. 3 is a cross-sectional view showing another configuration of the test carrier and the package component in FIG. It is to be noted that the 'test carrier board 2'a is substantially the same as the test board 200 described above, and the same or similar element numbers in the above embodiments and the present embodiment represent the same or similar elements. In the following, the differences between the two embodiments will be explained in detail, and the details will not be described again. Referring to FIG. 3A, the difference between the test carrier 200a of the present embodiment and the test carrier 200 is at 200905222 .vV-FINAL-TW-20070720. The test carrier 200a includes a plurality of dielectric layers 21〇, and more The inner layer circuit layer 250 replaces the first wire 252 and replaces the pad connection line 232 (please refer to FIG. 2A) and the second wire 234 with a surface layer layer 23A. Specifically, the inner circuit layer 250 is disposed between two adjacent dielectric layers 21 ' electrically connected to the test pad 240 and its corresponding partial pads 22 , wherein the inner circuit layer 250 is, for example, The first wire 252 is composed of the above. Further, the surface wiring layer 230 is located at the outermost side of the dielectric layer 21A, and the surface wiring layer 230 is composed of, for example, a plurality of the above-described interface connecting lines 232 (see Fig. 2A) and the second wiring 234. It should be noted that in the present embodiment, although a plurality of inner layer circuit layers 250 are taken as an example, 'but only one inner layer circuit layer 25 亦可 may be disposed, and the present invention is another 'as shown in FIG. 3B. Alternatively, the line 234 may be connected to the test layer 及其 and its corresponding partial pads 22 仅. As described above, the test carrier of the present invention replaces the conventional test carrier with a first-conductor or inner-layer circuit layer disposed on the interface surface; the electrical connection between the electrodes is not easily improved by the package component and the = The electrical property between the crucible and the test pad == the plate is higher. In addition, due to the test load, the line is mistakenly judged as a seal;; piece ==== plate itself The accuracy of the two test carriers. </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; And Fan _, when you can make some changes and retouching, so the scope of the Ming dynasty is attached to the application of the metric _ defined as 竿 0 [Simple diagram of the diagram] The picture shows a top view of a test carrier. 1B is a cross-sectional view of the test carrier of FIG. 1A carrying a package component. 2A is a top plan view of a test carrier in accordance with an embodiment of the present invention. 2B is a cross-sectional view of the test carrier of FIG. 2A carrying a package component. Figure 2C is a cross-sectional view of another configuration of the test carrier and package components of Figure 2A. 。 Ώ A is a cross-sectional view of a test carrier support member in another embodiment of the invention. 3 is a cross-sectional view of another type of test carrier and package component in FIG. 3^ [Major component symbol description] 5〇: package component 100: test carrier 110: dielectric layer 120: pad 130: test pad 140 : Conductor 11 200905222 ./-FINAL-TW-20070720 150 : Stress concentration region 112 : Surface 112a : Component junction region 200a , 200 . Test carrier 210 : Dielectric layer 212 : First surface 212 a : Component junction region 214 : Two surfaces 220 : pads 230 : surface layer 232 : pad connection lines 234 : second wires 240 : test pads 250 : inner layer circuit layer 252 : first wires 260 : protective layer 12