JP2011165956A - Ball grid array substrate and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a ball grid array substrate which can steadily deliver and receive a test signal from a side surface without rise in cost. <P>SOLUTION: The ball grid array substrate 1 is provided with a semiconductor chip 2, on the upper surface and a plurality of conductive balls 4 on the lower surface opposing the upper surface. The ball grid array substrate includes a first terminal, arranged on the upper surface and connected to the semiconductor chip 2, wiring electrically connected to the first terminal, and an insulating portion covering the wiring. The wiring has an exposed surface 112a exposed from the insulating portion on a side surface connecting the upper surface and the lower surface, and the first wiring width of the exposed surface 112a is larger than the wiring width of the wiring covered with the insulating portion. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a ball grid array substrate and a semiconductor device including the ball grid array substrate.

  A BGA (ball grid array) substrate has a plurality of external connection terminals arranged in a plane arrangement on the surface opposite to the semiconductor chip mounting surface. For example, Patent Document 1 discloses the structure of a BGA substrate. The semiconductor device described in Patent Document 1 is characterized in that an external electrode and a test terminal are provided adjacent to each other on the main surface, and the internal conductor and the test terminal are connected via the external electrode. That is, the example of the BGA board | substrate with which all the terminals are arrange | positioned on the same surface is disclosed.

  Patent Document 2 discloses a BGA package in which a test pad electrically connected to a bump is disposed on a side surface. In such a BGA package, even if the size of the solder bump is reduced, the test pad on the side surface is not affected, so that a pin short during the test can be prevented.

  As another BGA substrate structure, Patent Document 3 discloses a BGA substrate in which a plating wire is exposed on the side surface.

Japanese Patent Laid-Open No. 11-072534 JP 11-17058 A JP 2001-274283 A

  Semiconductor devices are required to be reduced in size in response to demands such as product miniaturization and cost reduction. However, even if the size of the semiconductor device is reduced, it is preferable that the number of signal terminals is not reduced as much as possible while securing the test terminals. In order to realize this, a method of passing a test signal from the side surface of the semiconductor device as in Patent Document 2 is considered. However, although this method can reduce the number of test terminals from the surface, it is necessary to form a new terminal on the side surface, which increases the cost. Furthermore, when an additional terminal is provided, there is a concern about deterioration of characteristics. Further, a method of inspecting electrical characteristics using a plated wire exposed on the side surface, such as a BGA substrate described in Patent Document 3, is also conceivable. However, with this method, it is difficult to perform a stable test with a small area exposed on the side surface.

  In the following, means for solving the problems will be described using the reference numerals used in the embodiments for carrying out the invention in parentheses. This symbol is added to clarify the correspondence between the description of the claims and the description of the mode for carrying out the invention, and the technical scope of the invention described in the claims. Must not be used to interpret

  The present invention is a ball grid array substrate (1) in which a semiconductor chip (2) is mounted on an upper surface and a plurality of conductive balls (4) are mounted on a lower surface opposite to the upper surface. A first terminal (12) connected to the chip (2), a wiring (20) electrically connected to the first terminal (12), and an insulating part (30) covering the wiring (20) are provided. The wiring (20) has an exposed surface (112a) exposed from the insulating portion (30) on the side surface connecting the upper surface and the lower surface, and the first wiring width (W3) of the exposed surface (112a) is the insulating portion. It is wider than the wiring width (W1) of the wiring covered with (30). In such a ball grid array substrate (1), since the cross-sectional area of the wiring (20) exposed from the side surface is large, the probe can stably contact from the side surface.

  The semiconductor device (5) of the present invention comprises the ball grid array substrate (1) of the previous paragraph, a semiconductor chip (2) mounted on the upper surface, and a first conductive ball (4) mounted on the lower surface. To do. The semiconductor chip (5) transmits signals to and from the test apparatus through the exposed surface (112a).

  The ball grid array substrate of the present invention can pass test signals stably from the side without increasing costs.

FIG. 1 is a plan view of a semiconductor device 5 including a BGA substrate 1 of the present invention. FIG. 2 is a side view of the semiconductor device 5 of FIG. 1 viewed from the Y direction. 3 is a cross-sectional view taken along the line AA in FIG. FIG. 4 is a perspective view showing the upper wiring 23 formed on the insulating portion 32. FIG. 5 is a perspective view showing the wiring 25 that is not used in the test.

  Hereinafter, a BGA (ball grid array) substrate according to an embodiment of the present invention will be described with reference to the accompanying drawings.

  FIG. 1 is a plan view of a semiconductor device 5 including a BGA substrate 1 of the present invention. FIG. 2 is a side view of the semiconductor device 5 of FIG. 1 viewed from the Y direction. Referring to FIGS. 1 and 2, the semiconductor device 5 includes a BGA substrate 1, a semiconductor chip 2, a plurality of bonding wires 3, and a plurality of conductive balls 4. In FIG. 1, the conductive balls 4 not on the surface of the BGA substrate 1 and the wirings connected to the conductive balls 4 are illustrated by dotted lines.

  The BGA substrate 1 is a ball grid array substrate on which a semiconductor chip 2 is mounted on an upper surface and a plurality of conductive balls 4 are mounted on a lower surface facing the upper surface. The BGA substrate 1 includes a plurality of upper terminals for connection to a plurality of electrode pads (not shown) of the semiconductor chip 2, a plurality of lower terminals for connection to a plurality of conductive balls 4, each upper terminal, And a plurality of wirings connecting the lower terminals. Referring to the side view of FIG. 2, the BGA substrate 1 has a two-layer wiring structure, and a part of these wirings (a wiring part 23, a wiring part 25, etc. described later) is exposed on the side surface. The BGA substrate 1 may have a single-layer wiring structure or a multilayer wiring structure of three or more layers.

  The semiconductor chip 2 includes a circuit for realizing a desired function, and has a plurality of electrode pads on the surface for connecting the circuit and the BGA substrate 1. Each of the plurality of bonding wires 3 electrically connects the electrode pad of the semiconductor chip 2 and the upper terminal of the BGA substrate 1. The plurality of conductive balls 4 are terminals for external connection for the semiconductor device 5 to exchange signals with the external device, and are arranged in a surface arrangement on the lower surface. In the present embodiment, the BGA substrate 1 and the semiconductor chip 2 are connected by a plurality of bonding wires 3, but may be connected by wireless bonding such as flip chip bonding or tape automated bonding.

  Details of the BGA substrate 1 will be described. 3 is a cross-sectional view taken along the line AA in FIG. Referring to FIG. 3, the BGA substrate 1 includes a lower terminal 11, an upper terminal 12, a wiring 20, and an insulating unit 30. In FIG. 3, configurations other than the lower terminal 11, the upper terminal 12, the wiring 20, and the insulating unit 30 are omitted. The lower terminal 11 is disposed on the lower surface of the BGA substrate 1 and connected to the conductive ball 4. The upper terminal 12 is disposed on the upper surface of the BGA substrate 1 and is connected to the semiconductor chip 2 through the bonding wires 3. The wiring 20 electrically connects the lower terminal 11 and the upper terminal 12. The insulating unit 30 covers and protects the wiring 20.

  The wiring 20 includes a lower wiring 21, a via 22, and an upper wiring 21. The insulating unit 30 includes an insulating unit 31, an insulating unit 32, and an insulating unit 33. The lower wiring 21 is a wiring formed in a pattern parallel to the upper surface and the lower surface of the BGA substrate 1. The lower wiring 21 is formed on the insulating portion 31 and is connected to the lower terminal 11. The lower terminal 11 is covered with the insulating portion 31 except for a part of the upper and lower surfaces so that the lower terminal 11 can be electrically connected to the conductive ball 4 and the lower wiring 21.

  The via 22 is formed on the lower wiring 21 and connects the lower wiring 21 and the upper wiring 23 in the thickness direction of the BGA substrate 1. The lower wiring 21 and the via 22 are covered with an insulating portion 32.

  Similar to the lower wiring 21, the upper wiring 23 is a wiring formed in a pattern parallel to the upper surface and the lower surface of the BGA substrate 1. The upper wiring 23 is formed on the insulating portion 32 and is connected to the upper terminal 12. The upper wiring 23 and the upper terminal 12 are covered with the insulating portion 33. The upper terminal 12 is formed on the upper wiring 23 and is covered with the insulating portion 33 except for a part of the upper surface so that it can be electrically connected to the semiconductor chip 2.

  FIG. 4 is a perspective view showing the upper wiring 23 formed on the insulating portion 32. FIG. 4 corresponds to the wiring shown by B in FIG. Referring to FIG. 4, the upper wiring 23 includes a wiring part 100 and a plated wire part 110. The wiring unit 100 transmits a signal passed between the semiconductor chip 2 and the conductive ball 4. The plated wire portion 110 is necessary for the wiring 20 and discharges electric charges from the BGA substrate 1. Furthermore, the plated wire portion 110 can stably pass a test signal passed between the semiconductor chip 2 and an external test apparatus.

  The wiring part 100 includes a connection part 100a and a connection part 100b. The connection part 100 a is a part to which the via 22 surrounded by the insulating part 32 is connected on the lower surface of the wiring part 100. That is, the connection part 100 a is connected to the lower terminal 11 through the via 22 and the lower wiring 21. The connection part 100 b is a part to which the upper terminal 12 surrounded by the insulating part 33 is connected on the upper surface of the wiring part 100. The wiring unit 100 transmits a signal passed between the semiconductor chip 2 and the conductive ball 4 via the connection unit 100a and the connection unit 100b. The wiring width W1 of the wiring part 100 is a width in a direction parallel to the upper surface and the lower surface of the BGA substrate 1 that is orthogonal to the signal transmission direction (wiring length direction) connecting the connecting part 100a and the connecting part 100b. is there.

  The plated wire part 110 includes a plated wire part 111 and a terminal part 112. The plated wire portion 111 is a wire having a wiring width W2 that connects the wiring portion 100 and the end portion 112. The wiring width W2 is a width that allows the wiring portion 110 to be pulled out to the side surface of the BGA substrate 1 so as not to contact the adjacent wiring, and is preferably narrower than the wiring width W1. When the wiring width W2 is narrower than the wiring width W1, the end portion 112 can be easily pulled out to the side surface of the BGA substrate 1 while avoiding contact with other wiring. However, the wiring width W2 may be the same as the wiring width W1 if a sufficient distance from other wiring can be maintained.

  The end portion 112 includes an exposed surface 112a that is connected to the plated wire portion 111 and exposed from the insulating portion 33 on the side surface. The BGA substrate 1 can release charges by exposing the end portion 112 to the outside. The area of the exposed surface 112a is larger than the cross-sectional area of the other wiring included in the wiring 20 covered with the insulating portion 30. In other words, the wiring width W3 of the exposed surface 112a is wider than other wiring widths of the wiring 20 covered with the insulating portion 30. Specifically, the wiring width W3 of the exposed surface 112a is larger than the wiring width W1, and is a width that does not contact other adjacent wirings. Since the wiring width W3 is larger than the wiring width W1, a probe for testing the semiconductor device 5 can stably come into contact. That is, the end portion 112 has two effects of being able to discharge electric charges and being able to stably contact the probe. The end portion 112 only needs to be formed with the wiring width W3 in the above-described range so that the area of the exposed surface 112a is increased. The planar shape of the end portion 112 is any shape such as a circle or a rectangle. Also good. Moreover, the wiring part 110 should just be connected with the wiring part 100, and the place connected is determined based on the whole wiring pattern. In FIG. 3, the upper wiring 23 is exposed by including the plated wire portion 110, but the lower wiring 21 may be exposed by including the plated wire portion 110. That is, it is only necessary that at least one of the lower wiring 21 and the upper wiring 23 is exposed from the side surface in the wiring 20 that electrically connects the lower terminal 11 and the upper terminal 12.

  As described above, the BGA substrate 1 includes a plurality of upper terminals for connecting to the semiconductor chip 2 on the upper surface, a plurality of lower terminals for connecting to the plurality of conductive balls 4 on the lower surface, the upper terminals, And a plurality of wirings connecting the lower terminals. In the BGA substrate 1, a plurality of wirings connecting the upper terminals and the lower terminals are exposed on the side surfaces, but each wiring may not have the end portion 112 shown in FIG. That is, in the wiring that is not used for the test among the plurality of wirings, the wiring width of the exposed surface exposed from the side surface is preferably narrower than the wiring width covered by the insulating portion 30. For example, since the wiring 25 in FIG. 2 is a wiring that is not used for the test, it has an exposed surface 210a that is smaller than the exposed surface 112a of the wiring 23.

  FIG. 5 is a perspective view showing the wiring 25 that is not used in the test. FIG. 5 corresponds to the wiring indicated by C in FIG. Referring to FIG. 5, the wiring 25 includes a wiring part 200 and a plated wire part 210. Similar to the wiring unit 100, the wiring unit 200 transmits a signal transferred between the semiconductor chip 2 and the conductive ball 4. The plated wire portion 210 is a wiring that discharges charges from the BGA substrate 1, as with the plated wire portion 110. However, unlike the plated wire portion 110, the plated wire portion 210 does not pass a test signal.

  The wiring part 200 includes a connection part 200a and a connection part 200b. The connection part 200 a is a part to which the via surrounded by the insulating part 32 is connected on the lower surface of the wiring part 200. The connection part 200 b is a part to which the upper terminal surrounded by the insulating part 33 is connected on the upper surface of the wiring part 200. The wiring unit 200 transmits a signal passed between the semiconductor chip 2 and the conductive ball 4 via the connection unit 200a and the connection unit 200b. The wiring part 200 has a wiring width W <b> 1 like the wiring part 100.

  The plated wire part 210 is connected to the wiring part 200 and includes an exposed surface 210a exposed from the insulating part 33 on the side surface. The plated wire portion 210 has a wiring width W2 like the plated wire portion 111. That is, the plated wire portion 210 can easily pull out the exposed surface 210a to the side surface of the BGA substrate 1 without contacting the adjacent wiring. The exposed surface 210a of the plated wire portion 210 is exposed to the outside, so that the BGA substrate 1 can release charges. The plated wire portion 210 may have any planar shape as long as the exposed surface 212a can be exposed from the side surface. Furthermore, the plating wire part 210 should just be connected with the wiring part 200, and the connection place is determined based on the whole wiring pattern.

  Further, the BGA substrate 1 of the present embodiment may be further laminated with a wiring on the upper wiring 23, and in that case, the laminated wiring connects the upper wiring 23 and the upper terminal 12. Further, the BGA substrate 1 may be a single layer that does not include the lower wiring 21. In this case, the upper wiring 23 is directly connected to the lower terminal 11 and the upper terminal 12.

  As described above, since the BGA substrate 1 of the present invention has the exposed surface 112a having the wide wiring width W3 on the side surface, the probe connected to the test apparatus can be contacted stably from the side surface. Particularly, in the plated wire portion 110 including the exposed surface 112a, since the wiring portion 111 may have the usual wiring width W2, the end portion 112 can be easily set at the stage of designing the wiring, and the wiring design is greatly changed. There is no need. In other words, the BGA substrate 1 according to the present invention uses the plated wire portion 110, so that it is not necessary to newly draw a wiring at a place where the design is dense, thereby producing an effect that does not cost. That is, the BGA substrate 1 of the present invention can easily provide the exposed surface 112a as a test terminal on the side surface without increasing the cost, and can stably pass a test signal from the exposed surface 112a. be able to.

  The semiconductor device 5 on which such a BGA substrate 1 is mounted can easily pass a test signal to and from the test device via the exposed surface 112a on the side surface. As an inspection method for the semiconductor device 5, a probe connected to a test device is brought into contact with the exposed surface 112 a of the BGA substrate 1, and then the test device outputs a test signal through the probe. Then, the semiconductor device 5 outputs a signal based on the signal, and the test device performs the determination based on the output signal.

DESCRIPTION OF SYMBOLS 1 BGA board | substrate 2 Semiconductor chip 3 Bonding wire 4 Conductive ball 5 Semiconductor device 11 Lower terminal 12 Upper terminal 20 Wiring 21 Lower wiring 22 Via 23 Upper wiring 25 Wiring 30 Insulating part 31 Insulating part 32 Insulating part 33 Insulating part 100 Wiring part 100a Connection portion 100b Connection portion 110 Plating wire portion 111 Plating wire portion 112 Terminal portion 112a Exposed surface 200 Wiring portion 200a Connection portion 200b Connection portion 210 Plating wire portion 210a Exposed surface W1 Wiring width W2 Wiring width W3 Wiring width

Claims (5)

A ball grid array substrate on which a semiconductor chip is mounted on an upper surface and a plurality of conductive balls are mounted on a lower surface facing the upper surface,
A first terminal disposed on the upper surface and connected to the semiconductor chip;
Wiring electrically connected to the first terminal;
An insulating portion covering the wiring,
The wiring is
On the side surface connecting the upper surface and the lower surface, and having an exposed surface exposed from the insulating portion,
The ball grid array substrate, wherein the first wiring width of the exposed surface is wider than the wiring width of the wiring covered with the insulating portion. The ball grid array substrate according to claim 1,
A second terminal disposed on the lower surface and connected to the first conductive ball, wherein the first terminal and the second terminal are electrically connected by the wiring;
The wiring is
A planar wiring pattern formed parallel to the upper surface and the lower surface;
A first wiring portion connecting the first terminal and the planar wiring;
A second wiring portion that connects the second terminal and the planar wiring;
The planar wiring is
A third wiring portion having a first connecting portion to which the first wiring portion is connected and a second connecting portion to which the second wiring portion is connected;
A fourth wiring part connected to the third wiring part and including the exposed surface;
The ball grid array substrate, wherein the first wiring width is wider than the second wiring width of the third wiring portion. The ball grid array substrate according to claim 2,
The fourth wiring part is
A terminal portion including the exposed surface;
A fifth wiring part connected to the terminal part and connected to the third wiring part;
The ball grid array substrate, wherein a third wiring width of the fifth wiring portion is narrower than the second wiring width. A ball grid array substrate according to any one of claims 1 to 3,
A ball grid array substrate satisfying at least one of the first terminal and the first wiring portion being the same, and the second terminal and the second wiring portion being the same. The ball grid array substrate according to any one of claims 1 to 4,
The semiconductor chip mounted on the upper surface;
The first conductive ball mounted on the lower surface;
The semiconductor chip transmits a signal to and from a test apparatus through the exposed surface.

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