JP2011134789A - Semiconductor device, and printed circuit board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that eliminates a shortage of electrodes to a printed circuit board, and a printed circuit board mounted with the same. <P>SOLUTION: An internal wiring of a semiconductor package substrate 1, a solder bump 2, and lower-face-side pins 4, 5 form a first signal transmission path group between a semiconductor chip 3 and a wiring pattern of a printed circuit board 11. The internal wiring of the semiconductor package substrate 1, the solder bump 2, and a plurality of conductor patterns 22 of flexible boards 6A, 6B form a second signal transmission path group, different from the first signal transmission path group, between the semiconductor chip 3 and the wiring pattern of the printed circuit board 11. The semiconductor package substrate 1 and the wiring pattern of the printed circuit board 11 are electrically connected via two types of signal transmission path groups of the first signal transmission path group and the second signal transmission path group. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  In the present invention, for example, a semiconductor device having a plurality of electrodes arranged at intervals such as a BGA (Ball Grid Array), a PGA (Pin Grid Array), or an LGA (Land Grid Array), and the semiconductor device are mounted. Related to printed wiring boards.

  FIG. 11 is a cross-sectional view showing a conventional BGA type semiconductor device. In FIG. 11, a semiconductor chip 103 is provided on the upper surface of a resin-made semiconductor package substrate 101 via a plurality of solder bumps 102. A plurality of solder balls 104 arranged in a lattice pattern are provided on the lower surface of the semiconductor package substrate 101. The semiconductor package substrate 101 is electrically and mechanically connected to the printed wiring board 111 via a plurality of solder balls 104.

  Here, the thermal expansion coefficients of the semiconductor package substrate 101, the semiconductor chip 103, and the printed wiring board 111 are different. Thereby, the thermal expansion distances in the lateral direction of the semiconductor package substrate 101, the semiconductor chip 103, and the printed wiring board 111 are as indicated by arrows A1 to C1 in FIG.

  As shown in FIG. 11, the difference between the lateral thermal expansion distance of the semiconductor package substrate 101 and the lateral thermal expansion distance of the semiconductor chip 103 is relatively large. For this reason, when a relatively large semiconductor chip 103 is mounted on the semiconductor package substrate 101 with the solder bumps 102, the thermal expansion distances (arrows A1 and B1) differ particularly around the semiconductor chip 103, and a relatively large stress is applied to the solder bumps 102. (Shear stress) may occur, and the solder bump 102 may be disconnected.

  Next, FIG. 12 is a cross-sectional view showing another example of a conventional BGA type semiconductor device. 12, the semiconductor device of this example uses a ceramic semiconductor package substrate 201 instead of the semiconductor package substrate 101 of the example of FIG. Other configurations are the same as those of the semiconductor device in the example of FIG.

  In the BGA type semiconductor device shown in FIG. 12, the thermal expansion coefficient of the ceramic semiconductor package substrate 201 and the thermal expansion coefficient of the semiconductor chip 103 are relatively close values. This reduces the difference between the thermal expansion distances (arrows A2 and B2) between the semiconductor package substrate 201 and the semiconductor chip 103 as compared with the BGA type semiconductor device shown in FIG. Is done.

  However, in the BGA type semiconductor device shown in FIG. 12, the difference between the thermal expansion coefficient of the semiconductor package substrate 201 and the thermal expansion coefficient of the printed wiring board 111 is relatively large. For this reason, a relatively large stress (shear stress) is generated in the solder ball 104 especially around the semiconductor package substrate 201, and the solder ball 104 may be disconnected.

  Next, FIG. 13 is a cross-sectional view showing a conventional PGA type semiconductor device. 13, in the PGA type semiconductor device of this example, a plurality of lower surface side pins 304 and a plurality of lower surface side pins 305 are used instead of the plurality of solder balls 104 of the example of FIG. The lower surface side pin 304 is a pin with a flange, and the lower surface side pin 305 is a pin without a flange. Other configurations are the same as those of the BGA type semiconductor device in the example of FIG. In the PGA type semiconductor device of FIG. 13, the difference in thermal expansion distance (arrows B3 and C3) between the semiconductor package substrate 301 and the printed wiring board 111 is absorbed by the deformation of the lower surface side pins 304 and 305.

  Next, for example, in a conventional semiconductor device as shown in Patent Document 1, a composite (stacked) semiconductor package having a two-layer structure is used. This composite type semiconductor package has a structure in which a QFP (Quad Flat Package) type semiconductor package is disposed above a PGA type semiconductor package. This composite semiconductor package has a QFP electrode (first pin) and a PGA electrode (second pin). Both these electrodes are fixed by soldering to the solder pads of the printed wiring board.

JP-A-6-163792

  Here, the PGA type semiconductor device as shown in FIG. 13 has a smaller number of electrodes (connection terminals) than the BGA type semiconductor device as shown in FIGS. Specifically, the number of electrodes of a general 1.27 mm pitch staggered lattice in a PGA type semiconductor device is only about 1/3 of the number of electrodes of a general 1 mm pitch square lattice in a BGA type semiconductor device. In some cases, the electrodes were insufficient.

  In addition, it is desirable to reduce the manufacturing cost by reducing the size of the semiconductor package substrate even in the BGA type semiconductor device in which the resin semiconductor package substrate 101 and the solder ball 104 are combined and the LGA type semiconductor device, Accordingly, the number of electrodes also decreases. For this reason, the solder balls 104 of the BGA type semiconductor device and the electrode pads (not shown) of the LGA type semiconductor device may be insufficient.

  Furthermore, the conventional device as shown in Patent Document 1 is a combination of two types of semiconductor packages to improve the degree of integration, the QFP electrode is electrically connected to the QFP semiconductor chip, and the PGA electrode is The structure is electrically connected to a PGA semiconductor chip. Therefore, the QFP electrode and the PGA electrode are electrically connected to different semiconductor chips, and the shortage of electrodes in the PGA semiconductor chip cannot be resolved.

  The present invention has been made in order to solve the above-described problems, and a semiconductor device capable of solving the shortage of electrodes between the printed wiring board and a printed wiring board on which the semiconductor device is mounted. The purpose is to obtain.

  The semiconductor device according to the present invention includes at least one of a single semiconductor chip and a plurality of semiconductor chips, a first main surface, and a second main surface that is a back surface of the first main surface and is disposed to face the printed wiring board. A semiconductor package substrate on which at least one of the first main surface and the second main surface is provided with the semiconductor chip; and a semiconductor package substrate provided on the second main surface of the semiconductor package substrate and spaced apart from each other. A plurality of principal surface side electrodes for forming a first signal transmission path group between the wiring pattern of the printed wiring board and the semiconductor chip, the plane of the semiconductor package substrate The first signal transmission path group differs between the wiring pattern of the printed wiring board and the semiconductor chip. That in which further comprising a plurality of outer peripheral side electrode for forming a second signal transmission path group.

  According to the semiconductor device of the present invention, the second signal transmission path group different from the first signal transmission path group by the plurality of main surface side electrodes is formed between the wiring pattern of the printed wiring board and the semiconductor chip. Since the plurality of outer peripheral electrodes are provided on the outer peripheral portion in plan view of the semiconductor package substrate, it is possible to eliminate the electrode shortage with the printed wiring board.

1 is a cross-sectional view showing a PGA type semiconductor device according to a first embodiment of the present invention. It is a top view which shows the flexible substrate of FIG. It is sectional drawing which shows the PGA type semiconductor device by Embodiment 2 of this invention. It is a perspective view which shows the package substrate of FIG. It is sectional drawing which shows the PGA type semiconductor device by Embodiment 3 of this invention. It is a top view which shows the flexible substrate by Embodiment 4 of this invention. It is a top view which shows the flexible substrate by Embodiment 5 of this invention. It is a top view which shows the flexible substrate by Embodiment 6 of this invention. It is a perspective view which shows the PGA type semiconductor device by Embodiment 7 of this invention. It is a top view which expands and shows the circumference | surroundings of the outer peripheral side pin of FIG. It is sectional drawing which shows the conventional BGA type semiconductor device. It is sectional drawing which shows the other example of the conventional BGA type semiconductor device. It is sectional drawing which shows the conventional PGA type semiconductor device.

Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.
Embodiment 1 FIG.
FIG. 1 is a sectional view showing a PGA type semiconductor device according to the first embodiment of the present invention. FIG. 2 is a plan view showing the flexible substrate 6 of FIG.
1 and 2, the semiconductor device (semiconductor package) of the first embodiment is a ceramic PGA type semiconductor device. The semiconductor device of the first embodiment is mounted on the upper surface of the printed wiring board 11. Furthermore, the semiconductor device of the first embodiment includes a ceramic semiconductor package substrate 1, a plurality of solder bumps 2, a semiconductor chip 3, a plurality of lower surface side pins 4, a plurality of lower surface side pins 5, and flexible substrates 6A and 6B. And a package-side connector 7.

  The semiconductor package substrate 1 has an upper surface as a first main surface, a lower surface as a second main surface disposed to face the upper surface of the printed wiring board 11, and four side surfaces (lateral surfaces). In addition, internal wiring (not shown) is formed on the semiconductor package substrate 1. The semiconductor chip 3 is fixed to the upper surface of the semiconductor package substrate 1 via a plurality of solder bumps 2. The semiconductor chip 3 is electrically connected to the internal wiring of the semiconductor package substrate 1 through a plurality of solder bumps 2.

  The plurality of lower surface side pins 4 and 5 constitute a main surface side electrode. The plurality of lower surface side pins 4 and 5 are fixed to the lower surface of the semiconductor package substrate 1 so as to protrude downward. The plurality of lower surface side pins 4 are respectively arranged in the vicinity of the four corners on the lower surface of the semiconductor package substrate 1. The plurality of lower surface side pins 5 are arranged in a staggered pattern between the plurality of lower surface side pins 4 (in a substantially quadrangular space) at intervals.

  Moreover, the lower surface side pin 4 is a pin with a hook, and the lower surface side pin 5 is a pin without a hook. A space is formed between the lower surface of the semiconductor package substrate 1 and the upper surface of the printed wiring board 11 by the ridges of the lower surface side pins 4. That is, the flange of the lower surface side pin 4 constitutes a spacer.

  The plurality of lower surface side pins 4 and 5 are electrically connected to the internal wiring of the semiconductor package substrate 1. Further, the plurality of lower surface side pins 4 and 5 are respectively inserted into a plurality of through holes (not shown) provided in the printed wiring board 11, and are soldered and fixed to the printed wiring board 11. . The plurality of lower surface side pins 4 and 5 are electrically connected to the wiring pattern of the printed wiring board 11.

  Here, a plurality of outer peripheral solder pads (not shown) are formed as a plurality of outer peripheral electrodes on the outer peripheral portion of the upper surface of the semiconductor package substrate 1, that is, the outer peripheral portion in plan view of the semiconductor package substrate 1. . The plurality of outer peripheral solder pads are provided at intervals in the circumferential direction of the semiconductor package substrate 1. The plurality of outer peripheral solder pads are electrically connected to the internal wiring of the semiconductor package substrate 1. That is, the plurality of outer peripheral solder pads are electrically connected to the semiconductor chip 3 via the internal wiring of the semiconductor package substrate 1 and the plurality of solder bumps 2.

  The package-side connector 7 is attached to the outer peripheral portion (the right side in FIG. 1) on the upper surface of the semiconductor package substrate 1 with, for example, an adhesive. The internal wiring (a plurality of connection terminals) of the package-side connector 7 is soldered and electrically connected to a plurality of outer peripheral solder pads.

  Next, the flexible boards 6A and 6B (hereinafter, the generic name of the flexible boards 6A and 6B will be described as the flexible board 6), as shown in FIG. 2, a plate-like dielectric 21 and a plurality of connection conductors. And a plurality of conductor patterns 22. The dielectric 21 forms the base material of the flexible substrate 6. The plurality of conductor patterns 22 are arranged in a straight line on the dielectric 21 at intervals.

  Part of the conductor pattern 22 is exposed at one end (left end in FIG. 1) and the other end (right end in FIG. 1) of the flexible substrate 6A. The conductive pattern 22 at one end of the flexible substrate 6 </ b> A is soldered and fixed to an outer peripheral solder pad on the upper surface of the semiconductor package substrate 1 to be electrically connected.

  The conductor pattern 22 at the other end of the flexible substrate 6A is soldered and fixed to a solder pad (not shown) formed on the upper surface of the printed wiring board 11 and electrically connected to the wiring pattern. It is connected. Therefore, one end of the flexible substrate 6 </ b> A is fixed (directly fixed) to the outer peripheral portion of the upper surface of the semiconductor package substrate 1 and the printed wiring board 11.

  Here, when the flexible substrate 6A is fixed to the semiconductor package substrate 1 and the printed wiring board 11, the lower surface side pins 4 and 5 are inserted into the through holes of the printed wiring board 11 and soldered, and then the flexible substrate 6A. The conductor pattern 22 may be soldered to each of the solder pads of the semiconductor package substrate 1 and the printed wiring board 11. Alternatively, one end of the flexible substrate 6A is pre-soldered to the solder pad of the semiconductor package substrate 1, and the lower surface side pins 4 and 5 are inserted into the through holes of the printed wiring board 11 and soldered. The ends may be soldered to the solder pads of the printed wiring board 11.

  Next, one end (left end in FIG. 1) of the flexible substrate 6B is inserted into the package-side connector 7 and fixed. The conductor pattern 22 of the flexible substrate 6 </ b> B is electrically connected to the solder pad of the semiconductor package substrate 1 through the internal wiring of the package-side connector 7.

  Here, a printed wiring board side connector 12 is attached to the upper surface of the printed wiring board 11. The internal wiring of the printed wiring board side connector 12 is electrically connected to the wiring pattern of the printed wiring board 11. The other end (the right end in FIG. 1) of the flexible substrate 6B is inserted into the printed wiring board side connector 12 and fixed. The conductor pattern 22 of the flexible substrate 6B is electrically connected to the wiring pattern of the printed wiring board 11 via the internal wiring of the printed wiring board side connector 12.

  Therefore, the internal wiring of the semiconductor package substrate 1, the solder bumps 2, and the lower surface side pins 4 and 5 form a first signal transmission path group between the semiconductor chip 3 and the wiring pattern of the printed wiring board 11. ing. On the other hand, the internal wiring of the semiconductor package substrate 1, the solder bumps 2, and the plurality of conductor patterns 22 of the flexible substrates 6 </ b> A and 6 </ b> B are arranged between the semiconductor chip 3 and the wiring pattern of the printed wiring board 11. A second signal transmission path group different from the one signal transmission path group is formed. That is, the semiconductor chip 3 and the wiring pattern of the printed wiring board 11 are electrically connected through two types of signal transmission path groups, the first signal transmission path group and the second signal transmission path group.

  According to the semiconductor device of the first embodiment as described above, the second signal transmission path group different from the first signal transmission path group by the plurality of lower surface side pins 4 and 5 is connected to the wiring pattern of the printed wiring board 11. A plurality of outer peripheral solder pads to be formed between the semiconductor chip 3 and the semiconductor chip 3 are provided on the outer peripheral portion of the semiconductor package substrate 1 in plan view. With this configuration, an electrode shortage with the printed wiring board 11 can be solved.

  Further, one end and the other end of the flexible substrate 6B are inserted into the package side connector 7 and the printed wiring board side connector 12, respectively. With this configuration, the flexible substrate 6B can be easily attached and detached.

  Further, the connection points of the second signal transmission path group in the printed wiring board 11 are changed to the connection points of the first signal transmission path group by the flexible boards 6A and 6B (insertion points of the lower surface side pins 4 and 5 in the printed wiring board 11). Therefore, the degree of freedom in designing the wiring pattern of the printed wiring board 11 can be improved.

In the first embodiment, the configuration in which two types of connection examples of the flexible substrates 6A and 6B are combined has been described. However, the present invention is not limited to this example. The connector may be omitted, and the flexible substrate 6B of the first embodiment may be fixed to the semiconductor package substrate 1 and the printed wiring board 11 by soldering as in the flexible substrate 6A. Good. In this case, parts costs can be reduced by not using a connector.
On the other hand, the flexible substrate 6A of the first embodiment may be inserted into the connector 7 or 12 and fixed to the semiconductor package substrate 1 or the printed wiring board 11 like the flexible substrate 6B. In this case, it is not necessary to solder the flexible substrate 6A, and the flexible substrate 6A can be easily attached.

  In the first embodiment, one end of the flexible substrate 6 </ b> A and the package-side connector 7 are fixed to the upper surface of the semiconductor package substrate 1. However, the present invention is not limited to this example. An outer peripheral solder pad as an outer peripheral electrode is provided on the side surface of the semiconductor package substrate 1, and one end of the flexible substrate or the package side connector is fixed to the side surface of the semiconductor package substrate 1. May be.

  Further, in the first embodiment, the connection relationship with the printed wiring board 11 on the two side surfaces of the four side surfaces of the semiconductor package substrate 1 has been described. However, in the first embodiment, the flexible printed circuit 6A or the flexible printed circuit 6B and the connectors 7 and 12 are used for the side surface (front surface) and the back surface (back surface) on the front side in FIG. The plate 11 may be electrically connected. Alternatively, the flexible substrate 6 may be used on only one of the four side surfaces of the semiconductor package substrate 1.

  In the first embodiment, the connectors 7 and 12 have internal wiring. However, the connector is not limited to this example, and the connector may have a structure in which the exposed portion of the end portion of the flexible substrate 6 is directly pressed against the solder pad of the semiconductor package substrate 1 or the printed wiring board 11. That is, the connector may have a structure in which internal wiring is omitted.

Further, in the first embodiment, the flexible substrate 6 </ b> A is soldered to the solder pad on the upper surface side of the semiconductor package substrate 1. However, the present invention is not limited to this example, and the flexible substrate 6A may be provided with a structure for switching between the front and the back in the middle of the conductor pattern 22 and may be soldered to the solder pad on the lower surface side of the semiconductor package substrate 1.
Here, in the PGA type semiconductor device, as shown in FIG. 1, in order to secure a space between the lower surface of the semiconductor package substrate 1 and the upper surface of the printed wiring board 11, the lower surfaces of the four corners of the semiconductor package substrate 1. It is necessary to use a lower surface side pin 4 with a hook as a side pin. In the absence of the flanged lower surface side pin 4, when the lower surface side pin 5 of the PGA type semiconductor device is soldered to the through hole of the printed wiring board 11, from the lower surface (back surface) side of the printed wiring board 11. Solder filled in the through hole spreads on the upper surface (front surface) side of the printed wiring board 11. As a result, the adjacent lower surface side pins 5 are short-circuited by the solder spread on the upper surface side of the printed wiring board 11.
On the other hand, when the flexible substrate 6A is provided with a structure in which the front and back sides are switched in the middle of the conductor pattern 22, the flexible substrate 6A also serves as a spacer between the semiconductor package substrate 1 and the printed wiring board 11. With this configuration, the lower surface side pins of the PGA type semiconductor device need only be one type of the lower surface side pins 5 without wrinkles, and the manufacturing cost of the PGA type semiconductor device can be suppressed.

Embodiment 2. FIG.
In the first embodiment, the example in which the plurality of conductor patterns 22 in the flexible substrates 6A and 6B are used as the plurality of connection conductors electrically connected to the plurality of outer peripheral electrodes, respectively. In contrast, in the second embodiment, an example in which a plurality of outer peripheral pins 8 are used as connection conductors electrically connected to a plurality of outer peripheral electrodes will be described.

  3 is a sectional view showing a PGA type semiconductor device according to the second embodiment of the present invention. FIG. 4 is a perspective view showing the semiconductor package substrate 1 of FIG. In FIG. 4, the solder bump 2, the semiconductor chip 3, and the printed wiring board 11 are omitted. 3 and 4, the configuration of the semiconductor device of the second embodiment is the same as the configuration of the semiconductor device of the first embodiment except for the configuration of the semiconductor package substrate 1, the flexible substrates 6A and 6B, and the connectors 7 and 12. is there. The semiconductor device according to the second embodiment has a plurality of outer peripheral pins 8 instead of the flexible substrates 6A and 6B according to the first embodiment.

  A plurality of outer peripheral solder pads (not shown) as a plurality of outer peripheral electrodes are formed on the outer peripheral portion of the lower surface of the semiconductor package substrate 1 of the second embodiment. The plurality of outer peripheral solder pads are respectively arranged at intervals in the circumferential direction of the semiconductor package substrate 1. Further, the plurality of outer peripheral side solder pads are electrically connected to the internal wiring of the semiconductor package substrate 1.

  One end of each of the plurality of outer peripheral pins 8 is soldered and fixed to each of the plurality of outer peripheral solder pads. The plurality of outer peripheral pins 8 are arranged so as to protrude from the side surface of the semiconductor package substrate 1 to the side. Here, the outer peripheral solder pads on the lower surface of the semiconductor package substrate 1 are electrically connected to the semiconductor chip 3 via internal wiring and solder bumps 2. That is, the plurality of outer peripheral pins 8 are electrically connected to the semiconductor chip 3.

  The other end of each of the plurality of outer peripheral pins 8 is soldered and fixed to each of a plurality of solder pads (not shown) formed on the upper surface of the printed wiring board 11. The solder pads of the printed wiring board 11 are electrically connected to other wiring patterns on the printed wiring board 11. Accordingly, the internal wiring of the semiconductor package substrate 1, the solder bumps 2, and the plurality of outer peripheral pins 8 form a second signal transmission path group that is different from the first signal transmission path group. Other configurations are the same as those in the first embodiment.

  According to the semiconductor device of the second embodiment as described above, the second signal transmission path group different from the first transmission path group of the plurality of lower surface side pins 5 by the plurality of outer peripheral side pins 8 is the printed wiring board. 11 wiring patterns and the semiconductor chip 3 are formed. With this configuration, the same effect as in the first embodiment can be obtained. Specifically, compared to a configuration in which the lower surface side pins 4 in a general PGA type semiconductor device are staggered at a pitch of 1.27 mm, it is possible to arrange a plurality of outer peripheral side pins 8 at a fine pitch, The effect of increasing the number of electrodes is great.

  In the semiconductor device of the second embodiment, the added outer peripheral pin 8 also serves as a spacer between the semiconductor package substrate 1 and the printed wiring board 11. With this configuration, the lower surface side pins of the PGA type semiconductor device need only be one type of the lower surface side pins 5 without wrinkles, and the manufacturing cost of the PGA type semiconductor device can be suppressed.

In the second embodiment, the shape of the plurality of outer peripheral pins 8 is linear. However, the present invention is not limited to this example. For example, one end of the plurality of outer peripheral pins 8 is fixed to the side surface or upper surface of the semiconductor package substrate 1, and the other end of the plurality of outer peripheral pins 8 faces downward. The arrangement, that is, the shape of the plurality of outer peripheral pins 8 may be a gull wing shape (L-shape).
Alternatively, for example, one end of the plurality of outer peripheral pins 8 is fixed to the side surface or upper surface of the semiconductor package substrate 1, and the other end of the plurality of outer peripheral pins 8 is disposed so as to wrap around the lower surface side of the semiconductor package substrate 1. The configuration, that is, the shape of the plurality of outer peripheral pins 8 may be a J lead shape. In the case of such a J lead shape, the outer peripheral side pins 8 may be arranged so as not to interfere with the lower surface side pins 4 and 5.

Embodiment 3 FIG.
In the first embodiment, the example in which the plurality of conductor patterns 22 in the flexible substrates 6A and 6B are used as the plurality of connection conductors electrically connected to the plurality of outer peripheral electrodes, respectively. In the second embodiment, an example in which a plurality of outer peripheral pins 8 are used as connection conductors electrically connected to a plurality of outer peripheral electrodes has been described. In contrast, the third embodiment describes an example in which the plurality of conductor patterns 22 in the flexible boards 6A and 6B in the first embodiment and the plurality of outer peripheral pins 8 in the second embodiment are used in combination. To do.

  FIG. 5 is a cross-sectional view showing a PGA type semiconductor device according to Embodiment 3 of the present invention. 5, the semiconductor device of the third embodiment has both the flexible substrates 6A and 6B in the first embodiment and the plurality of outer peripheral side pins 8 in the second embodiment. Also, a plurality of outer peripheral solder pads as a plurality of outer peripheral electrodes are formed on the outer peripheral portions of the upper surface and the lower surface of the semiconductor package substrate 1 of the third embodiment. Other configurations are the same as those in the first and second embodiments.

  Therefore, in the semiconductor device of the third embodiment, the plurality of conductor patterns 22 of the flexible substrates 6A and 6B form a second signal transmission path group together with a group of the plurality of outer peripheral solder pads. Also, the plurality of outer peripheral pins 8 form a second signal transmission path group together with the rest of the plurality of outer peripheral solder pads.

  According to the semiconductor device of the third embodiment as described above, two types of connection conductors of the plurality of conductor patterns 22 and the plurality of outer peripheral pins 8 of the flexible substrates 6A and 6B are used. With this configuration, the effects of both Embodiment 1 and Embodiment 2 can be obtained, and the number of electrodes can be greatly increased as compared to the configurations of Embodiment 1 and Embodiment 2. Can do.

Embodiment 4 FIG.
In the first embodiment, the configuration in which signals are not assigned to the plurality of conductor patterns 22 in the flexible substrate 6 has been described. In contrast, in the fourth embodiment, a configuration in which signals are assigned to the plurality of conductor patterns 22 in the flexible substrate 6 will be described.

  FIG. 6 is a plan view showing a flexible substrate 6 according to Embodiment 4 of the present invention. In FIG. 6, a part of the plurality of conductor patterns 22 is a plurality of GND conductor patterns 22a as GND connection conductors. The GND conductor pattern 22a is a conductor pattern having a GND potential.

  The remainder of the plurality of conductor patterns 22 is a plurality of state notification conductor patterns 22b as state notification connection conductors. The state notification conductor pattern 22b is an H level / L level signal representing the internal state of the semiconductor chip 3 and an H level representing the state of another electrical element (not shown) electrically connected to the semiconductor chip 3. A conductor pattern in which either one of the L level signals is transmitted. Other configurations are the same as those in the first or third embodiment.

  Here, in the plurality of conductor patterns 22 of the flexible substrate 6, the GND conductor pattern 22a is less than the state notification conductor pattern 22b. In such a transmission line structure, the characteristic impedance is unstable and crosstalk noise is likely to be generated, which is generally inappropriate for use as a signal wiring. However, if the conductor pattern 22 is used for transmission of a mode notification signal (state notification signal) for only the state (H level or L level) at the time of occurrence of a trigger in the semiconductor chip 3 or other electrical element, the influence of noise is caused. It is hard to occur and there is no problem.

  According to the semiconductor device of the fourth embodiment as described above, some of the plurality of conductor patterns 22 are the plurality of GND conductor patterns 22a, and the remainder of the plurality of conductor patterns 22 is the plurality of state notification conductors. This is the pattern 22b. With this configuration, a plurality of state notification conductor patterns 22b can be arranged on the flexible substrate 6 at a relatively high density.

  Further, by assigning the mode notification signal to the state notification conductor pattern 22b, other operation signals (pulse signals and the like) are applied to the lower surface side pins 4 and 5 in FIGS. Only trigger signals etc. can be assigned. As a result, the mode notification signal and the operation signal can be separated, and the operation signal can be prevented from giving crosstalk noise to the mode notification signal.

  In the fourth embodiment, the proportion of the GND conductor pattern 22a in the plurality of conductor patterns 22 may be 1/10 or less of the state notification conductor pattern 22b, or all of the GND conductor patterns 22a are omitted. Also good.

Embodiment 5 FIG.
In the fourth embodiment, the configuration in which the plurality of conductor patterns 22 include the state notification conductor pattern 22b has been described. In contrast, in the fifth embodiment, a configuration in which a plurality of conductor patterns 22 include signal conductor patterns 22d for transmitting operation signals (pulse signals, trigger signals, etc.) will be described.

  FIG. 7 is a plan view showing flexible substrate 6 according to the fifth embodiment of the present invention. In FIG. 7, the plurality of conductor patterns 22 of the fifth embodiment includes a plurality of GND conductor patterns 22c as GND connection conductors and a plurality of signal conductor patterns 22d as signal connection conductors. The plurality of GND conductor patterns 22c and the plurality of signal conductor patterns 22d are alternately arranged, and one signal conductor pattern 22d is arranged between the two GND conductor patterns 22c. The two GND conductor patterns 22c and one signal conductor pattern 22d constitute a signal transmission connecting conductor group.

  Here, in Embodiments 1 and 4, an example in which the size of the plurality of conductor patterns 22 in the flexible substrate 6 and the pitch between the conductor patterns 22 adjacent to each other is uniform is shown. On the other hand, in the fifth embodiment, the respective widths of the two GND conductor patterns 22c and one signal conductor pattern 22d in the signal transmission connection conductor group and the distance between each of the conductor patterns 22c and 22d. The pitch is set in advance so that the characteristic impedance of one signal conductor pattern 22d has a desired value (for example, 50Ω, 75Ω, 100Ω, etc.). Other configurations are the same as those in the first or third embodiment.

  According to the semiconductor device of the fifth embodiment as described above, the respective widths of the two GND conductor patterns 22c and one signal conductor pattern 22d in the signal transmission connection conductor group, and the respective conductor patterns 22c. , 22d is set in advance so that the characteristic impedance of one signal conductor pattern 22d has a desired value. With this configuration, the transmission line structure between the semiconductor package substrate 1 and the printed wiring board 11 can be a transmission line structure having a small parasitic component and a characteristic impedance suitable for an operation signal. Therefore, the upper limit of the band of signal transmission characteristics between the semiconductor package substrate 1 and the printed wiring board 11 can be increased, and a transmission line structure having excellent high frequency characteristics can be obtained.

  Further, a GND conductor pattern 22c is disposed between the adjacent signal conductor patterns 22d. With this configuration, crosstalk noise can be reduced. Furthermore, for example, when the characteristic impedance is 50Ω, it can be used as a transmission line in which the differential impedance of a general differential signal is 100Ω by using two signal conductor patterns 22d.

Embodiment 6 FIG.
In the fifth embodiment, the signal transmission connecting conductor group is constituted by the two GND conductor patterns 22c and the one signal conductor pattern 22d. On the other hand, in the sixth embodiment, a signal transmission connection conductor group is constituted by two GND conductor patterns 22e and one signal conductor pattern 22f.

  FIG. 8 is a plan view showing flexible substrate 6 according to the sixth embodiment of the present invention. In FIG. 8, the plurality of conductor patterns 22 according to the sixth embodiment includes a plurality of GND conductor patterns 22e as GND connection conductors and a plurality of signal conductor patterns 22f as signal connection conductors. The plurality of GND conductor patterns 22e are arranged at intervals.

  The plurality of signal conductor patterns 22f are arranged two by two between the two GND conductor patterns 22c adjacent to each other, spaced from each of the two GND conductor patterns 22c. Further, these two signal conductor patterns (pair wiring) 22f are arranged at intervals. These two GND conductor patterns 22c and the two signal conductor patterns 22f constitute a signal transmission connecting conductor group.

  Here, the respective widths of the two GND conductor patterns 22e and the two signal conductor patterns 22f in the signal transmission connection conductor group and the pitch between the conductor patterns 22e and 22f are for two signals. The differential impedance of the conductor pattern 22f is set in advance so as to have a desired value (for example, 100Ω). Other configurations are the same as those in the first or third embodiment.

  According to the semiconductor device of the sixth embodiment as described above, the respective widths of the two GND conductor patterns 22e and the two signal conductor patterns 22f in the signal transmission connection conductor group, and the respective conductor patterns 22e. , 22f is set in advance so that the differential impedance of the two signal conductor patterns 22f has a desired value. With this configuration, the transmission line structure between the semiconductor package substrate 1 and the printed wiring board 11 can be a transmission line structure having a small parasitic component and a differential impedance suitable for an operation signal. Therefore, as in the fifth embodiment, the upper limit of the band of the differential signal transmission characteristics between the semiconductor package substrate 1 and the printed wiring board 11 can be increased, and a transmission path having excellent high frequency characteristics can be obtained.

  In addition, since the GND conductor pattern 22e is arranged for each of the two signal conductor patterns 22f, crosstalk noise between differential signals can be reduced.

  In the fifth embodiment, the example corresponding to the differential signal has been described by setting the impedance of the pair wiring to 100Ω. On the other hand, by setting the impedance of the pair wiring to 50Ω, it is possible to cope with a single-ended signal.

  In the fifth embodiment, one GND conductor pattern 22c is arranged between two signal conductor patterns 22d belonging to different signal transmission connection conductor groups. In the sixth embodiment, one GND conductor pattern 22e is arranged between two signal conductor patterns 22f belonging to different signal transmission connection conductor groups. However, the present invention is not limited to these examples. Even if two or more GND conductor patterns 22c and 22e are disposed between two signal conductor patterns 22d and 22f belonging to different signal transmission connection conductor groups. Good.

  Furthermore, in Embodiments 4 to 6, the configuration of the conductor pattern 22 in the flexible substrate 6 has been described. However, for the outer peripheral side pins 8 in the second and third embodiments, the use, pitch, and width may be set in advance as in the configuration of the conductor pattern 22 in the fourth to sixth embodiments.

  In the first and fourth embodiments, the conductor pattern 22 is formed only on one side of the flexible substrate 6. However, the present invention is not limited to this example, and the conductor pattern 22 may be formed on both surfaces of the flexible substrate 6. In this case, one side of the flexible substrate 6 may be a solid GND. Further, three or more layers of conductor patterns 22 may be formed on the flexible substrate 6.

Embodiment 7 FIG.
In the second and third embodiments, the width and pitch of the outer peripheral side pin 8 on the semiconductor package substrate 1 side and the printed wiring board 11 side are configured to be uniform. In contrast, in the seventh embodiment, the width and pitch of the outer peripheral pins 31 to 34 on the semiconductor package substrate 1 side and the printed wiring board 11 side are different values.

  FIG. 9 is a perspective view showing a PGA type semiconductor device according to Embodiment 7 of the present invention. FIG. 10 is an enlarged plan view showing the periphery of the outer peripheral side pins 31 to 34 in FIG. 9. In FIG. 9, the solder bump 2, the semiconductor chip 3, and the printed wiring board 11 are omitted. 9 and 10, in the semiconductor device of the seventh embodiment, instead of the plurality of outer peripheral pins 8 in the semiconductor device of the second embodiment, GND outer peripheral pins 31 and 34 as GND connection conductors, It has signal outer peripheral pins 32 and 33 as signal connection conductors. These outer peripheral side pins 31 to 34 constitute a signal transmission connection conductor group. Each outer peripheral side pin 31-34 has two linear part 31a-34a, 31c-34c, and the intermediate | middle adjustment part 31b-34b.

  Two outer peripheral solder pads 1a for GND and two outer peripheral solder pads 1b for signals are formed as outer peripheral electrodes on the outer peripheral portion of the lower surface of the semiconductor package substrate 1 of the seventh embodiment. These outer peripheral solder pads 1a and 1b are arranged at equal intervals. In addition, the widths of the outer peripheral solder pads 1a and 1b are uniform.

  Two GND solder pads 11a and two signal solder pads 11b are formed on the upper surface of the printed wiring board 11 of the seventh embodiment. These solder pads 11a and 11b are arranged at equal intervals. The widths of the solder pads 11a and 11b are uniform. The width and pitch of the outer peripheral solder pads 1a and 1b of the semiconductor package substrate 1 and the width and pitch of the solder pads 11a and 11b of the printed wiring board 11 are different from each other.

  Here, in the semiconductor package substrate 1 of the seventh embodiment, the difference between the two outer peripheral solder pads for signal 1b depends on the width of the outer peripheral solder pads 1a and 1b and the pitch between the outer peripheral solder pads 1a and 1b. Dynamic impedance is optimized. On the other hand, in the printed wiring board 11, the differential impedance of the wiring pattern connected to the two signal solder pads 11b is optimized by the width of the solder pads 11a and 11b and the pitch between the solder pads 11a and 11b. ing. Therefore, when the width of each outer peripheral side pin 8 and the pitch between each outer peripheral side pin 8 are uniform as in the second embodiment, the semiconductor package substrate 1 side and the printed wiring board 11 side are Cannot connect with impedance matching.

  On the other hand, the width of each linear part 31a-34a and the pitch between each linear part 31a-34a are the width | variety of each outer peripheral side solder pad 1a, 1b of the semiconductor package board | substrate 1, and each outer peripheral side solder pad 1a, It corresponds to the pitch between 1b, and each linear portion 31a-34a is soldered and fixed to each outer peripheral side solder pad 1a, 1b. Further, the width of each linear portion 31c to 34c and the pitch between each linear portion 31c to 34c are the width of each outer peripheral solder pad 11a, 11b of the semiconductor package substrate 1 and the pitch between each linear portion 31c to 34c. Correspondingly, the straight portions 31c to 34c are fixed by soldering to the solder pads 11a and 11b.

  The widths of the intermediate adjustment units 31b to 34c and the pitch between the intermediate adjustment units 31b to 34c are set in advance so that the differential impedance of the signal outer peripheral pins 32 and 33 has a desired value. That is, the width of the portion between the semiconductor package substrate 1 and the printed wiring board 11 in each of the outer peripheral pins 31 to 34 and the portion between the semiconductor package substrate 1 and the printed wiring board 11 in each of the outer peripheral pins 31 to 34. Is set in advance so that the differential impedance of the signal outer peripheral pins 32 and 33 has a desired value. Accordingly, each of the outer peripheral pins 31 to 34 connects the semiconductor package substrate 1 side and the printed wiring board 11 side in a state where impedance matching is achieved. Other configurations are the same as those in the second embodiment.

  According to the semiconductor device of the seventh embodiment as described above, the width of each of the intermediate adjustment units 31b to 34c and the pitch between each of the intermediate adjustment units 31b to 34c are the differential impedances of the signal outer peripheral pins 32 and 33. Is set in advance so as to have a desired value. With this configuration, even when the width and pitch of the wiring that can be impedance-matched are different between the semiconductor package substrate 1 side and the printed wiring board 11 side, the transmission line has a small parasitic component and has a differential impedance suitable for signals. A structure can be obtained.

  In the seventh embodiment, the arrangement of the outer peripheral pins 31 to 34 is for GND-signal-signal-GND. However, the present invention is not limited to this example, and a GND outer peripheral pin may be arranged for each signal outer peripheral pin. That is, the arrangement of the outer peripheral pins may be for GND, for signal, and for GND. In this case, it is possible to optimize the characteristic impedance of one signal outer peripheral side pin. Together with this, it is possible to reduce the loss talk noise in one signal outer peripheral side pin.

  Further, in the seventh embodiment, only one set of signal transmission connection conductor groups from the GND outer peripheral side pin 31 to the GND outer peripheral side pin 34 is shown. However, the present invention is not limited to this example, and a plurality of signal transmission connection conductor groups may be repeatedly arranged. Even in this case, the crosstalk noise between the differential signals at the two signal outer peripheral pins 32 and 33 can be reduced in each of the plurality of signal transmission connection conductor groups.

  Furthermore, the width and pitch of the conductor pattern 22 of the flexible substrate 6 in the first and fourth embodiments may be the same as the width and pitch of the outer peripheral pins 31 to 34 in the seventh embodiment. That is, the flexible substrate 6 may be provided with adjustment portions such as the intermediate adjustment portions 31 b to 34 c of the seventh embodiment by setting the width and pitch to be different between the one end side and the other end side of the conductor pattern 22.

  Moreover, it is good also as a structure like Embodiment 3 combining each outer peripheral side pins 31-34 of Embodiment 7, and the flexible substrate 6 of Embodiment 4-6.

  Furthermore, in the first to seventh embodiments, the semiconductor package substrate 1 is made of ceramic. However, the present invention is not limited to this example, and the semiconductor package substrate 1 may be made of resin, and the semiconductor package substrate 1 may be formed of a material other than ceramic and resin.

  In the first to seventh embodiments, the outer peripheral pad is provided on the upper surface or the lower surface of the semiconductor package substrate 1. However, the present invention is not limited to this example, and an outer peripheral pad may be provided on the side surface (lateral surface) of the semiconductor package substrate 1.

  Furthermore, in Embodiments 1 to 7, the lower surface side pins 4 and 5 are used as the main surface side electrodes. However, the present invention is not limited to this example, and a solder ball or an electrode pad may be used as the main surface side electrode. That is, the present invention can be applied not only to the BGA type semiconductor device in the first to seventh embodiments, but also to a PGA type semiconductor device and an LGA type semiconductor device, and can also be applied to semiconductor devices other than these types.

  In the first to seventh embodiments, a single (one) semiconductor chip 3 is used. However, the present invention is not limited to this example, and a plurality (two or more) of semiconductor chips 3 may be used. That is, a plurality of semiconductor chips 3 may be provided on the semiconductor package substrate 1.

  Further, in the first to seventh embodiments, the semiconductor chip 3 is provided on the upper surface (first main surface) of the semiconductor package substrate 1. However, the present invention is not limited to this example, and a part of the lower surface side pins 4 and 5 may be omitted, and the semiconductor chip 3 may be provided on the lower surface (second main surface) of the semiconductor package substrate 1. When a plurality of semiconductor chips 3 are used, a part of the plurality of semiconductor chips 3 is provided on the upper surface of the semiconductor package substrate 1, and the rest of the plurality of semiconductor chips 3 is disposed on the lower surface of the semiconductor package substrate 1. May be provided.

  In the first to seventh embodiments, the upper surface of the semiconductor chip 3 is exposed. However, the present invention is not limited to this example, and the semiconductor chip 3 may be entirely covered with a resin or the like.

  Further, in the first to seventh embodiments, the outer peripheral side solder pad as the outer peripheral side electrode is electrically connected to the wiring pattern of the printed wiring board 11 via the conductor pattern 22 of the flexible substrate 6 or the outer peripheral side pin 8. It was the configuration that was made. However, the present invention is not limited to this example. For example, in a configuration in which a semiconductor device is inserted into an IC socket previously mounted on a printed wiring board and mounted on the printed wiring board, the outer peripheral electrode of the semiconductor package substrate The electrode pad may be electrically connected to the wiring pattern of the printed wiring board 11 via the internal wiring of the IC socket.

  DESCRIPTION OF SYMBOLS 1 Semiconductor package board | substrate, 1a GND outer peripheral side solder pad (outer peripheral side electrode), 1b Signal outer peripheral side solder pad (outer peripheral side electrode), 3 Semiconductor chip, 4, 5 Lower surface side pin (main surface side electrode), 6, 6A, 6B Flexible substrate (connection conductor), 7 Package side connector, 8 Outer peripheral side pin (connection conductor), 11 Printed wiring board, 22 Conductor pattern, 22a, 22c, 22e GND conductor pattern (GND connection conductor), 22b State notification conductor pattern (state notification connection conductor), 22d, 22f Signal conductor pattern (signal connection conductor), 31, 34 GND outer peripheral pin (GND connection conductor), 32, 33 Signal outer peripheral pin (Signal connection conductor).

Claims (14)

One or more semiconductor chips, and
A first main surface and a second main surface which is a back surface of the first main surface and is disposed opposite to the printed wiring board; and the semiconductor is provided on at least one of the first main surface and the second main surface A semiconductor package substrate provided with a chip; and
A plurality of the first signal transmission path groups provided on the second main surface of the semiconductor package substrate and spaced apart from each other to form a first signal transmission path group between the wiring pattern of the printed wiring board and the semiconductor chip. A main surface side electrode of the semiconductor device,
A second different from the first signal transmission path group between the wiring pattern of the printed wiring board and the semiconductor chip, which is provided on the outer peripheral portion in plan view of the semiconductor package substrate and arranged at intervals. A semiconductor device, further comprising a plurality of outer peripheral electrodes for forming a signal transmission path group. A pattern shape for electrically connecting the wiring pattern of the printed wiring board and the plurality of outer peripheral electrodes to form the second signal transmission path group together with the plurality of outer peripheral electrodes. The semiconductor device according to claim 1, further comprising: a flexible substrate having a plurality of connection conductors, one end fixed to the outer peripheral portion of the semiconductor package substrate, and the other end fixed to the printed wiring board. . The second signal transmission path group, together with the group of the plurality of outer peripheral electrodes, electrically connecting the wiring pattern of the printed wiring board and the group of the plurality of outer peripheral electrodes, which are arranged at intervals. A flexible substrate having one end fixed to the outer periphery of the semiconductor package substrate and the other end fixed to the printed wiring board.
One end is fixed to the outer peripheral portion of the semiconductor package substrate, the other end is fixed to the printed wiring board, and each of them is arranged at intervals, and the wiring pattern of the printed wiring board and the plurality of outer peripheral electrodes 2. A plurality of pin-shaped connecting conductors for electrically connecting the rest and forming the second signal transmission path group together with the rest of the plurality of outer peripheral electrodes. Semiconductor device. An internal wiring electrically connected to the plurality of outer peripheral electrodes, further comprising a connector attached to the outer peripheral portion of the semiconductor package substrate;
One end of the flexible substrate is inserted into the connector and fixed to the outer peripheral portion of the semiconductor package substrate,
4. The semiconductor according to claim 2, wherein the plurality of connection conductors of the flexible substrate are electrically connected to the plurality of outer peripheral electrodes via the internal wiring of the connector. 5. apparatus. One end is fixed to the outer peripheral portion of the semiconductor package substrate, the other end is fixed to the printed wiring board, and arranged at intervals, and the wiring pattern of the printed wiring board and the plurality of outer peripheral electrodes are electrically connected. 2. The semiconductor device according to claim 1, further comprising a plurality of pin-shaped connection conductors that are connected together to form the second signal transmission path group together with the plurality of outer peripheral electrodes. The plurality of connection conductors transmit either one of an H level / L level signal representing the internal state of the semiconductor chip and an H level / L level signal representing the state of another electrical element. The semiconductor device according to claim 2, further comprising a state notification connection conductor. The plurality of connection conductors include two GND connection conductors that are spaced apart from each other and have a GND potential, and one signal connection conductor that is disposed between the two GND connection conductors and transmits an operation signal. A signal transmission connecting conductor group consisting of
The width of each of the two GND connection conductors and the one signal connection conductor in the signal transmission connection conductor group and the pitch between the connection conductors are the characteristics of the one signal connection conductor. The semiconductor device according to any one of claims 2 to 5, wherein the impedance is set in advance so as to have a desired value. The width on the semiconductor package substrate side of each connection conductor and the width on the printed wiring board side of each connection conductor are set to different values in advance,
The pitch on the semiconductor package substrate side between the connection conductors and the pitch on the printed wiring board side between the connection conductors are set to different values in advance,
The width of the location between each of the connection conductors between the semiconductor package substrate and the printed wiring board, and the pitch of the location between the semiconductor package substrate and the printed wiring board between the connection conductors are as described above. The semiconductor device according to claim 7, wherein the characteristic impedance of each of the signal connection conductors is set in advance so as to have a desired value. The plurality of connection conductors include two GND connection conductors that are spaced apart from each other and set to the GND potential, and two signal transmission signals that are disposed adjacent to each other between the two GND connection conductors. A signal transmission connection conductor group consisting of connection conductors for
The width of each of the two GND connection conductors and the two signal connection conductors in the signal transmission connection conductor group and the pitch between these connection conductors are the difference between the two signal connection conductors. The dynamic impedance and at least one of the characteristic impedances of each of the two signal connection conductors are set in advance so that a desired value is obtained. 6. 2. A semiconductor device according to item 1. The width on the semiconductor package substrate side of each connection conductor and the width on the printed wiring board side of each connection conductor are set to different values in advance,
The pitch on the semiconductor package substrate side between the connection conductors and the pitch on the printed wiring board side between the connection conductors are set to different values in advance,
The width of the location between the semiconductor package substrate and the printed wiring board of each connection conductor and the pitch of the location between the semiconductor package substrate and the printed wiring board between the connection conductors are 2 The differential impedance of two signal connection conductors and the characteristic impedance of each of the two signal connection conductors are set in advance so as to have a desired value. Semiconductor device. The plurality of main surface side electrodes are a plurality of second main surface side pins protruding from the second main surface to the opposite side of the first main surface. The semiconductor device according to any one of the above. The semiconductor device according to any one of claims 1 to 10, wherein the plurality of principal surface side electrodes are a plurality of solder balls. The semiconductor device according to any one of claims 1 to 10, wherein the plurality of main surface side electrodes are a plurality of electrode pads.   14. A printed wiring board on which the semiconductor device according to claim 1 is mounted.

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