JPH08293570A - Semiconductor package - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a semiconductor package that can be easily aligned with a substrate and can be expanded with more electrode terminals. In a surface mounting type semiconductor package for surface mounting on a substrate 14, a first wiring portion 25 of the substrate 14 is provided.
Electrode terminals 1 provided on the bottom surface 10 for electrical connection with the plurality of lead terminals 2 arranged on the outer periphery for electrically connecting to the second wiring portion 30 of the substrate.
And

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a surface mounting type semiconductor package which is surface mounted on a printed wiring board.

[0002]

2. Description of the Related Art A conventional package of this type has a semiconductor package structure as shown in FIG. 5, that is, a so-called ball grid array (BGA) structure. The semiconductor package has ball electrodes in a grid pattern, and the ball electrodes are suitable for connecting to a substrate in order to extract a large number of signals.

[0003]

However, recently, the degree of integration in semiconductor devices has increased, and in order to extract more signals, the spacing between the grids of the ball-shaped electrodes is narrowed to increase the number of ball-shaped electrodes. Need to be placed.

Here, when a large number of ball-shaped electrodes are arranged at a narrow pitch, there are the following problems. The first is the alignment accuracy between the semiconductor package and the substrate on which the semiconductor package is mounted. For example, 1.5 mm
The semiconductor package in which the ball-shaped electrodes are arranged along the grid having the pitch of 1 can be connected without any problem if the alignment accuracy with the substrate electrode is within 0.6 mm. However, in a semiconductor package in which ball-shaped electrodes are arranged along a lattice of a package having a narrow pitch (for example, a pitch of 1.0 mm), the alignment accuracy with the substrate electrode must be within 0.3 mm. A so-called bridge phenomenon occurs between the melted ball-shaped electrodes, and the ball-shaped electrodes are short-circuited with each other. Secondly, as another problem, even if an attempt is made to wire a semiconductor signal line for connection with another circuit component, the pitch between the ball-shaped electrodes of the substrate is narrow, and the wire can be passed between the electrodes. For that reason, the wiring must be provided by making the number of layers of the wiring substrate multi-layered. Therefore, the cost of the wiring board is increased.

Therefore, the present invention has been made in order to solve the above problems, and provides a semiconductor package which can be easily aligned with a substrate and in which more electrode terminals can be added. Is intended.

[0006]

According to the invention of claim 1, in the surface mount type semiconductor package for surface mounting on a substrate, the above object is electrically connected to the first wiring portion of the substrate. Therefore, by a semiconductor package including a plurality of projecting electrode terminals provided on the bottom surface and a plurality of lead terminals arranged on an outer peripheral portion for electrically connecting to the second wiring portion of the substrate, To be achieved. In the invention of claim 2, the lead terminal is preferably connected so as to be at the ground potential. In the invention of claim 3, preferably, the lead terminal has a gull wing shape. In the invention of claim 4, the distance from the bottom surface to the lead terminal is preferably smaller than the distance from the bottom surface to the electrode terminal. In the invention of claim 5, preferably, the electrode terminal has a ball shape or a column shape.

[0007]

According to the first aspect of the invention, when the semiconductor package is mounted on the substrate, the protruding electrode terminals provided on the bottom surface are electrically connected to the first wiring portion of the substrate. . Moreover, the lead terminal on the outer peripheral portion is electrically connected to the second wiring portion of the substrate. In this way, in addition to the protruding electrodes provided on the bottom surface of the semiconductor package, the lead terminals are provided on the outer peripheral portion, so that the semiconductor package can be aligned with reference to the lead terminals, Invisible bottom electrode terminals on the bottom and the first of the substrate
The electrical connection with the wiring part can be surely performed. Further, by adding the lead terminal to the outer peripheral portion, the number of terminals can be significantly increased without increasing the number of protruding electrode terminals on the bottom surface side. According to the second aspect of the invention, since the lead terminal on the outer peripheral portion of the semiconductor package is at the ground potential, unnecessary radiation is reduced, and noise and the like from other circuits can be blocked. Claim 4
According to the invention, since the distance from the bottom surface to the lead terminal is smaller than the distance from the bottom surface to the electrode terminal, the protruding electrode terminal on the bottom surface is electrically connected to the first wiring portion and When the lead terminal is electrically connected to the second wiring portion of the substrate, the protruding electrode terminal on the bottom surface melts and is crushed by the weight of the semiconductor package, which reduces the distance from the bottom surface to the electrode terminal. As a result, the lead terminal on the outer peripheral portion is electrically connected to the second connection portion of the substrate.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described in detail below with reference to the accompanying drawings. The examples described below are
Since it is a preferred specific example of the present invention, various technically preferable limitations are attached, but the scope of the present invention is, unless otherwise stated to limit the present invention, in the following description.
It is not limited to these modes.

FIG. 1 is a perspective view showing a preferred embodiment of the semiconductor package of the present invention. This semiconductor package 2
Reference numeral 0 has a plurality of protruding electrode terminals 1, a plurality of lead terminals 2, a circuit board 3, and a sealing member 4. As shown in FIGS. 1 and 2, the plurality of protruding electrode terminals 1 are electrode terminals arranged in a grid pattern having a predetermined pitch, and preferably have a ball shape. This semiconductor package 20 is formed by adding a plurality of lead terminals 2 to the outer periphery 5 of a ball grid array (BGA) having projecting electrode terminals arranged in a grid pattern.

A semiconductor element (not shown) die-bonded to the surface of the circuit board 3 is packaged by overcoating with a sealing member 4 made of, for example, an epoxy resin. A predetermined number of signal lines (not shown) drawn from the semiconductor elements die-bonded to the surface of the circuit board 3 which is a semiconductor substrate are respectively connected to the back surface of the circuit board through through holes (not shown). A large number of the above-mentioned protruding electrode terminals 1 are formed by connecting to electrode terminals (not shown) arranged in a predetermined pattern on the side, and further solder ball bonding corresponding to the electrode terminals. Has been done. Circuit board 3
Among the signal lines drawn from the semiconductor element die-bonded on the surface of the circuit board, the signal line that should be at the ground potential is the outer peripheral portion 5 of the circuit board 3 through the front surface of the circuit board 3 or the back surface through the through hole. And is electrically connected to each lead terminal 2. This lead terminal 2 preferably has a so-called gull wing shape. The plurality of lead terminals 2 are arranged on the four sides of the outer peripheral portions 5a to 5d of the semiconductor package 20, respectively.
However, the present invention is not limited to this, and the lead terminals 2 are opposed to the outer peripheral portion 5
Outer peripheral portion 5 provided only on a or 5c or facing each other
b, 5d, or adjacent outer peripheral portions 5a, 5
Of course, it does not matter even if they are arranged in b, adjacent 5c, 5d, or the like.

Next, a preferred shape of the lead terminal 2 shown in FIG. 1 will be described with reference to FIGS. Lead terminal 2
The lead terminal 2 is a so-called F-shaped lead frame, and has a holding portion 6 and a lead tip portion 7. The holding portion 6 is almost U
The holding portion 6 has a V shape and is fixed to the circuit board 3 so as to sandwich the electrode lands 8 on the end surface of the circuit board 3. Moreover, in order to ensure electrical conduction between the holding portion 6 and the electrode land 8 of the circuit board 3, the holding portion 6 and the electrode land 8 are preferably soldered.

A particularly characteristic feature of the embodiment of the present invention is that
The next point. The distance between the bottom surface 10 of the semiconductor package 20 and the tip of the protruding electrode terminal 1 is indicated by reference numeral h1. On the other hand, the distance between the lead tip portion 7 of the lead terminal 2 and the bottom surface 10 is indicated by reference numeral h2. The distance h2 is set to be slightly smaller than the distance h1 as shown in FIG. Specifically, the distance h1 is, for example, 0.6 mm, and the distance h2 is 0.45 mm. This electrode terminal 2 is made of a conductive member having elasticity.

FIG. 4 shows how the printed wiring board 14, which is a substrate on which the above-mentioned semiconductor package 20 is mounted, and the semiconductor package 20 are mounted. Electrode lands 8 are provided on the printed wiring board (substrate) 14 shown in FIG. The semiconductor package 20 will be mounted on the printed wiring board 14.

Next, a method of mounting the semiconductor package of the present invention on the printed wiring board 14 will be described with reference to FIG. First, the printed wiring board 14 for mounting the semiconductor package 20 is a technology (surface mount technology, SMT) process for surface-mounting ordinary chip components, large-scale integrated circuits (LSI), etc. on the printed wiring board 14. Using solder paste 17
Is applied to the land 8 side by a printing method using a squeegee 18. When the thickness of the metal screen 16 used at this time is 180 μm, for example, the solder paste 17
Has a thickness of, for example, 150 μm.

Next, the printed wiring board 14 obtained in the steps of FIGS. 4 (a) and 4 (b) has a first wiring portion 25 and a second wiring portion 30 as shown in FIG. 4 (C). And have. The first wiring portion 25 has a plurality of, for example, circular electrode lands 25a. The electrode lands 25a are formed at positions corresponding to the protruding electrode terminals 1 of the semiconductor package 20, respectively. The second wiring portion 30 has a plurality of electrode lands 30a. These electrode lands 3
0a are located at positions corresponding to the lead terminals 2 of the semiconductor package 20, respectively. Each electrode land 30a has a rectangular shape in FIG. 4 (c), and the lead terminal 2 in FIG.
Is a portion electrically connected to the lead tip portion 7. In FIG. 4, the number of lead terminals 2, the number of electrode lands 30a,
The number of the electrode lands 25a is drawn relatively small for simplification of the drawing.

Next, the electrode terminal 1 of the semiconductor package 20.
Then, the electrode lands 25a coated with the solder paste as described above are respectively aligned. At the time of this alignment, the gull-wing-shaped lead terminals 2 on the outer peripheral portion 5 of the semiconductor package 20 are connected to the electrode terminals 1 and the electrode lands 2.
It serves as a reference for alignment with 5a. That is, by aligning the lead terminals 2 with the electrode lands 30a, the electrode terminals 1 can be automatically and easily positioned on the electrode lands 25a automatically. Then, the printed wiring board 14 on which the semiconductor package 20 is mounted is put into a reflow furnace and the above-mentioned solder paste is melted. At this time, the reflow profile was first raised at a temperature of 2 to 3 ° C./second and then raised to about 150 ° C., similarly to the technique of surface mounting ordinary chip parts, large-scale integrated circuits, etc. on a printed wiring board. Later, this temperature is maintained for 90 to 120 seconds.

Next, the temperature of the printed wiring board 14 on which the semiconductor package 20 is mounted is raised at 2 to 3 ° C./sec.
Hold at 210 ° C. for 5 to 10 seconds and then cool.
At this time, the electrode terminals 1 and the solder paste of the semiconductor package 20 are melted to reduce the gap between the bottom surface 10 of the semiconductor package 20 and the printed wiring board 14. Specifically, for example, the lead terminal 2 having 255 pins and 1.
Semiconductor package 20 having 5 mm pitch electrode terminals 1
In this case, the gap between the bottom surface 10 of the semiconductor package 20 and the printed wiring board 14 is about 0.4 mm.
However, due to the gull wing-shaped lead terminal 2, this gap is reduced to the distance h2 of FIG.
You will be limited to millimeters. Thus, the lead terminals 2 on the outer peripheral portions 5a to 5d of the semiconductor package 20 can be reliably connected to the predetermined electrode lands 30a of the printed wiring board 14, respectively.

As described above, according to the embodiment of the semiconductor package of the present invention, in addition to the arrangement of the protruding electrode terminals only on the back surface of the semiconductor package, the lead terminals are additionally provided on the outer peripheral portion of the semiconductor package. The number of terminals to be pulled out from the package can be greatly increased.
Further, since the height (distance) of the lead terminal is made lower than the height (distance) of the protruding electrode terminal, the protruding electrode melts at the time of solder bonding and is crushed by the weight of the semiconductor package. Since the height of the protruding electrode is reduced, each lead terminal can be reliably connected to each electrode land of the printed wiring board. Further, in the conventional ball grid array type semiconductor package, the alignment state of the electrode terminals on the bottom surface and the electrode lands of the printed wiring board could not be confirmed, but according to the embodiment of the semiconductor package of the present invention, ,
Using the lead terminals provided on the outer peripheral portion of the semiconductor package as a reference, it is possible to confirm the alignment of the projecting electrode terminals of the semiconductor package with the electrode lands of the printed wiring board. Moreover, since the lead terminals can be used as signal lines, the number of terminals for connection to a printed wiring board or the like can be significantly increased. By grounding the lead terminal to the ground potential (same potential), the shielding effect of the semiconductor package can be obtained. In other words, unnecessary radiation can be reduced,
Noise and the like from other electronic circuits can be shielded.
Therefore, mounting of a semiconductor package having a shield effect can be realized.

The present invention is not limited to the above embodiment. In the above-described embodiment, the lead terminals 2 are added to the four outer peripheral portions 5a to 5d of the semiconductor package 20 as shown in FIG. However, the present invention is not limited to this, and it is conceivable to add lead terminals to one or three portions of the four outer peripheral portions 5a to 5d. Further, the semiconductor package 20 has a substantially square shape when viewed from above in the embodiment of FIG. 1, but it is not limited to this and may have a rectangular shape or another polygonal shape.

Further, the projection-shaped electrode terminals on the bottom surface are ball-shaped in the above-mentioned embodiments, but they are not limited to this and may be cylindrical. Further, although the lead terminal 2 has a gull wing shape, it is of course possible to adopt other shapes without being limited to this.

[0021]

As described above, according to the present invention, it is possible to easily align with the substrate, and it is possible to add more electrode terminals.

[Brief description of drawings]

FIG. 1 is a perspective view showing a preferred embodiment of a semiconductor package of the present invention.

2 is a distance h1 between a bottom surface and a protruding electrode terminal and a distance h2 between a bottom surface and a lead terminal 2 in the semiconductor package of FIG.
FIG.

FIG. 3 is a side view showing a preferred embodiment of the lead terminal of FIG.

FIG. 4 is a diagram showing a state in which the semiconductor package of the present invention is being mounted on a printed wiring board.

FIG. 5 is a perspective view showing a bottom surface side of a conventional ball grid array type semiconductor package.

[Explanation of symbols]

 1 Protruding Electrode Terminal 2 Lead Terminal 10 Bottom 14 Printed Wiring Board (Substrate) 20 Semiconductor Package 25 First Wiring Section 30 Second Wiring Section h1 Distance from Bottom to Electrode Terminal h2 Bottom to Lead Tip of Lead Terminal The distance

Claims (5)

[Claims] 1. A surface mount semiconductor package for surface mounting on a substrate, comprising: a plurality of projecting electrode terminals provided on a bottom surface for electrically connecting to a first wiring portion of the substrate; A plurality of lead terminals arranged on the outer peripheral portion for electrically connecting to the second wiring portion of the semiconductor package. 2. The semiconductor package according to claim 1, wherein the lead terminal is connected so as to have a ground potential. 3. The semiconductor package according to claim 1, wherein the lead terminal has a gull wing shape. 4. The semiconductor package according to claim 1, wherein the distance from the bottom surface to the lead terminal is smaller than the distance from the bottom surface to the electrode terminal. 5. The semiconductor package according to claim 1, wherein the electrode terminal has a ball shape or a column shape.