CN216902914U - Silicon-based substrate and chip - Google Patents

Silicon-based substrate and chip Download PDF

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Publication number
CN216902914U
CN216902914U CN202220583934.2U CN202220583934U CN216902914U CN 216902914 U CN216902914 U CN 216902914U CN 202220583934 U CN202220583934 U CN 202220583934U CN 216902914 U CN216902914 U CN 216902914U
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substrate
metal
substrate body
threshold
via hole
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CN202220583934.2U
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Chinese (zh)
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张达
杜树安
沙超群
历军
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Haiguang Information Technology Co Ltd
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Haiguang Information Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15182—Fan-in arrangement of the internal vias
    • H01L2924/15184—Fan-in arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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Abstract

The embodiment of the utility model discloses a silicon-based substrate and a chip, relates to the technical field of semiconductor packaging, and is convenient for effectively considering both short-distance high-density signal transmission and long-distance low-loss signal transmission through the same silicon-based substrate. The silicon-based substrate includes: the circuit board comprises a substrate body, wherein at least two via holes are arranged in the substrate body, the at least two via holes comprise at least one first via hole and at least one second via hole, and the cross sectional area of the first via hole is larger than that of the second via hole; the first via hole is used for being electrically connected with a first metal wire arranged in the substrate body, the second via hole is used for being electrically connected with a second metal wire arranged in the substrate body, and the cross sectional area of the first metal wire is larger than that of the second metal wire. The utility model is suitable for chip packaging.

Description

Silicon-based substrate and chip
Technical Field
The utility model relates to the technical field of semiconductor packaging, in particular to a silicon-based substrate and a chip.
Background
Along with the miniaturization, integration and intellectualization of electronic products, the complexity and the use number of chips are greatly increased, and the complexity of chip packaging is higher and higher. In chip packaging, interconnection between different pins of a single die or between multiple dies can be achieved through a silicon wafer as well as an organic substrate.
For the interconnection realized by the silicon wafer, dense metal thin lines (generally, the line width is less than 1um (micrometer), and the line height is less than 1um) are generally adopted as interconnection lines, and the metal thin lines on different layers in the silicon wafer are connected by arranging fine via holes in the silicon wafer. The via holes are generally small in size and uniform in distribution, so that the chip-to-chip short-distance signal transmission with high density and large bandwidth is facilitated, and the manufacturing process is also facilitated to control.
However, although the via hole and the interconnect structure can effectively support short-distance signal transmission, signal integrity is lost in long-distance and high-speed signal transmission, so that a signal at a receiving end is inconsistent with an original transmission end, and a chip function is faulty.
SUMMERY OF THE UTILITY MODEL
In view of this, embodiments of the present invention provide a silicon-based substrate and a chip, which facilitate the effective combination of short-distance high-density signal transmission and long-distance low-loss signal transmission through the same silicon-based substrate in chip packaging.
In a first aspect, an embodiment of the present invention provides a silicon-based substrate, including: the circuit board comprises a substrate body, wherein at least two via holes are arranged in the substrate body, the at least two via holes comprise at least one first via hole and at least one second via hole, and the cross sectional area of the first via hole is larger than that of the second via hole; the first via hole is used for electrically connecting a first metal wire arranged in the substrate body, the second via hole is used for electrically connecting a second metal wire arranged in the substrate body, and the cross-sectional area of the first metal wire is larger than that of the second metal wire; wherein at least one of the at least two vias has any of the following: one end of the substrate body is positioned on the first surface of the substrate body, and the other end of the substrate body is positioned in the substrate body; one end of the substrate body is positioned on the second surface of the substrate body, and the other end of the substrate body is positioned in the substrate body; one end of the substrate body is positioned on the first surface of the substrate body, and the other end of the substrate body is positioned on the second surface of the substrate body; both ends are positioned in the substrate body; the first surface of the substrate body is used for arranging crystal grains, and the second surface and the first surface are opposite.
Optionally, the cross-sectional area of the first via is greater than a first area threshold, and the cross-sectional area of the second via is smaller than a second area threshold, where the first area threshold is greater than or equal to the second area threshold.
Optionally, a ratio of the cross-sectional area of the first via to the cross-sectional area of the second via is greater than or equal to a first proportional threshold.
Optionally, the first ratio threshold is 2:1, 4:1, 5:1, 9:1, 16: 1.
Optionally, the first vias and the second vias are staggered in a direction parallel to the first surface of the substrate body and/or in a direction perpendicular to the first surface of the substrate body within at least a partial spatial region within the substrate body.
Optionally, the first surface of the substrate body is used for laying crystal grains; the second metal wire used for electric connection of the second via hole and the first metal wire used for electric connection of the first via hole are distributed in the substrate body in a layered mode, and the layer where the second metal wire is located is closer to the first surface of the substrate body relative to the layer where the first metal wire is located.
Optionally, the length of the first metal line is greater than a first length threshold, and the length of the second metal line is less than or equal to the first length threshold.
Optionally, a value range of the first length threshold is 4 mm to 6 mm.
In a second aspect, an embodiment of the present invention further provides a chip, including a substrate and at least one die disposed on the substrate, where the substrate is any one of the silicon-based substrates provided in the embodiments of the present invention, a first metal contact on the die is electrically connected to the first metal line in the substrate, and a second metal contact on the die is electrically connected to a second metal line in the substrate; the first metal wire is electrically connected with the first via hole, and the second metal wire is electrically connected with the second via hole.
In a third aspect, an embodiment of the present invention further provides a chip, including: the structure comprises a first substrate, a second substrate and a crystal grain, wherein the first substrate is any one of silicon-based substrates provided by the embodiment of the utility model; at least part of pins of the crystal grain are electrically connected with the metal contact on the first surface of the first substrate; metal wires are distributed in the first substrate and comprise at least one first metal wire and at least one second metal wire; a part of the metal contacts on the first surface of the first substrate are interconnected through the metal wires in the first substrate, and the other part of the metal contacts are electrically connected with the metal contacts on the second surface of the first substrate through the via holes and the metal wires in the first substrate; the metal contact on the second surface of the first substrate is electrically connected with the metal contact on the first surface of the second substrate, and the metal contact on the first surface of the second substrate is electrically connected with the metal contact on the second surface of the second substrate through a via hole and a metal wire in the second substrate.
Optionally, the first metal contact and the second metal contact on the first surface of the first substrate are interconnected through the first metal line; and/or the third metal contact and the fourth metal contact on the first surface of the first substrate are interconnected through the second metal wire.
Optionally, the minimum pitch between the metal contacts on the first surface of the first substrate is less than a first pitch threshold; a minimum pitch between metal contacts on the second surface of the second substrate is greater than a second pitch threshold, the first pitch threshold being less than the second pitch threshold.
Optionally, a minimum pitch between the metal contacts on the second surface of the first substrate is greater than the first pitch threshold and less than the second pitch threshold.
Optionally, the second substrate is a high-density interconnection printed circuit board.
Optionally, the second metal line and the first metal line are layered in the first substrate, the first metal line and the second metal line are located in different layers, and the thickness of the first metal line is greater than that of the second metal line.
Optionally, the width of the second metal line is less than 10 micrometers.
Optionally, the number of the grains includes one or more.
Optionally, the number of the first substrates includes one or more, and at least one die is disposed on each of the first substrates.
In the silicon-based substrate and the chip provided by the embodiment of the utility model, at least two via holes are arranged in the substrate body, and at least one via hole in the at least two via holes has any one of the following positions: one end of the substrate body is positioned on the first surface of the substrate body, and the other end of the substrate body is positioned in the substrate body; one end of the substrate body is positioned on the second surface of the substrate body, and the other end of the substrate body is positioned in the substrate body; one end of the substrate body is positioned on the first surface of the substrate body, and the other end of the substrate body is positioned on the second surface of the substrate body; both ends are located inside the base plate body. Therefore, the first surface and the second surface of the substrate body and the metal wires or the metal contacts in the substrate body are conveniently and electrically connected, so that abundant available resources are provided for interconnection of the crystal grain pins, and the cross section area of the first via hole is larger than that of the second via hole, and the cross section area of the first metal wire is larger than that of the second metal wire, so that the first via hole is conveniently and electrically connected with the first metal wire, and the second via hole is conveniently and electrically connected with the second metal wire, so that the crystal grain pins which are far away from each other are conveniently interconnected through the first metal wire with the larger cross section area, the attenuation of the metal wire impedance to signals is reduced, and the quality of the transmitted signals is ensured; meanwhile, the crystal grain pins with short distance are conveniently interconnected through the second metal wire with small cross section area so as to realize high-density signal transmission, and therefore, the short-distance high-density signal transmission and the long-distance low-loss signal transmission are conveniently realized through the same silicon-based substrate.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of a silicon-based substrate according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a via structure according to an embodiment of the present invention;
FIG. 3 is another schematic diagram of a via in an embodiment of the utility model;
FIG. 4 is a schematic diagram of another structure of a via in an embodiment of the utility model;
FIG. 5 is a schematic diagram of yet another via structure in an embodiment of the utility model;
FIG. 6 is a schematic illustration of another exemplary embodiment of a silicon-based substrate;
FIG. 7 is a schematic illustration of yet another exemplary embodiment of a silicon-based substrate;
FIG. 8 is a schematic illustration of yet another exemplary embodiment of a silicon-based substrate;
fig. 9 is a schematic structural diagram of a chip according to an embodiment of the present invention.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
It should be understood that the described embodiments are only some embodiments of the utility model, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In a first aspect, embodiments of the present invention provide a silicon-based substrate, which facilitates effective signal transmission with both short-range high-density signal transmission and long-range low-loss signal transmission through the same silicon-based substrate.
Fig. 1 is a side view of a silicon-based substrate according to an embodiment of the present invention. As shown in fig. 1, a silicon-based substrate provided by an embodiment of the present invention may include:
the structure comprises a substrate body 1, wherein at least two via holes 2 are arranged in the substrate body 1, the at least two via holes 2 comprise at least one first via hole 21 and at least one second via hole 22, and the cross sectional area of the first via hole 21 is larger than that of the second via hole 22; the first via 21 is used for electrically connecting a first metal wire 31 arranged in the substrate body 1, the second via 22 is used for electrically connecting a second metal wire 32 arranged in the substrate body 1, and the cross-sectional area of the first metal wire 31 is larger than that of the second metal wire 32; wherein at least one via of the at least two vias 2 has any of the following positions: one end is positioned on the first surface 11 of the substrate body 1, and the other end is positioned inside the substrate body 1; one end is positioned on the second surface 12 of the substrate body 1, and the other end is positioned inside the substrate body 1; one end is positioned on the first surface 11 of the substrate body 1, and the other end is positioned on the second surface 12 of the substrate body 1; both ends are positioned inside the substrate body 1; the first surface 11 of the substrate body 1 is used for laying the dies, and the second surface 12 faces away from the first surface 11.
In the silicon-based substrate provided by the embodiment of the present invention, at least two vias 2 are disposed in a substrate body 1, and at least one via of the at least two vias 2 has any one of the following positions: one end is positioned on the first surface 11 of the substrate body 1, and the other end is positioned inside the substrate body 1; one end is positioned on the second surface 12 of the substrate body 1, and the other end is positioned inside the substrate body 1; one end is positioned on the first surface 11 of the substrate body 1, and the other end is positioned on the second surface 12 of the substrate body 1; both ends are located inside the substrate body 1. Therefore, the first surface and the second surface of the substrate body and the metal wires or metal contacts in the substrate body are conveniently and electrically connected, so that abundant available resources are provided for interconnection of the crystal grain pins, and the cross sectional area of the first via hole 21 is larger than that of the second via hole 22, and the cross sectional area of the first metal wire 31 is larger than that of the second metal wire 32, so that the first via hole 21 is conveniently and electrically connected with the first metal wire 31, and the second via hole 22 is conveniently and electrically connected with the second metal wire 32, so that the crystal grain pins far away are conveniently interconnected through the first metal wire 31 with the larger cross sectional area, the attenuation of the metal wire impedance to signals is reduced, and the quality of the transmitted signals is ensured; meanwhile, the interconnection of the crystal grain pins with the closer distance is facilitated through the second metal wire 32 with the smaller cross section area, so that high-density signal transmission is realized, and both short-distance high-density signal transmission and long-distance low-loss signal transmission are facilitated through the same silicon-based substrate.
In the embodiment of the present invention, the via hole 2 may refer to any hole in the silicon-based substrate for electrically connecting metal lines of different layers. The via hole 2 can be further divided into the following cases according to whether the openings at the two ends of the via hole 2 are located on the surface of the substrate body 1. Here, the via hole 2 may include a first via hole 21 having a larger cross-sectional area, or may include a second via hole 22 having a smaller cross-sectional area.
As shown in fig. 2, in one embodiment of the present invention, one end of at least one via 2 of the at least two vias 2 may be located at the first surface 11 of the substrate body 1, and the other end may be located inside the substrate body 1. Such vias 2 may be used to electrically connect metal contacts on the first surface 11 of the substrate body 1 with metal lines inside the substrate body 1. Alternatively, as shown in fig. 3, in another embodiment of the present invention, one end of at least one via 2 of the at least two vias 2 may be located at the second surface 12 of the substrate body 1, and the other end may be located inside the substrate body 1. Such vias 2 may be used to electrically connect metal lines inside the substrate body 1 with metal contacts on the second surface 12 of the substrate body 1. Alternatively, as shown in fig. 4, in another embodiment of the present invention, one end of at least one via 2 of the at least two vias 2 may be located at the first surface 11 of the substrate body 1, and the other end may be located at the second surface 12 of the substrate body 1. Such vias 2 may be used to electrically connect metal contacts on the first surface 11 of the substrate body 1 with metal contacts on the second surface 12 of the substrate body 1. Alternatively, as shown in fig. 5, in a further embodiment of the present invention, both ends of at least one via 2 of the at least two vias 2 may be located inside the substrate body 1; such vias 2 may be used to electrically connect two metal lines of different layers inside the substrate body 1. Various interconnections of metal lines of different layers can be effectively realized through the via holes 2.
In specific implementation, whether the first via 21, the first metal line 31, the second via 22, and the second metal line 32 are used for interconnection between die pins may be determined as required. Because the cross-sectional areas of the first via 21 and the first metal line 31 are larger, the signal transmission at a longer distance can be supported, and based on this, in an embodiment of the present invention, the length of the first metal line 31 can be larger than a first length threshold, so that when the signal transmission distance is larger than the first length threshold, the first metal line 31 and the first via 21 are used for interconnection. In contrast, the length of the second metal line 32 may be less than or equal to the first length threshold, so that when the signal transmission distance is less than or equal to the first length threshold, the second metal line 32 and the second via 22 are used for interconnection. Optionally, the first length threshold may be different according to the conductivity of the metal wire, and the better the conductivity, the larger the first length threshold, the worse the conductivity, and the smaller the first length threshold. For example, in one embodiment of the present invention, for a metal wire made of copper metal, the first length threshold may range from 4 mm to 6 mm, and typically may range from 5 mm.
In an embodiment of the present invention, the size of the via 2 can be represented by the cross-sectional area of the via, with larger vias having larger cross-sectional areas and smaller vias having smaller cross-sectional areas. Since the first via hole 21 and the first metal line 31 are suitable for long-distance low-loss signal transmission, and the second via hole 22 and the second metal line 32 are suitable for short-distance high-density signal transmission, that is, the two have different task division, in order to more effectively complete the long-distance low-loss signal transmission task and the short-distance high-density signal transmission task, in an embodiment of the present invention, the cross-sectional area of the first via hole 21 and the cross-sectional area of the second via hole 22 may be made to have a larger difference. For example, in one embodiment of the present invention, the cross-sectional area of the first via 21 may be greater than a first area threshold, and the cross-sectional area of the second via 22 may be less than a second area threshold, wherein the first area threshold is greater than or equal to the second area threshold. The specific values of the first area threshold and the second area threshold may be set or adjusted according to specific process parameters. Alternatively, in order to make the cross-sectional area of the first via 21 and the cross-sectional area of the second via 22 have a large difference, in another embodiment of the present invention, the difference between the cross-sectional area of the first via 21 and the cross-sectional area of the second via 22 may be defined by a ratio of the cross-sectional area of the first via 21 to the cross-sectional area of the second via 22. For example, the ratio of the cross-sectional area of the first via 21 to the cross-sectional area of the second via 22 may be greater than or equal to a first ratio threshold, and optionally, the first ratio threshold may be, for example, 2:1, 4:1, 5:1, 9:1, 16:1, and the like.
In the embodiment of the present invention, the first via 21 and the second via 22 are for electrically connecting metal lines at different layers in the substrate body, and therefore, the specific shape of each via 2 is not limited as long as the above-mentioned effective electrical connection can be achieved, for example, each via 2 may be a circle, an ellipse, a rectangle, a polygon, etc., the specific shape may be set and changed according to the layout, and the shapes of the vias 2 may be the same or different.
Further, since the interconnection of the die leads is often complex and varied, there may be various situations in the distribution of metal lines and vias used for interconnection in order to achieve such interconnection. For example, a plurality of layers of metal lines may be disposed on the substrate, an insulating dielectric layer may be disposed between adjacent layers of metal lines, and any two metal lines in different layers may be electrically connected through the via 2, where the first metal line 31 having a larger cross-sectional area may be electrically connected through the first via 21, and the second metal line 32 having a smaller cross-sectional area may be electrically connected through the second via 22.
Optionally, in order to facilitate electrical connection between metal lines of different layers, the positions of the vias 2 may be set at any positions or arranged at any positions as needed, which is not limited in the embodiment of the present invention. For example, in an embodiment of the present invention, a certain distribution area may be planned for the first vias 21, a certain distribution area may be planned for the second vias 22, so that the distribution of the two vias in the substrate is significantly limited, or the first vias 21 and the second vias 22 may be distributed in a staggered manner or randomly, so that the vias are distributed more uniformly in the substrate, and the stress and the electrical performance are more optimized.
For example, as shown in fig. 6 to 8, in one embodiment of the present invention, the first via 21 and the second via 22 may be alternately arranged in a direction parallel to the first surface 11 of the substrate body 1 and/or in a direction perpendicular to the first surface 11 of the substrate body 1 in at least a partial spatial region within the substrate body 1. Here, the first surface 11 of the substrate body 1 may be any surface of the substrate body 1, and may be a surface for laying out a die, for example. Wherein the first via holes 21 and the second via holes 22 in fig. 6 are arranged alternately in a direction parallel to the first surface 11 of the substrate body 1, the first via holes 21 and the second via holes 22 in fig. 7 are arranged alternately in a direction perpendicular to the first surface 11 of the substrate body 1, and the first via holes 21 and the second via holes 22 in fig. 8 are arranged alternately in a direction parallel to the first surface 11 of the substrate body 1 and in a direction perpendicular to the first surface 11 of the substrate body 1.
As mentioned above, the first via 21 and the first metal line 31 are more suitable for signal transmission with low loss at a longer distance because of their larger cross-sectional areas, and the second via 22 and the second metal line 32 are more suitable for signal transmission with high density at a shorter distance because of their smaller cross-sectional areas. In an embodiment of the present invention, since the first surface 11 of the substrate body 1 is used for laying the die, in order to make the length of the second metal line 32 as short as possible so as to avoid causing more signal loss, the second metal line 32 for electrically connecting the second via 22 and the first metal line 31 for electrically connecting the first via 21 may be laid in layers in the substrate body 1, wherein the layer where the second metal line 32 is located may be closer to the first surface 11 of the substrate body 1, that is, closer to the die, than the layer where the first metal line 31 is located. Since the first metal lines 31 of different layers are electrically connected through the first vias 21 and the second metal lines 32 of different layers are electrically connected through the second vias 22, the second vias 22 may be relatively close to the first surface 11 of the substrate body 1 in distribution. For example, in one embodiment of the present invention, one end of the second via 22 may be located at the first surface 11 of the substrate body 1, and the other end may be located inside the substrate body 1.
Optionally, in an embodiment of the present invention, the layer where the first metal line 31 is located may be closer to the first surface 11 of the substrate body 1 or closer to the second surface 12 of the substrate body 1, and accordingly, the first via 21 for electrically connecting the first metal line 31 may not be particularly limited in distribution. For example, in one embodiment of the present invention, one end of the first via 21 may be located at the first surface 11 of the substrate body 1 and the other end may be located inside the substrate body 1, or one end of the first via 21 may be located at the second surface 12 of the substrate body 1 and the other end is located inside the substrate body 1, or one end of the first via 21 may be located at the first surface 11 of the substrate body 1 and the other end may be located at the second surface 12 of the substrate body 1, or both ends of the first via 21 may be located inside the substrate body 1.
Correspondingly, the embodiment of the utility model also provides a chip, which is convenient for effectively considering both short-distance high-density signal transmission and long-distance low-loss signal transmission through the same silicon-based substrate.
The chip provided by the embodiment of the utility model may include a substrate and at least one die disposed on the substrate, where the substrate is any one of the silicon-based substrates provided by the foregoing embodiments, a first metal contact on the die is electrically connected to the first metal wire in the substrate, and a second metal contact on the die is electrically connected to a second metal wire in the substrate; the first metal wire is electrically connected with the first via hole, and the second metal wire is electrically connected with the second via hole.
The chip provided by the embodiment of the present invention utilizes any one of the silicon-based substrates provided by the foregoing embodiments to perform die interconnection, so that corresponding beneficial technical effects can be achieved.
Correspondingly, the embodiment of the utility model also provides a chip which is convenient for effectively considering both short-distance high-density signal transmission and long-distance low-loss signal transmission through the same silicon-based substrate.
As shown in fig. 9, a chip provided by an embodiment of the utility model may include: a first substrate 10, a second substrate 20 and a crystal grain 30; wherein, the first substrate 10 is any one of the silicon-based substrates provided in the foregoing embodiments; at least part of the pins of the die 30 are electrically connected to the metal contacts 110 on the first surface 101 of the first substrate 10; the first substrate 10 has metal lines 102 disposed therein, where the metal lines 102 may include at least one first metal line 1021 and at least one second metal line 1022, and a cross-sectional area of the first metal line 1021 is greater than a cross-sectional area of the second metal line 1022;
a part of the metal contacts on the first surface 101 of the first substrate 10 may be interconnected through the metal lines 102 in the first substrate 10, and another part of the metal contacts may be electrically connected with the metal contacts 140 on the second surface 104 of the first substrate 10 through the vias 103 and the metal lines 102 in the first substrate 10;
the metal contacts 140 on the second surface 104 of the first substrate 10 are electrically connected to the metal contacts on the first surface 201 of the second substrate 20, and the metal contacts on the first surface 201 of the second substrate 20 are electrically connected to the metal contacts on the second surface 204 of the second substrate 20 through vias 203 and metal lines 202 in the second substrate 20.
In the chip provided by the embodiment of the present invention, at least a portion of the leads of the die 30 are electrically connected to the metal contacts 110 on the first surface 101 of the first substrate 10, the metal lines 102 are disposed in the first substrate 10, a portion of the metal contacts on the first surface 101 of the first substrate 10 can be interconnected through the metal lines 102 in the first substrate 10, and another portion of the metal contacts can be electrically connected to the metal contacts 140 on the second surface 104 of the first substrate 10 through the vias 103 and the metal lines 102 in the first substrate 10, and further electrically connected to the second substrate 20, because the metal lines 102 in the first substrate 10 include both the first metal lines 1021 with a larger cross-sectional area and the second metal lines 1022 with a smaller cross-sectional area, the die leads with a larger cross-sectional area can be interconnected through the first metal lines 1021 to reduce the attenuation of the signal caused by the metal line impedance, ensuring the quality of the transmitted signals; meanwhile, the die pins with a short distance can be interconnected through the second metal wire 1022 with a small cross-sectional area, so that high-density signal transmission is realized, and short-distance high-density signal transmission and long-distance low-loss signal transmission are realized.
It should be noted that the various metal contacts described in the embodiments of the present invention may be generally referred to as metal contacts having an electrical connection function, and the specific form and shape of the metal contacts are not limited, for example, the metal contacts may be planar metal contacts, or may be metal bumps or metal balls protruding from the surface.
Optionally, in an embodiment of the present invention, the packaged chip may include one or more dies 30, and the dies 30 may be disposed on one or more first substrates 10, that is, the number of the dies 30 may include one or more, the number of the first substrates 10 may also include one or more, each first substrate 10 may be disposed on the second substrate 20, where one or more dies 30 may be disposed on each first substrate 10.
Alternatively, the second substrate 20 may be a variety of substrates suitable for chip packaging, for example, in one embodiment of the present invention, the second substrate 20 may be a high-density interconnect printed circuit board.
In a specific implementation, in order to more effectively achieve the effect of reducing signal loss of the first metal line 1021 and the effect of increasing signal interconnection density of the second metal line 1022 when interconnecting pin signals of a die, in an embodiment of the present invention, cross-sectional areas of the first metal line 1021 and the second metal line 1022 may have a larger difference, for example, the cross-sectional area of the first metal line 1021 may be greater than a first area threshold, and the cross-sectional area of the second metal line 1022 may be smaller than a second area threshold, where the first area threshold may be greater than or equal to the second area threshold, and for example, the first area threshold may be one of the following area thresholds: 4 square microns, 10 square microns, 100 square microns. In addition, the width of the second metal line 1022 may also be limited, for example, the width of the second metal line 1022 may be limited to be less than 10 micrometers, so that more second metal lines 1022 may be disposed on a unit area of the first substrate 10, and the signal interconnection density of the second metal lines 1022 is effectively improved.
The chip provided by the embodiment of the present invention may refer to a chip product obtained by packaging the die 30. In order to realize signal interconnection between different pins of the same die 30 or interconnection between pins of different dies 30, in an embodiment of the present invention, the die 30 may be disposed on the first substrate 10 to realize the signal interconnection through the metal wires 102 disposed in the first substrate 10. Alternatively, in the case of laying multiple layers of metal lines 102 in the first substrate 10, the metal lines 102 of different layers may be further electrically connected through vias 103 in the first substrate 10.
Further, in order to facilitate the application of the chip, for example, to facilitate the placement of the packaged chip on a device motherboard or connection with other external circuits, in an embodiment of the utility model, the first substrate 10 may, in addition to signal interconnection of the pins of the die 30 through the metal lines 102, lead out the pin signals of the die 30 to the second substrate 20 through the metal lines 102 and the vias 13, so as to be electrically connected with the device motherboard or other external circuits through the second substrate 20.
Alternatively, the metal lines 102 for interconnecting the die pin signals or the metal lines 102 for leading out the die pin signals to the second substrate 20 may be implemented by using the first metal lines 1021 with a larger cross-sectional area or the second metal lines 1022 with a smaller cross-sectional area according to the length of the path between the signal transmission terminals. For example, in one embodiment of the present invention, the first metal contact and the second metal contact on the first surface 101 of the first substrate 10 may be interconnected by a first metal line 1021; and/or the third metal contact and the fourth metal contact on the first surface 101 of the first substrate 10 may be interconnected by the second metal line 1022. That is, in this embodiment, the metal line 102 for implementing signal interconnection of the die pins may include the first metal line 1021, the second metal line 1022, or both. Similarly, in another embodiment of the present invention, the metal lines 102 for leading out the die pin signals to the second substrate 20 may also include the first metal lines 1021, the second metal lines 1022, or both.
In order to facilitate selection of the first metal line 1021 or the second metal line 1022 for signal interconnection according to the length of the path between the signal transmission terminals, in an embodiment of the present invention, a certain range may be set for the lengths of the first metal line 1021 and the second metal line 1022. For example, the length of the first metal wire 1021 may be greater than a preset length threshold, and the length of the second metal wire 1022 may be less than or equal to the preset length threshold, and optionally, the value of the preset length threshold may range from 4 mm to 6 mm, for example, 5 mm. In this way, if the path between the signal transmission terminals is greater than the preset length threshold, the signal interconnection may be performed through the first metal line 1021, and if the path between the signal transmission terminals is less than or equal to the preset length threshold, the signal interconnection may be performed through the second metal line 1022.
In order to be able to transmit more signals in the first substrate 1, a larger number of metal lines 102 may be routed in the first substrate 10. When the metal lines 102 cannot be laid on one plane, the metal lines 102 may be laid in layers, and the metal lines 102 in different layers may be isolated from each other by an insulating dielectric layer. For example, in one embodiment of the present invention, the metal lines 102 may be disposed in one or more layers in the first substrate 10, and an insulating dielectric layer is disposed between the metal lines 102 in different layers. The metal lines 102 in different layers may be electrically connected through vias in the insulating dielectric layer. Optionally, in an embodiment of the present invention, the via 103 in the first substrate 10 may include at least one first via and at least one second via, where the first via may be electrically connected to the first metal line 1021, the second via may be electrically connected to the second metal line 1022, and a cross-sectional area of the first via is greater than a cross-sectional area of the second via.
Alternatively, the first metal line 1021 and the second metal line 1022 may be in the same layer or in different layers. For example, in an embodiment of the present invention, the second metal lines 1022 and the first metal lines 1021 are layered in the first substrate 10, and the layer of the second metal lines 1022 is closer to the first surface 101 of the first substrate 10 than the layer of the first metal lines 1021. In this way, since the die 30 is disposed on the first surface 101 of the first substrate 10, the second metal line 1022 is closer to the die 30 than the first metal line 1021, so that the length of the second metal line 1022 can be effectively reduced, and the signal transmission loss of the second metal line 1022 can be reduced.
Further, in the case that the first metal line 1021 and the second metal line 1022 are in the same layer, the difference of the cross-sectional area of the first metal line 1021 and the second metal line 1022 can be realized by different widths of the metal lines. When the first metal line 1021 and the second metal line 1022 are in different layers, the difference in cross-sectional area between the first metal line 1021 and the second metal line 1022 can be achieved by different widths and/or different thicknesses of the metal lines. For example, in an embodiment of the present invention, the second metal lines 1022 and the first metal lines 1021 are layered in the first substrate 10, the first metal lines 1021 and the second metal lines 1022 are in different layers, and the thickness of the first metal lines 1021 may be greater than that of the second metal lines 1022.
Generally, the die 30 has a smaller area and volume relative to the packaged chip product, and therefore the pin pitch of the same die 30 is smaller, for example, in an embodiment of the present invention, the minimum distance between the pins of the same die 30 may be 40 microns to 150 microns. The minimum spacing between pads in external circuits such as motherboards is typically large, such as 800 microns to 1000 microns. In view of this, in order to be suitable for connecting the die 30 with an external circuit such as a motherboard, in the embodiment of the utility model, transition may be performed through the first substrate 1 and the second substrate 2, so as to gradually transition the pin pitch of 40 micrometers to 150 micrometers to the pad pitch of 800 micrometers to 1000 micrometers.
Specifically, in one embodiment of the present invention, in a chip package, the die 30 may be disposed on the first surface 101 of the first substrate 10 by a flip-chip bonding process, for example, and the first substrate 10 may also be disposed on the first surface 201 of the second substrate 20 by a flip-chip bonding process, for example, and the second surface 204 of the second substrate 20 may be used for electrical connection with an external circuit such as a motherboard. The minimum spacing between the metal contacts 110 on the first surface 101 of the first substrate 10 may be less than a first spacing threshold, and the minimum spacing between the metal contacts on the second surface 204 of the second substrate 20 may be greater than a second spacing threshold, wherein the first spacing threshold may be less than the second spacing threshold. For example, in one example, the first pitch threshold may be 100 microns and the second pitch threshold may be 800 microns.
In order to smoothly transition from the minimum pitch between the metal contacts 110 on the first surface 101 of the first substrate 10 to the minimum pitch between the metal contacts on the second surface 204 of the second substrate 20, in one embodiment of the present invention, the minimum pitch between the metal contacts 140 on the second surface 104 of the first substrate 10 may be further defined, for example, the minimum pitch between the metal contacts 140 on the second surface 104 of the first substrate 10 may be greater than the first pitch threshold and less than the second pitch threshold. For example, in one example, the minimum spacing between the metal contacts 140 may be 350 microns to 600 microns.
It can be understood that, since the first substrate 10 is disposed on the first surface 201 of the second substrate 20 through the flip-chip bonding process, the metal contacts 140 on the second surface 104 of the first substrate 10 may correspond to the metal contacts on the first surface 201 of the second substrate 20, i.e., the minimum pitch between the metal contacts is equal to the minimum pitch between the metal contacts 140.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on differences from other embodiments.
In particular, as for the apparatus embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
For convenience of description, the above devices are described separately in terms of functional division into various units/modules. Of course, the functionality of the various units/modules may be implemented in the same software and/or hardware in the implementation of the utility model.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (18)

1. A silicon-based substrate, comprising:
the circuit board comprises a substrate body, wherein at least two via holes are arranged in the substrate body, the at least two via holes comprise at least one first via hole and at least one second via hole, and the cross sectional area of the first via hole is larger than that of the second via hole; the first via hole is used for electrically connecting a first metal wire arranged in the substrate body, the second via hole is used for electrically connecting a second metal wire arranged in the substrate body, and the cross-sectional area of the first metal wire is larger than that of the second metal wire;
wherein at least one of the at least two vias has any of the following:
one end of the substrate body is positioned on the first surface of the substrate body, and the other end of the substrate body is positioned in the substrate body;
one end of the substrate body is positioned on the second surface of the substrate body, and the other end of the substrate body is positioned in the substrate body;
one end of the substrate body is positioned on the first surface of the substrate body, and the other end of the substrate body is positioned on the second surface of the substrate body;
both ends are positioned in the substrate body;
the first surface of the substrate body is used for arranging crystal grains, and the second surface and the first surface are opposite.
2. The silicon-based substrate of claim 1, wherein a cross-sectional area of the first via is greater than a first area threshold and a cross-sectional area of the second via is less than a second area threshold, wherein the first area threshold is greater than or equal to the second area threshold.
3. The silicon-based substrate of claim 1, wherein a ratio of a cross-sectional area of the first via to a cross-sectional area of the second via is greater than or equal to a first ratio threshold.
4. The silicon-based substrate according to claim 3, wherein the first scale threshold is 2:1, 4:1, 5:1, 9:1, 16: 1.
5. The silicon-based substrate according to claim 1, characterized in that the first and second vias are staggered in a direction parallel to the first surface of the substrate body and/or in a direction perpendicular to the first surface of the substrate body within at least a partial spatial region within the substrate body.
6. The silicon-based substrate according to claim 1,
the first surface of the substrate body is used for arranging crystal grains;
the second metal wire used for electric connection of the second via hole and the first metal wire used for electric connection of the first via hole are distributed in the substrate body in a layered mode, and the layer where the second metal wire is located is closer to the first surface of the substrate body relative to the layer where the first metal wire is located.
7. The silicon-based substrate of claim 1, wherein the length of the first metal line is greater than a first length threshold, and the length of the second metal line is less than or equal to the first length threshold.
8. The silicon-based substrate according to claim 7, wherein the first length threshold has a value in a range from 4 mm to 6 mm.
9. A chip comprising a substrate and at least one die disposed on the substrate, wherein the substrate is a silicon-based substrate according to any one of claims 1 to 8, a first metal contact on the die is electrically connected to the first metal line in the substrate, and a second metal contact on the die is electrically connected to a second metal line in the substrate; the first metal line is electrically connected with the first via hole, and the second metal line is electrically connected with the second via hole.
10. A chip, comprising: a first substrate, a second substrate and a die, wherein the first substrate is the silicon-based substrate of any one of claims 1 to 8; at least part of pins of the crystal grain are electrically connected with the metal contact on the first surface of the first substrate; metal wires are distributed in the first substrate and comprise at least one first metal wire and at least one second metal wire;
a part of the metal contacts on the first surface of the first substrate are interconnected through the metal wires in the first substrate, and the other part of the metal contacts are electrically connected with the metal contacts on the second surface of the first substrate through the via holes and the metal wires in the first substrate;
the metal contact on the second surface of the first substrate is electrically connected with the metal contact on the first surface of the second substrate, and the metal contact on the first surface of the second substrate is electrically connected with the metal contact on the second surface of the second substrate through a via hole and a metal wire in the second substrate.
11. The chip of claim 10,
the first metal contact and the second metal contact on the first surface of the first substrate are interconnected through the first metal wire; and/or the presence of a gas in the gas,
the third metal contact and the fourth metal contact on the first surface of the first substrate are interconnected through the second metal line.
12. The chip of claim 10, wherein a minimum pitch between metal contacts on the first surface of the first substrate is less than a first pitch threshold; a minimum pitch between metal contacts on the second surface of the second substrate is greater than a second pitch threshold, the first pitch threshold being less than the second pitch threshold.
13. The chip of claim 12, wherein a minimum pitch between metal contacts on the second surface of the first substrate is greater than the first pitch threshold and less than the second pitch threshold.
14. The chip of claim 10, wherein the second substrate is a high-density interconnect printed circuit board.
15. The chip of claim 10, wherein the second metal line and the first metal line are layered in the first substrate, the first metal line and the second metal line are in different layers, and a thickness of the first metal line is greater than a thickness of the second metal line.
16. The chip of claim 10, wherein the width of the second metal line is less than 10 microns.
17. The chip of claim 10, wherein the number of dies comprises one or more.
18. The chip of claim 10, wherein the number of the first substrates comprises one or more, and each of the first substrates has at least one die disposed thereon.
CN202220583934.2U 2022-03-17 2022-03-17 Silicon-based substrate and chip Active CN216902914U (en)

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