TWI737363B - One-sided electrical measurement technology for packaging substrate - Google Patents
One-sided electrical measurement technology for packaging substrate Download PDFInfo
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- TWI737363B TWI737363B TW109121325A TW109121325A TWI737363B TW I737363 B TWI737363 B TW I737363B TW 109121325 A TW109121325 A TW 109121325A TW 109121325 A TW109121325 A TW 109121325A TW I737363 B TWI737363 B TW I737363B
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Description
本發明係有關於一種用於封裝基板之電性量測技術,特別是指一種封裝基板以及用於封裝基板之同側電性量測方法。The present invention relates to an electrical measurement technology for packaging substrates, and in particular to a packaging substrate and a same-side electrical measurement method for packaging substrates.
現有的半導體製程中,扇出式晶圓封裝(fan-out wafer level package,FOPLP)被認為是具有成本效益的下一代高集成封裝IC技術。圖1A係為一習知扇出式晶圓封裝之封裝基板10,其包括載板11、再分佈層(redistribution layer,RDL)13。再分佈層13具有一或複數個疊合之介電層14、15,每一介電層14、15具有複數個導電通孔16、17。該等複數個導電通孔16、17上覆蓋著導電圖案18、19,因而形成多層之再分佈電路,以連接不同介電層之導電圖案。參考圖1A與圖1B,封裝基板10接著與晶片20接合,再塗佈封裝材料30,以完成晶片20的封裝,如圖1B所示。In the existing semiconductor manufacturing process, fan-out wafer level package (FOPLP) is considered to be a cost-effective next-generation highly integrated packaging IC technology. FIG. 1A shows a conventional fan-out wafer
如上所述,如果要知道封裝基板10是否為良品,必須在封裝基板10與晶片20接合之後才能進行電性量測。如此一來,一旦封裝基板10之再分佈電路不正常工作時,必須連同已經接合的晶片20一起報廢,損失甚大。As mentioned above, if it is necessary to know whether the
因此,如何能夠在封裝基板10與晶片20接合之前即對於封裝基板10之再分佈電路進行檢測之技術,以減少晶片20因為封裝基板10的故障而一起報廢之風險,進而提升封裝晶片之良率,已成為電子封裝產業與其相關電子產業的重要研發課題之一。Therefore, how to detect the redistribution circuit of the
有鑑於此,本發明提供一種用於封裝基板之電性量測技術,藉由導電黏著層的使用,可以實現一種封裝基板以及用於封裝基板之同側電性量測方法。In view of this, the present invention provides an electrical measurement technology for a package substrate. By using a conductive adhesive layer, a package substrate and a same-side electrical measurement method for the package substrate can be realized.
為達上述目的,於一實施例中,本發明提出一種用於封裝基板之同側電性量測方法,包括以下步驟:提供載板;塗佈導電黏著層於載板上;形成再分佈層,透過導電黏著層而黏合於載板上,再分佈層具有一或複數個疊合之介電層,每一介電層具有複數個導電通孔,複數個導電通孔上覆蓋著導電圖案,因而形成多層之再分佈電路,以連接不同介電層之導電圖案;以及在再分佈層上提供一對電極性相反之量測探針,以量測再分佈層之同側上的任兩個導電通孔之間的電阻值,以判斷同側上任兩個導電通孔之間的導通性。In order to achieve the above objective, in one embodiment, the present invention provides a method for measuring the same-side electrical properties of a package substrate, which includes the following steps: providing a carrier; coating a conductive adhesive layer on the carrier; forming a redistribution layer , Bonded to the carrier through the conductive adhesive layer, the redistribution layer has one or more stacked dielectric layers, each dielectric layer has a plurality of conductive vias, and the plurality of conductive vias are covered with conductive patterns, thus forming Multi-layer redistribution circuit to connect the conductive patterns of different dielectric layers; and provide a pair of measurement probes with opposite polarity on the redistribution layer to measure any two conductions on the same side of the redistribution layer The resistance value between the holes is used to determine the continuity between any two conductive vias on the same side.
於一實施例中,載板係由玻璃、塑膠、印刷電路板或其他介電材料所形成。In one embodiment, the carrier board is formed of glass, plastic, printed circuit board or other dielectric materials.
於一實施例中,複數個導電通孔與複數個導電圖案係由沉積製程、微影製程、與蝕刻製程而形成。In one embodiment, the plurality of conductive vias and the plurality of conductive patterns are formed by a deposition process, a photolithography process, and an etching process.
於一實施例中,導電黏著層係可剝離,以將再分佈層與載板分離。In one embodiment, the conductive adhesive layer can be peeled off to separate the redistribution layer from the carrier.
於一實施例中,用於封裝基板之同側電性量測方法,更包括以下步驟:移除導電黏著層與載板;以及在再分佈層上提供一對電極性相反之量測探針,以量測再分佈層之同側上的任兩個導電通孔之間的電阻值,以判斷同側上任兩個導電通孔之間的絕緣性。In one embodiment, the same-side electrical measurement method for the package substrate further includes the following steps: removing the conductive adhesive layer and the carrier; and providing a pair of measurement probes with opposite electrical polarity on the redistribution layer , To measure the resistance between any two conductive vias on the same side of the redistribution layer to determine the insulation between any two conductive vias on the same side.
於另一實施例中,本發明提出一種封裝基板,包括:載板;導電黏著層,係塗佈於載板上;以及再分佈層,透過導電黏著層而黏合於載板上,再分佈層具有一或複數個疊合之介電層,每一介電層具有複數個導電通孔,複數個導電通孔上覆蓋著導電圖案,因而形成多層之再分佈電路,以連接不同介電層之導電圖案。In another embodiment, the present invention provides a package substrate including: a carrier; a conductive adhesive layer coated on the carrier; and a redistribution layer, which is adhered to the carrier through the conductive adhesive layer, and the redistribution layer With one or more stacked dielectric layers, each dielectric layer has a plurality of conductive vias, and the plurality of conductive vias are covered with conductive patterns, thus forming a multilayer redistribution circuit to connect the conductive patterns of different dielectric layers .
綜合上述,本發明提供一種用於封裝基板之電性量測技術,藉由導電黏著層的使用,可以實現一種封裝基板以及用於封裝基板之同側電性量測方法,進而在封裝基板與晶片接合之前即對於封裝基板之再分佈電路進行檢測,以減少晶片因為封裝基板的故障而一起報廢之風險,並且提升封裝晶片之良率。In summary, the present invention provides an electrical measurement technology for packaging substrates. Through the use of a conductive adhesive layer, a packaging substrate and a method for electrical measurement on the same side of the packaging substrate can be realized. Before chip bonding, the redistribution circuit of the package substrate is tested to reduce the risk that the chip will be scrapped due to the failure of the package substrate and improve the yield of the packaged chip.
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.
請配合參考圖2A,其顯示本發明封裝基板50的橫截面示意圖以及進行同側電性量測之實施例。在圖2A中,首先提供載板11。接著,塗佈導電黏著層12於載板11上。之後,形成再分佈層13,其透過導電黏著層12而黏合於載板11上。再分佈層13具有一或複數個疊合之介電層14、15。於一實施例中,可以使用兩層介電層14、15。然而,本發明之範圍並不受限於疊合之介電層之數目。於一實施例中,每一介電層具有複數個導電通孔16、17,其上方覆蓋著導電圖案18、19,因而形成多層之再分佈電路,以透過導電通孔16、17連接不同介電層14、15之導電圖案18、19。接著,在再分佈層13上提供一對電極性相反之量測探針40、41。藉由導電黏著層12之導電特性,可以量測再分佈層之同側上的任兩個導電通孔之間的電阻值,以判斷同側上任兩個導電通孔16之間的導通性。Please refer to FIG. 2A, which shows a schematic cross-sectional view of the
於一實施例中,載板11係由玻璃、塑膠、印刷電路板或其他介電材料所形成。於一實施例中,介電層14、15係由沉積製程、微影製程、與蝕刻製程而形成。詳而言之,在介電層14形成後,形成複數個開口,再利用導電材料的沉積與研磨,形成複數個導電通孔16,其上方再接著形成導電圖案18。同理,在以沉積製程形成介電層15後,形成複數個開口,再利用導電材料的沉積與研磨,形成複數個導電通孔17,其上方再接著形成導電圖案19。In one embodiment, the
簡言之,複數個導電通孔16、17與複數個導電圖案18、19係由沉積製程、微影製程、與蝕刻製程而形成。上述相關的半導體製程已為本技術領域中的人士所知悉,其詳細製程在此不予贅述。In short, the plurality of
於一實施例中,導電黏著層12係可剝離,以將再分佈層13與載板11分離。基於上述特性,請配合參考圖2B,其顯示本發明封裝基板60的橫截面示意圖以及進行同側電性量測之另一實施例。於一實施例中,可以從封裝基板60中移除導電黏著層12與載板11。接著,在再分佈層13上提供一對電極性相反之量測探針40、41,以量測再分佈層之同側上的任兩個導電通孔之間的電阻值。由於此時已經沒有導電黏著層12來傳導另一側的電流,可以藉以判斷同側上任兩個導電通孔16之間的絕緣性。In one embodiment, the conductive
因此,於另一實施例中,請配合參考圖2A,本發明提出一種封裝基板50,包括載板11;導電黏著層12,係塗佈於載板11上;以及再分佈層13,透過導電黏著層12而黏合於載板11上,再分佈層具有一或複數個疊合之介電層14、15,每一介電層14、15具有複數個導電通孔16、17,上方上覆蓋著導電圖案18、19,因而形成多層之再分佈電路,以連接不同介電層之導電圖案。藉由導電黏著層12之導電特性,可以在再分佈層13上提供一對電極性相反之量測探針40、41,以量測再分佈層之同側上的任兩個導電通孔16之間的電阻值,進而判斷同側上任兩個導電通孔16之間的導通性。Therefore, in another embodiment, please refer to FIG. 2A. The present invention provides a
於一實施例中,導電黏著層12係可剝離,以將再分佈層13與載板11分離,而形成圖2B所示之封裝基板60。由於此時已經沒有導電黏著層12來傳導另一側的電流,可以在再分佈層13上提供一對電極性相反之量測探針40、41,以量測再分佈層之同側上的任兩個導電通孔16之間的電阻值,進而判斷同側上任兩個導電通孔16之間的絕緣性。In one embodiment, the conductive
綜合上述,本發明提供一種用於封裝基板之電性量測技術,藉由導電黏著層的使用,可以實現一種封裝基板以及用於封裝基板之同側電性量測方法,進而在封裝基板與晶片接合之前即對於封裝基板之再分佈電路進行檢測,以減少晶片因為封裝基板的故障而一起報廢之風險,並且提升封裝晶片之良率。In summary, the present invention provides an electrical measurement technology for packaging substrates. Through the use of a conductive adhesive layer, a packaging substrate and a method for electrical measurement on the same side of the packaging substrate can be realized. Before chip bonding, the redistribution circuit of the package substrate is tested to reduce the risk that the chip will be scrapped due to the failure of the package substrate and improve the yield of the packaged chip.
雖然本發明的技術內容已經以較佳實施例揭露如上,然其並非用以限定本發明,任何熟習此技藝者,在不脫離本發明之精神所作些許之更動與潤飾,皆應涵蓋於本發明的範疇內,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the technical content of the present invention has been disclosed in the preferred embodiments as above, it is not intended to limit the present invention. Anyone who is familiar with this technique and makes some changes and modifications without departing from the spirit of the present invention should be covered by the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of the attached patent application.
10、50、60:封裝基板10, 50, 60: package substrate
11:載板11: Carrier board
12:導電黏著層12: Conductive adhesive layer
13:再分佈層13: Redistribution layer
14、15:介電層14, 15: Dielectric layer
16、17:導電通孔16, 17: conductive vias
18、19:導電圖案18, 19: conductive pattern
20:晶片20: chip
30:封裝材料30: Packaging materials
40、41:量測探針40, 41: Measuring probe
圖1A係習知封裝基板的橫截面示意圖; 圖1B係習知已完成封裝之晶片的橫截面示意圖; 圖2A係本發明封裝基板的橫截面示意圖以及進行同側電性量測之實施例;以及 圖2B係本發明封裝基板的橫截面示意圖以及進行同側電性量測之另一實施例。 Fig. 1A is a schematic cross-sectional view of a conventional package substrate; Figure 1B is a schematic cross-sectional view of a conventionally packaged chip; 2A is a schematic cross-sectional view of the package substrate of the present invention and an embodiment of performing electrical measurements on the same side; and 2B is a schematic cross-sectional view of the package substrate of the present invention and another embodiment of the same-side electrical measurement.
50:封裝基板 50: Package substrate
11:載板 11: Carrier board
12:導電黏著層 12: Conductive adhesive layer
13:再分佈層 13: Redistribution layer
14、15:介電層 14, 15: Dielectric layer
16、17:導電通孔 16, 17: conductive vias
18、19:導電圖案 18, 19: conductive pattern
40、41:量測探針 40, 41: Measuring probe
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TWI829063B (en) * | 2021-12-30 | 2024-01-11 | 漢民測試系統股份有限公司 | Testing substrate and manufacturing method thereof and probe card |
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WO2017111840A1 (en) * | 2015-12-26 | 2017-06-29 | Intel Corporation | Conductive base embedded interconnect |
US20190057912A1 (en) * | 2011-06-03 | 2019-02-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interposer Test Structures and Methods |
WO2020029096A1 (en) * | 2018-08-07 | 2020-02-13 | 深圳市为通博科技有限责任公司 | Chip package structure and manufacturing method therefor |
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US20190057912A1 (en) * | 2011-06-03 | 2019-02-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interposer Test Structures and Methods |
WO2017111840A1 (en) * | 2015-12-26 | 2017-06-29 | Intel Corporation | Conductive base embedded interconnect |
WO2020029096A1 (en) * | 2018-08-07 | 2020-02-13 | 深圳市为通博科技有限责任公司 | Chip package structure and manufacturing method therefor |
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TWI829063B (en) * | 2021-12-30 | 2024-01-11 | 漢民測試系統股份有限公司 | Testing substrate and manufacturing method thereof and probe card |
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