CN110310938A - A kind of semiconductor devices and electronic device - Google Patents
A kind of semiconductor devices and electronic device Download PDFInfo
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- CN110310938A CN110310938A CN201810231077.8A CN201810231077A CN110310938A CN 110310938 A CN110310938 A CN 110310938A CN 201810231077 A CN201810231077 A CN 201810231077A CN 110310938 A CN110310938 A CN 110310938A
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- redistribution dielectric
- sealing ring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
- H01L2224/02331—Multilayer structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02381—Side view
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/024—Material of the insulating layers therebetween
Abstract
The present invention provides a kind of semiconductor devices and electronic device, the semiconductor devices includes: semiconductor substrate, the semiconductor substrate includes master chip area, it is formed with interconnection layer in the semiconductor substrate for being located at the main core section, is formed with sealing ring between the main core section and Cutting Road；And second for being formed in the first redistribution dielectric layer of the upperside interconnection layer and being formed on first redistributing layer redistributes dielectric layer, is formed with the redistributing layer being electrically connected with the interconnection layer in the first redistribution dielectric layer；Wherein, the edge of the first redistribution dielectric layer is located at the top of the sealing ring, and the edge of the second redistribution dielectric layer is located at the top of the first redistribution dielectric layer.Semiconductor devices provided by the invention can reduce the edge stress of redistribution dielectric layer, the risk for generating cracking phenomena be reduced, so that chip be avoided to be damaged.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and electronic device.
Background technique
In IC design and manufacturing process, encapsulation is the integrated electricity of indispensable an important ring and semiconductor
The final stage of road manufacture.With the collection that the function of integrated circuit is increasingly stronger, performance and integrated level are higher and higher and novel
At the appearance of circuit, encapsulation technology plays an increasingly important role in IC products.Meanwhile with integrated circuit
Characteristic size reach nanoscale, transistor develops towards more high density, higher clock frequency, mentions to the encapsulation of integrated circuit
Increasingly higher demands are gone out.
When carrying out chip package, need the pad of chip top-layer and pad corresponding on lead frame or lead pair
It connects, can be connect chip with external circuit by lead frame in this way.Wherein, lead frame is generally mode standard, carries out
The pad locations of the chip of encapsulation on lead frame pad or wire locations it is not corresponding, it is therefore desirable to chip top-layer
Pad redistributed, allow pad on lead frame pad or lead be electrically connected.
Redistributing layer includes forming the metallized traces such as redistribution dielectric layer and aluminium/copper on the passivation layer, and redistribution is situated between
Matter layer is usually made of polymer material.When being packaged, redistribution dielectric layer is shunk at high temperature, to the passivation layer of lower section
Certain stress is generated, passivation layer is caused to crack, crackle easily extends to chip functions region, so as to cause chip failure.
Therefore, to solve the above-mentioned problems, it is necessary to propose a kind of new semiconductor devices and electronic device.
Summary of the invention
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.Summary of the invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection scope for attempting to determine technical solution claimed more.
In view of the deficiencies of the prior art, the present invention provides a kind of semiconductor devices, and the semiconductor devices includes:
Semiconductor substrate, the semiconductor substrate include master chip area, in the semiconductor for being located at the main core section
It is formed with interconnection layer on substrate, is formed with sealing ring between the main core section and Cutting Road；And
The for being formed in the first redistribution dielectric layer of the upperside interconnection layer and being formed on first redistributing layer
Two redistribute dielectric layers, are formed with the redistributing layer being electrically connected with the interconnection layer in the first redistribution dielectric layer；
Wherein, the edge of the first redistribution dielectric layer is located at the top of the sealing ring, and second redistribution is situated between
The edge of matter layer is located at the top of the first redistribution dielectric layer.
Illustratively, the semiconductor devices further includes the passivation being formed between the interconnection layer and the redistributing layer
Layer.
Illustratively, the semiconductor devices further includes that the crackle being formed between the sealing ring and the Cutting Road stops
Only area.
Illustratively, the material of the first redistribution dielectric layer and/or the second redistribution dielectric layer is polymer.
Illustratively, the material of the first redistribution dielectric layer and/or the second redistribution dielectric layer includes polyamides
Imines and/or polybenzoxazoles.
Illustratively, the width of the sealing ring is 6.8-7.2 microns.
Illustratively, the distance between the sealing ring and the crackle stop zone are 1.8-2.2 microns.
Illustratively, the first redistribution dielectric layer and/or the second redistribution dielectric layer have inclined side wall.
Illustratively, opening is formed in the passivation layer, the redistributing layer passes through the opening and the interconnection layer
Electrical connection.
Illustratively, the sealing ring is the stepped construction for including more metal layers.
Illustratively, the crackle stop zone is the stepped construction for including more metal layers.
The present invention also provides a kind of electronic device, the electronic device includes above-mentioned semiconductor devices.
Semiconductor devices provided by the invention can reduce the edge stress of redistribution dielectric layer, reduces and generates cracking now
The risk of elephant, so that chip be avoided to be damaged.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing:
Fig. 1 shows a kind of structural schematic diagram of existing semiconductor devices.
Fig. 2 shows the structural schematic diagrams for the semiconductor devices that one embodiment of the invention provides.
Fig. 3 shows the structural schematic diagram of electronic device according to an embodiment of the present invention.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.On the contrary, provide these embodiments will make it is open thoroughly and completely, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the area Ceng He may be exaggerated.From beginning to end
Same reference numerals indicate identical element.
It should be understood that when element or layer be referred to " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties by person.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or " being directly coupled to " other elements or when layer, then there is no elements or layer between two parties.It should be understood that although can make
Various component, assembly units, area, floor and/or part are described with term first, second, third, etc., these component, assembly units, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish a component, assembly unit, area, floor or part with it is another
One component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion
Part, area, floor or part are represented by second element, component, area, floor or part.
Spatial relation term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and being used describe an elements or features shown in figure with
The relationship of other elements or features.It should be understood that spatial relation term intention further includes making other than orientation shown in figure
With the different orientation with the device in operation.For example, then, being described as " under other elements if the device in attached drawing is overturn
Face " or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as limitation of the invention.Make herein
Used time, " one " of singular, "one" and " described/should " be also intended to include plural form, unless the context clearly indicates separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related listed item and institute
There is combination.
It describes to send out herein with reference to the cross-sectional view of the schematic diagram as desirable embodiment (and intermediate structure) of the invention
Bright embodiment.As a result, it is contemplated that from the variation of shown shape as caused by such as manufacturing technology and/or tolerance.Therefore,
The embodiment of the present invention should not necessarily be limited to the specific shape in area shown here, but including due to for example manufacturing caused shape
Shape deviation.For example, being shown as the injection region of rectangle usually has round or bending features and/or implantation concentration ladder at its edge
Degree, rather than binary from injection region to non-injection regions changes.Equally, which can lead to by the disposal area that injection is formed
Some injections in area between the surface passed through when injection progress.Therefore, the area shown in figure is substantially schematic
, their shape is not intended the true form in the area of display device and is not intended to limit the scope of the invention.
In order to thoroughly understand the present invention, detailed structure will be proposed in following description, to illustrate proposition of the present invention
Technical solution.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, the present invention can be with
With other embodiments.
When carrying out chip package, need the pad of chip top-layer and pad corresponding on lead frame or lead pair
It connects, can be connect chip with external circuit by lead frame in this way.Wherein, lead frame is generally mode standard, carries out
The pad locations of the chip of encapsulation on lead frame pad or wire locations it is not corresponding, it is therefore desirable to chip top-layer
Pad redistributed, allow pad on lead frame pad or lead be electrically connected.
Specifically, as shown in Figure 1, a kind of semiconductor devices includes: semiconductor substrate 100, the semiconductor substrate 100 is wrapped
Main core section 101 is included, is formed with device layer (not shown) and interconnection layer in the semiconductor substrate 100 for being located at master chip area 101
102, sealing ring 106 is formed on the outside of the main core section 101, and sealing ring outer layer is formed with crackle stop zone 107, the interconnection
102 top of layer is formed with passivation layer 103, and redistributing layer 104 and the first redistribution dielectric layer are formed with above passivation layer 103
105a, the second redistribution dielectric layer 105b.When being packaged, the first redistribution dielectric layer 105a, the second redistribution dielectric layer
105b is shunk at high temperature, generates certain stress to the passivation layer 103 of lower section, causes passivation layer 103 to crack, crack growth is extremely
Main core section 101, leads to chip failure.
In view of the above-mentioned problems, the present invention provides a kind of semiconductor devices, the semiconductor devices includes: semiconductor substrate,
The semiconductor substrate includes master chip area, is formed with interconnection layer in the semiconductor substrate for being located at the main core section,
Sealing ring is formed between the main core section and Cutting Road；And it is formed in first redistribution Jie of the upperside interconnection layer
Matter layer and be formed on first redistributing layer second redistribution dielectric layer, it is described first redistribution dielectric layer in be formed with
The redistributing layer being electrically connected with the interconnection layer；Wherein, the edge of the first redistribution dielectric layer is located at the sealing ring
Top, the edge of the second redistribution dielectric layer are located at the top of the first redistribution dielectric layer.
The semiconductor devices further includes the passivation layer being formed between the interconnection layer and the redistributing layer.
The semiconductor devices further includes the crackle stop zone being formed between the sealing ring and the Cutting Road.
The material of the first redistribution dielectric layer and/or the second redistribution dielectric layer is polymer.
It is described first redistribution dielectric layer and/or it is described second redistribution dielectric layer material include polyimides and/or
Polybenzoxazoles.
The width of the sealing ring is 6.8-7.2 microns.
The distance between the sealing ring and the crackle stop zone are 1.8-2.2 microns.
The first redistribution dielectric layer and/or the second redistribution dielectric layer have inclined side wall.
Opening is formed in the passivation layer, the redistributing layer is electrically connected by the opening with the interconnection layer.
The sealing ring is the stepped construction for including more metal layers.The crackle stop zone be include more metal layers
Stepped construction.
The present invention also provides a kind of electronic device, the electronic device includes above-mentioned semiconductor devices.
Semiconductor devices provided by the invention can reduce the edge stress of redistribution dielectric layer, reduces and generates cracking now
The risk of elephant, so that chip be avoided to be damaged.
In order to thoroughly understand the present invention, detailed structure and/or step will be proposed in following description, to illustrate this
Invent the technical solution proposed.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, this hair
It is bright to have other embodiments.
Below with reference to Fig. 2, the semiconductor devices of an embodiment of the present invention is described in detail.
As shown in Fig. 2, the semiconductor devices of the present embodiment includes: semiconductor substrate 200, the semiconductor substrate 200 is wrapped
Main core section 201 is included, is formed with interconnection layer 202, the main core in the semiconductor substrate 200 for being located at master chip area 201
Sealing ring 206 is formed between section 201 and Cutting Road (not shown).
Wherein, semiconductor substrate 200 can be following at least one of the material being previously mentioned: Si, Ge, SiGe, SiC,
SiGeC, InAs, GaAs, InP or other III/V compound semiconductors further include the multilayered structure etc. that these semiconductors are constituted
Or it is silicon-on-insulator (SOI), silicon (SSOI) is laminated on insulator, SiGe (S-SiGeOI), insulation is laminated on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on body.As an example, in the present embodiment, semiconductor substrate 200
Constituent material select monocrystalline silicon.
It is formed with device layer (not shown) and interconnection layer 202 on semiconductor substrate 200, wherein device layer may include all
Such as the various circuit structures that NMOS, PMOS transistor form, interconnection layer can be various interconnection structures, real for underlying device layer
It is now electrically connected, and interconnection structure can according to need the dielectric layer and metal layer that various quantity are arranged, such as 6 layers or 7 layers Jie
Electric layer and metal layer.In addition, can also be formed with isolation structure in the semiconductor substrate, the isolation structure is shallow trench isolation
(STI) structure or selective oxidation silicon (LOCOS) isolation structure.In the present embodiment, for purposes of brevity, interconnection is only shown
Top interconnection layers in layer.The top interconnection layers can be made as other interconnection layers by method commonly used in the art,
Such as dual-damascene technics.Illustratively, the forming process of the interconnection layer are as follows: pass through such as PVD (physical vapour deposition (PVD)), CVD
The conventional process such as (chemical vapor deposition) and ALD (atomic layer deposition) form dielectric layer.Then, by dual-damascene technics in dielectric
Form through-hole and groove in layer, fill metal into through-hole and groove finally by plating or depositing operation, for example, metallic copper or
Aluminium copper.
Interlayer dielectric layer is filled between interconnection layer, as the insulating materials and backing material between each metal layer.One
As, the material of interlayer dielectric layer is silica, phosphorus silicon compound or low K organo-silicon compound etc..In one embodiment, institute
The material for stating interlayer dielectric layer is such as silica, the general dielectric material of phosphorus silicon compound；In other embodiments, the layer
Between the material of dielectric layer also include low-K material layer, such as fluorine silica glass, carbonaceous material, porous material or homologue.
Sealing ring (seal ring) 206 is formed on the outside of main core section 201.In manufacture of semiconductor, in same crystalline substance
It is formed with multiple chips on circle, is divided between each chip by criss-cross region Cutting Road (scribe line), edge
Cutting Road wafer is carried out to be cut to one single chip.Chip area meeting in cutting process, positioned at Cutting Road periphery
By mechanical impact, to cause to generate local crackle and fragment on the cutting profile of the chip separated, crackle is again
It is readily extended to chip interior, deteriorated so as to cause chip or is failed.In addition, layer can be exposed in the side of the chip separated
Between dielectric layer, moisture, moisture etc. may invade chip interior from there, equally will cause the maloperation and destruction of chip.Therefore,
It needs to protect chip using sealing ring 206.Sealing ring 206 is arranged between Cutting Road and main core section 201, around master
Chip region 201 avoids carrying out scribing so that semiconductor substrate to be cut into for preventing electrostatic to the influence of main core section 201
Stress damage main core section 201 during with the chip for completelying integrate circuit structure, and prevent steam or other
Pollution, corrosive factor enter main core section 201.
In the present embodiment, crackle stop zone 207 is also formed between the sealing ring 206 and Cutting Road (not shown), it is close
Seal ring 206 and crackle stop zone 207 are the stepped construction including more metal layers.Illustratively, the stepped construction includes
The contact hole that is electrically connected with device region, several metal wiring layers for being parallel to semiconductor substrate, connect neighbouring hardware cloth
The conductive through hole of line layer, the pad being electrically connected with top metal wiring layer being formed in passivation layer 203 etc..Above layers are
It is formed with each corresponding layer in inside chip manufacturing process in same step, does not need additional manufacturing process, and
Above layers be not necessarily all it is necessary, different layer structures can be retained according to different chip technologies is prepared.
Passivation layer 203 is formed with above interconnection layer 202.The passivation layer 203 can protect top-level metallic wiring layer, keep away
Exempt from it in later period encapsulation process or use process by the destruction of external environment.Passivation layer 203 can be using various suitable
Passivation material, such as oxide, nitride or nitrogen oxides etc., and formed by techniques such as common PVD, CVD, ALD.Show
Example property, in the present embodiment, passivation layer 203 is composite layer comprising it is underlying for buffering the oxide skin(coating) of stress,
With the nitride layer being located on oxide layer, such as silicon oxynitride layer.After forming passivation layer 203, chemical wet etching can be passed through
Equal patterning process, form the opening for exposing metal layer at top in passivation layer 203.
It is formed with the first redistribution dielectric layer 205a above passivation layer 203 and is formed on the first redistributing layer 205a
Second redistribution dielectric layer 205b.Redistributing layer 204 is formed in first redistribution dielectric layer 205a.Redistributing layer 204 is used
It is laid out again in the port I/O to chip, is arranged into the region that new, pitch occupy-place can be more loose.First again
The redistribution dielectric layer 205b of distribution medium layer 205a and second is for protecting and being isolated redistributing layer 204.Specifically, first divides again
Cloth dielectric layer 205a can reinforce passivation layer 205, play the role of stress buffer.Second redistribution dielectric layer 205b makes chip surface
It planarizes and protects redistributing layer 204.Redistributing layer 204 can be with various suitable metal materials, illustratively, in the present embodiment
In, redistributing layer 204 uses metallic aluminium, can be formed by the various depositing operations such as sputtering, PVD, CVD.First redistribution
The material that dielectric layer 205a, second redistribute dielectric layer 205b is polymer, in the present embodiment, the first redistribution dielectric layer
205a, the second material for redistributing dielectric layer 205b include polyimides (PI) and/or polybenzoxazoles (PBO), polyimides
There is preferable heat-resisting quantity and dimensional stability with polybenzoxazoles.
In the present embodiment, in order to avoid due to the high temperature in encapsulation process cause redistribute dielectric layer shrink and to passivation
Cracking phenomena caused by the stress that layer generates, to the position of the first redistribution dielectric layer 205a, the second redistribution dielectric layer 205b
It sets and is optimized.Specifically, the edge of the first redistribution dielectric layer 205a is located at the top of the sealing ring 206, institute
The edge for stating the second redistribution dielectric layer 205b is located at the top of the first redistribution dielectric layer 205a.Applicant sends out through research
It is existing, if the edge of the first redistribution dielectric layer 205a or the second redistribution dielectric layer 205b are set to sealing ring 206 and crackle
Between stop zone 207, then redistribution dielectric layer edge peeling is easy to appear；If by the first redistribution dielectric layer 205a or the
The edge of two redistribution dielectric layer 205b is set between crackle stop zone 207 and Cutting Road, then reduces the width of Cutting Road,
Influence cutting.In contrast, using the device architecture of the present embodiment, the first redistribution dielectric layer 205a and the second redistribution medium
The edge stress of layer 205b is minimum, is not easy to cause cracking；Meanwhile it being also not susceptible to peeling, and do not influence to cut.At this
In embodiment, the first redistribution dielectric layer 205a, the second redistribution dielectric layer 205b have inclined side wall, thus further drop
The risk of low cracking and removing.
Further, since existing sealing ring width (about 5 microns) is difficult to meet encapsulation factory's process capability, in the present embodiment
In, also sealing ring 206 is optimized.Specifically, 207 side of sealing circumferential crack stop zone is widened, that is, exists
While increasing the width of sealing ring 206, reduce the distance between sealing ring 206 and crackle stop zone 207, is sealed without changing
The distance between ring 206 and main core section 201.As an example, the width of sealing ring 206 is had 5 microns of increasings in the prior art
Add to 6.8 microns -7.2 microns, such as 7 microns；And by the distance between sealing ring 206 and crackle stop zone 207 by existing skill
4 microns in art are decreased to 1.8 microns -2.2 microns, such as 2 microns.It as a result, can either be with optimized redistribution dielectric layer
Match, and does not increase the overall dimensions of device.
Semiconductor devices provided by the invention can reduce the edge stress of redistribution dielectric layer, reduces and generates cracking now
The risk of elephant, so that chip be avoided to be damaged.
The present invention also provides a kind of electronic devices, including above-mentioned semiconductor device.Wherein, which includes: half
Conductor substrate；The chip being formed in the semiconductor substrate；Around the sealing ring of the chip；Positioned at the chip with it is described
Isolated area between sealing ring is formed with several staggered barrier structures in the interlayer dielectric layer of the isolated area.
Wherein, the electronic building brick can be any electronic building bricks such as discrete device, integrated circuit.
The electronic device of the present embodiment can be mobile phone, tablet computer, laptop, net book, game machine, TV
Any electronic product such as machine, VCD, DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment can also be
Any intermediate products including the semiconductor devices.
Wherein, Fig. 3 shows the example of mobile phone.The outside of mobile phone 300 is provided with including the display portion in shell 301
302, operation button 303, external connection port 304, loudspeaker 305, microphone 306 etc..
The electronic device of the embodiment of the present invention, since the semiconductor devices for being included can reduce the side of redistribution dielectric layer
Fiber stress reduces the risk for generating cracking phenomena, so that chip be avoided to be damaged, therefore the electronic device equally have it is similar
The advantages of.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member
Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (12)
1. a kind of semiconductor devices, which is characterized in that the semiconductor devices includes:
Semiconductor substrate, the semiconductor substrate include master chip area, in the semiconductor substrate for being located at the main core section
On be formed with interconnection layer, be formed with sealing ring between the main core section and Cutting Road；And
Be formed in the first redistribution dielectric layer of the upperside interconnection layer and be formed on first redistributing layer second again
Distribution medium layer, it is described first redistribution dielectric layer in be formed with the redistributing layer being electrically connected with the interconnection layer；
Wherein, the edge of the first redistribution dielectric layer is located at the top of the sealing ring, the second redistribution dielectric layer
Edge be located at it is described first redistribution dielectric layer top.
2. semiconductor devices according to claim 1, which is characterized in that further include be formed in the interconnection layer and it is described again
Passivation layer between distribution layer.
3. semiconductor devices according to claim 1, which is characterized in that further include being formed in the sealing ring to cut with described
Crackle stop zone between cutting.
4. semiconductor devices according to claim 1, which is characterized in that the first redistribution dielectric layer and/or described
The material of second redistribution dielectric layer is polymer.
5. semiconductor devices according to claim 4, which is characterized in that the first redistribution dielectric layer and/or described
The material of second redistribution dielectric layer includes polyimides and/or polybenzoxazoles.
6. semiconductor devices according to claim 1, which is characterized in that the width of the sealing ring is 6.8-7.2 microns.
7. semiconductor devices according to claim 3, which is characterized in that between the sealing ring and the crackle stop zone
Distance be 1.8-2.2 microns.
8. semiconductor devices according to claim 1, which is characterized in that the first redistribution dielectric layer and/or described
Second redistribution dielectric layer has inclined side wall.
9. semiconductor devices according to claim 2, which is characterized in that be formed with opening in the passivation layer, it is described again
Distribution layer is electrically connected by the opening with the interconnection layer.
10. semiconductor devices according to claim 1, which is characterized in that the sealing ring be include more metal layers
Stepped construction.
11. semiconductor devices according to claim 3, which is characterized in that the crackle stop zone be include multiple layer metal
The stepped construction of layer.
12. a kind of electronic device, which is characterized in that including the semiconductor devices as described in one of claim 1-11.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810231077.8A CN110310938A (en) | 2018-03-20 | 2018-03-20 | A kind of semiconductor devices and electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810231077.8A CN110310938A (en) | 2018-03-20 | 2018-03-20 | A kind of semiconductor devices and electronic device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111883437A (en) * | 2020-07-03 | 2020-11-03 | 矽磐微电子(重庆)有限公司 | Semiconductor packaging method and semiconductor packaging structure |
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| CN102593076A (en) * | 2011-01-11 | 2012-07-18 | 台湾积体电路制造股份有限公司 | Semiconductor device |
| CN105448866A (en) * | 2014-08-20 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device structure and manufacturing method thereof |
| US9589915B2 (en) * | 2014-07-17 | 2017-03-07 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and manufacturing method thereof |
| CN106711140A (en) * | 2015-11-13 | 2017-05-24 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of forming the same |
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| CN1381070A (en) * | 2000-03-23 | 2002-11-20 | 精工爱普生株式会社 | Semiconductor device, method of manufacture thereof, circuit board and electronic device |
| CN102593076A (en) * | 2011-01-11 | 2012-07-18 | 台湾积体电路制造股份有限公司 | Semiconductor device |
| US9589915B2 (en) * | 2014-07-17 | 2017-03-07 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and manufacturing method thereof |
| CN105448866A (en) * | 2014-08-20 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device structure and manufacturing method thereof |
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| CN111883437A (en) * | 2020-07-03 | 2020-11-03 | 矽磐微电子(重庆)有限公司 | Semiconductor packaging method and semiconductor packaging structure |
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