CN208806243U - Moat structure in chip - Google Patents

Abstract

The utility model provides moat structure in a kind of chip; the structure includes substrate, diffusion barrier layer, dielectric layer, metal interconnection structure, passivation protection layer, moat groove structure and sealer; wherein; moat groove structure is formed in the grooved ring that chip perimeter region includes at least two discrete settings; grooved ring is extended to down in dielectric layer but not through the diffusion barrier layer; sealer successively includes conforma layer and filled layer from bottom to top; conforma layer is also formed into side wall and the bottom of grooved ring, and filled layer also inserts grooved ring.The utility model arranges grooved ring in chip perimeter region, grooved ring is around chip body region, and conforma layer and filled layer are filled in grooved ring, it can effectively absorb or baffle wafers cut stress, it is transmitted to block wafer to cut stress toward chip body region, and the use of metal material is reduced, while increasing the stability of structure.

Description

Moat structure in chip

Technical field

The utility model belongs to semiconductor integrated circuit field, is related to moat structure in a kind of chip.

Background technique

In manufacture of semiconductor, the wafer for being formed with integrated circuit is usually cut into chip (chip) one by one, so The semiconductor package that these chip manufacturings are different at function afterwards.As shown in Figure 1, it is shown as the partial top view of wafer, Include multiple chips 101 in wafer, is separated by between adjacent two chip with Cutting Road 102 (Scribe line or scribe line). Each chip includes the device architecture being formed on the substrate by techniques such as deposition, photoetching, etching, doping and heat treatments, interconnection Structure and weld pad etc..Later, wafer is cut into multiple independent chips along Cutting Road.

When being cut to wafer, mechanical stress can be applied on the wafer, therefore, be easy made of cutting Slight crack is caused in chip.In the prior art, damage of the semiconductor chip by cutting technique in order to prevent, can be in each chip Device region and Cutting Road between formed surround chip protection ring 103 (Guard Ring).

As shown in Fig. 2, being shown as the A-A ' of Fig. 1 to sectional view, it is seen then that protection ring in the prior art is from bottom to top successively Including contact bolt 104, the first becket 105, the first plug 106, the second becket 107, the second plug 108, third becket 109 and passivation protection layer 110, wherein surrounded around contact bolt and the first becket by dielectric layer 111, the first plug, the second gold medal Belong to and being surrounded around ring, the second plug and third becket by dielectric layer 112, has one between dielectric layer 111 and dielectric layer 112 SiCN diffusion barrier layer 113, passivation protection layer successively include that oxide skin(coating) 1101, silicon nitride layer 1102 and polyamides are sub- from bottom to top W can be used in the material of amine layer 1103, contact bolt and the first plug, and Cu, the second becket, can be used in the material of the first becket Aluminium can be used in the material of two plugs and third becket.In order to reinforce the connection between metal and medium, each contact bolt, plug and Also there is adhesion coating 114 between second, third becket and dielectric layer.

Due to, in existing chip protection ring structure include more metal layers, manufacture craft is complex, cost also compared with Therefore how height provides a kind of new safeguard structure, to reduce process complexity, and reduces cost, while providing good core Piece protection effect becomes those skilled in the art's important technological problems urgently to be resolved.

Utility model content

In view of the foregoing deficiencies of prior art, the purpose of this utility model is to provide moat knots in a kind of chip Structure, for solving the problems, such as chip protection ring structure fabrication processes complexity, higher cost in the prior art.

In order to achieve the above objects and other related objects, the utility model provides moat structure in a kind of chip, comprising:

Substrate, definition has chip body region and the chip perimeter area around the chip body region on the substrate Domain；

Diffusion barrier layer is located at the substrate surface, is embedded with moat ring structure in the substrate, is located at the chip In neighboring area and cover under the diffusion barrier layer；

Dielectric layer is located at the diffusion barrier layer surface；

Metal interconnection structure is located in the dielectric layer, and the conductive metal layer of the metal interconnection structure is located at the core In piece body region；

Passivation protection layer is located at the dielectric layer surface；

Moat groove structure, is formed in the chip perimeter region and in alignment with the moat ring structure, described Moat groove structure includes the grooved ring of at least two discrete settings, and the grooved ring is extended to down in the dielectric layer, but not Through the diffusion barrier layer；

Sealer is located in the passivation protection layer, and the sealer successively includes conforma layer from bottom to top And filled layer, the conforma layer are also formed into side wall and the bottom of the grooved ring, the filled layer also inserts the grooved ring.

Optionally, the filled layer includes polymeric layer, and the conforma layer includes carbon-coating.

Optionally, the passivation protection layer successively includes silicon dioxide layer and silicon nitride layer from bottom to top.

Optionally, the filled layer is located at the part in the grooved ring with air gap.

Optionally, the passivation protection layer includes silicon dioxide layer, and the conforma layer includes silicon nitride layer, the filled layer Including silicon dioxide layer, moat structure further includes polymeric layer in the chip, is located on the filled layer.

Optionally, the moat ring structure includes the first becket of at least two discrete settings and multiple first conductive Plug, the diffusion barrier layer cover first becket, and the conductive plunger is connected to below the becket, the slot Ring is longitudinally aligned with first becket.

Optionally, there is upper layer diffusion barrier layer, the upper layer diffusion barrier layer is located at the metal in the dielectric layer The top of interconnection structure wherein one layer of conductive metal layer, to prevent the diffusion of underlying conductive metal layer, the metal interconnection structure It further includes and is aligned in the second becket of at least two discrete settings and multiple second metal plugs on the moat ring structure In the dielectric layer in the chip perimeter region, second becket is located at below the upper layer diffusion barrier layer, institute The second metal plug is stated to be connected to below second becket.

Optionally, the bottom surface of the grooved ring is located relatively at non-including the dielectric layer on the top surface of the diffusion barrier layer Through surface.

Optionally, the grooved ring runs through the dielectric layer, and the bottom surface of the grooved ring includes the dew of the diffusion barrier layer Surface out.

As described above, moat structure in the chip of the utility model, has the advantages that the core of the utility model Moat structure arranges grooved ring in chip perimeter region in piece, and grooved ring has conforma layer around chip body region in grooved ring And polymeric layer can be used in filled layer, filled layer, and which is flexible material, wafer cutting stress can be effectively absorbed, It is transmitted to block wafer to cut stress toward chip body region, prevents the generation of slight crack in chip.Can also have in filled layer Air gap, using the mechanical stress in air gap baffle wafers cutting process, so that wafer be blocked to cut stress toward chip body region Transmitting, can be effectively prevented the generation of slight crack in chip.Due in grooved ring use nonmetallic conforma layer and filled layer instead of Conventional multiple layer metal filling, it is possible to reduce the use of metal material can not only reduce process complexity, promote yield, also Production cost is advantageously reduced, meanwhile, conforma layer and filled layer are filled in grooved ring the stability that can also increase structure.

Detailed description of the invention

Fig. 1 is shown as the partial top view of wafer in the prior art.

Fig. 2 is shown as the A-A ' of Fig. 1 to sectional view.

Fig. 3 is shown as the partial top view of the utility model wafer in embodiment one.

Fig. 4 is shown as the B-B ' of Fig. 3 to sectional view.

Fig. 5-Figure 15 is shown as the section that each step of manufacturing method of moat structure in chip in embodiment one is presented Structural schematic diagram.

Figure 16 is shown as the sectional structure chart that moat structure is presented in embodiment two in the chip of the utility model.

Figure 17 is shown as the sectional structure chart that moat structure is presented in embodiment three in the chip of the utility model.

Figure 18 is shown as the sectional structure chart that moat structure is presented in example IV in the chip of the utility model.

Figure 19 is shown as the sectional structure chart that moat structure is presented in embodiment five in the chip of the utility model.

Figure 20 is shown as the sectional structure chart that moat structure is presented in embodiment six in the chip of the utility model.

Figure 21 is shown as the partial top view of the utility model wafer in embodiment seven.

Figure 22 is shown as the B-B ' of Fig. 3 to sectional view.

Figure 23-Figure 34 is shown as the section that each step of manufacturing method of moat structure in chip in embodiment seven is presented Structural schematic diagram.

Figure 35 is shown as the sectional structure chart that moat structure is presented in embodiment eight in the chip of the utility model.

Figure 36 is shown as the sectional structure chart that moat structure is presented in embodiment nine in the chip of the utility model.

Figure 37 is shown as the sectional structure chart that moat structure is presented in embodiment ten in the chip of the utility model.

Figure 38 is shown as the cross-section structure that moat structure is presented in embodiment 11 in the chip of the utility model Figure.

Figure 39 is shown as the cross-section structure that moat structure is presented in embodiment 12 in the chip of the utility model Figure.

Component label instructions

101 chips

102 Cutting Roads

103 protection rings

104 contact bolts

105 first beckets

106 first plugs

107 second beckets

108 second plugs

109 third beckets

110 passivation protection layers

1101 oxide skin(coating)s

1102 silicon nitride layers

1103 polyimide layers

111,112 dielectric layers

113 SiCN diffusion barrier layers

114 adhesion coatings

200 Cutting Roads

I chip body region

II chip perimeter region

201 substrates

202 bottom conductive metal layers

203 bottom conductive plungers

204 adhesion coatings

205 first beckets

206 first conductive plungers

207 adhesion coatings

208 diffusion barrier layers

209 dielectric layers

The first dielectric layer of 209a

The second dielectric layer of 209b

210 metal interconnection structures

210a, 210b conductive metal layer

210c conductive column

210c ' conductive column through-hole

210d bottom conductive column

211 bond pads

212 passivation protection layers

212a oxide skin(coating)

212b silicon nitride layer

213 filled layers

214 grooved rings

215 apertures

216 upper layer diffusion barrier layers

217 second beckets

218 second metal plugs

219 photoresist layers

The first photoresist layer of 219a opening

The second photoresist layer of 219b opening

220 conforma layers

The width of W grooved ring

The height of H grooved ring

The spacing of D grooved ring

300 Cutting Roads

301 substrates

302 bottom conductive metal layers

303 bottom conductive plungers

304 adhesion coatings

305 first beckets

306 first conductive plungers

307 adhesion coatings

308 diffusion barrier layers

309 dielectric layers

The first dielectric layer of 309a

The second dielectric layer of 309b

310 metal interconnection structures

310a, 310b conductive metal layer

310c conductive column

310c ' conductive column through-hole

310d bottom conductive column

311 bond pads

312 passivation protection layers

313 filled layers

314 grooved rings

315 apertures

316 upper layer diffusion barrier layers

317 second beckets

318 second metal plugs

319 photoresist layers

319 ' photoresist layers opening

320 conforma layers

321 air gaps

322 polymeric layers

Specific embodiment

Illustrate the embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this theory Content disclosed by bright book understands other advantages and effect of the utility model easily.The utility model can also be by addition Different specific embodiments are embodied or practiced, and the various details in this specification can also be based on different viewpoints and answer With carrying out various modifications or alterations under the spirit without departing from the utility model.

Fig. 3 is please referred to Figure 20.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way The basic conception of utility model is only shown with related component in the utility model rather than when according to actual implementation in schema then Component count, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind Become, and its assembly layout kenel may also be increasingly complex.

Embodiment one

In the present embodiment, moat structure fabrication is on a wafer in chip.Referring to Fig. 3, being shown as the wafer Partial top view is provided with moat structure in multiple chips in the wafer, passes through between moat structure in adjacent chips Cutting Road 200 is spaced.

As shown in figure 3, the definition of moat structure has chip body region I and around the chip body area in the chip The chip perimeter region II of domain I, the chip perimeter region II are equipped with moat groove structure, the moat groove structure packet The grooved ring 214 of at least two discrete settings is included, the grooved ring 214 is around the chip body region I, to block wafer to cut Stress is transmitted toward the chip body region I.In the present embodiment, using straight-flanked ring, (Fig. 3 illustrates only rectangle to the grooved ring 214 Two sides of ring), and the quantity of the grooved ring 214 is 3, however in other embodiments, the shape of the grooved ring 214 can also To be adjusted according to the actual profile and device layout of chip, the quantity of the grooved ring 214, which also can according to need, to be adjusted It is whole, for example, 2~10, the protection scope of the utility model should not be excessively limited herein.

Referring to Fig. 4, being shown as the B-B ' of Fig. 3 to sectional view, it is seen that in addition to the moat groove structure, the chip Interior moat structure further includes substrate 201, diffusion barrier layer 208, dielectric layer 209, metal interconnection structure 210, bond pad 211, passivation protection layer 212, aperture 215 and sealer (being made of conforma layer 220 and filled layer 213), wherein the expansion It dissipates barrier layer 208 and is located at 201 surface of substrate, be embedded with moat ring structure, the moat ring knot in the substrate 201 Structure is located in the chip perimeter region II and covers under the diffusion barrier layer 208, and the moat ring structure includes The first becket 205 and multiple first conductive plungers 206 of at least two discrete settings, first conductive plunger 206 and institute The interface for stating substrate 201 has adhesion coating 207, and the diffusion barrier layer 208 covers first becket 205, the conduction Plug 206 is connected to 205 lower section of the first becket.In the present embodiment, the moat groove structure is in alignment with the shield Fosse ring structure, and the grooved ring 214 is longitudinally aligned with first becket 205.The dielectric layer 209 is located at the diffusion 208 surface of barrier layer, the metal interconnection structure 210 and the bond pad 211 are located in the dielectric layer 209, the gold The conductive metal layer and the bond pad 211 for belonging to interconnection structure 210 are located in the chip body region I, in the present embodiment, The bond pad 211 is used for packaging and testing close to the chip body region edge I.The passivation protection layer 212 is located at institute 209 surface of electric layer is given an account of, the grooved ring 214 is open from 212 top surface of passivation protection layer, and extends to the dielectric layer down In 209, but do not run through the diffusion barrier layer 208, the conforma layer 220 be coated on side wall and the bottom surface of the grooved ring 214 with And the top surface of the passivation protection layer 212, the filled layer 213 is coated on 220 surface of conforma layer, and is filled into the slot The remaining space of ring.The aperture 215 is open from 212 top surface of passivation protection layer, and extends to the bond pad down 211 surface, to expose the bond pad 211.In the present embodiment, the conforma layer 220 is coated on the aperture simultaneously 215 side wall and bottom surface, and the filled layer 213 is filled into the remaining space of the aperture 215.

Specifically, the width W range of the grooved ring is 1~3 μm, the height H range of the grooved ring is 2~10 μm, adjacent The space D range of the grooved ring is 4~90 μm.In the present embodiment, the bottom surface of the grooved ring 214 is located relatively at the diffusion barrier It include the non-through surface of the dielectric layer 209 on the top surface of layer 208.

Specifically, the metal interconnection structure 210 includes at least two conductive metal layer.In the present embodiment, the metal Interconnection structure 210 includes two conductive metal layer 210a, 210b, passes through conductive column between conductive metal layer described in adjacent two layers 210c connection, and be located at below the conductive metal layer 210b of bottom and be connected with bottom conductive column 210d.The conductive metal The material of layer 210a, 210b and conductive column 210c includes but is not limited to tungsten, copper, aluminium etc..

It is located at together specifically, being more formed in the substrate of the chip body region I with the moat ring structure The bottom conductive metal layer 202 and multiple bottom conductive plungers 203 of one layer of structure, the bottom conductive plunger 203 are connected to the bottom and lead Below metal layer 202, diffusion barrier layer 208 described in 210 break-through of metal interconnection structure, and it is connected to the bottom conductive gold Belong to 202 top of layer.The material of the bottom conductive metal layer 202 and the bottom conductive plunger 203 includes but is not limited to tungsten, copper, aluminium Deng.

Specifically, the passivation protection layer 212 successively includes oxide skin(coating) 212a and silicon nitride layer 212b from bottom to top.Institute The material for stating oxide skin(coating) 212a includes but is not limited to silica, and the material of the conforma layer 220 includes but is not limited to carbon, institute Stating filled layer 213 is polymeric layer, and material includes but is not limited to polyimides, and the material of the diffusion barrier layer 208 includes But it is not limited to carbonitride of silicium.

As an example, manufacture moat structure in the chip the following steps are included:

Fig. 5 and Fig. 6 is please referred to, step S201 is executed: a substrate 201 is provided, the substrate surface has a diffusion barrier Layer 208, and definition has the chip body region I and chip perimeter region II around the chip body region on the substrate, It is embedded with moat ring structure in the substrate, be located in the chip perimeter region II and covers in the diffusion barrier layer Under 208.The moat ring structure includes the first becket 205 and multiple first conductive plungers of at least two discrete settings 206, the interface of first conductive plunger 206 and the substrate 201 has adhesion coating 207, and the diffusion barrier layer 208 covers First becket 205, the conductive plunger 206 are connected to 205 lower section of the first becket.It is described in the present embodiment Moat groove structure is in alignment with the moat ring structure, and the grooved ring 214 is longitudinally aligned with first becket 205.The bottom that structure is located on the same floor with the moat ring structure is more formed in the substrate of the chip body region I Conductive metal layer 202 and multiple bottom conductive plungers 203, the bottom conductive plunger 203 are connected under the bottom conductive metal layer 202 Side is as an example, as shown in figure 5, be initially formed multiple bottom conductive plungers 203 and multiple first conductive plungers 206 in the substrate In 201, the bottom conductive plunger 203 is located in the substrate of the chip body region I, first conductive plunger 206 In the substrate of the chip perimeter region II.As shown in fig. 6, then forming bottom conductive metal layer 202 in the bottom On conductive plunger 203, formed the first becket 205 on first conductive plunger 206, re-form diffusion barrier layer 208 in On the substrate.

Specifically, forming conductive plunger groove in the substrate by photoetching process and etching technics first, then sink In product conductive plunger material (such as W) Yu Suoshu conductive plunger groove, and institute is removed by chemical attack or chemical mechanical grinding State conductive plunger material extra outside conductive plunger groove.In order to enhance the conductive plunger 203 and first conductive plunger Combination between 206 and the substrate 201, and the diffusion of conductive plunger material is reduced, it can first sink before depositing conductive plunger Bottom surface and side wall of one adhesion coating 204,207 of product in the conductive plunger groove.The diffusion barrier layer 208 is described for preventing The diffusion of bottom conductive metal layer 202,205 material of the first becket.The material of the diffusion barrier layer 208 includes but unlimited In carbonitride of silicium.

It please refers to Fig. 7 to Figure 10, executes step S202: forming dielectric layer 209 on the diffusion barrier layer, and form gold Belong to interconnection structure 210 and bond pad 211 in the dielectric layer 209, the conductive metal layer of the metal interconnection structure 210 and The bond pad 211 is located at the chip body region I, and the bond pad 211 is close to the chip body region side I Edge.

Specifically, the metal interconnection structure 210 includes at least two conductive metal layer.In the present embodiment, the metal Interconnection structure 210 includes two conductive metal layer 210a, 210b, passes through conductive column between conductive metal layer described in adjacent two layers 210c connection, and be located at below the conductive metal layer 210b of bottom and be connected with bottom conductive column 210d.The conductive metal The material of layer 210a, 210b and conductive column 210c includes but is not limited to tungsten, copper, aluminium etc..

As an example, as shown in fig. 7, be initially formed the first dielectric layer 209a on the diffusion barrier layer 208, and form bottom Layer conductive column 210d is in the first dielectric layer 209a of the chip body region I, the material of the bottom conductive column 210d Tungsten can be selected in matter, and Fig. 7 is shown as the structure that the bottom conductive column 210d is presented after chemically mechanical polishing.Such as Fig. 8 institute Show, then forms conductive metal layer 210b on the bottom conductive column 210d, Fig. 8 is shown as conductive metal layer 210b by carving The structure presented after erosion is graphical.As shown in figure 9, being subsequently formed the second dielectric layer 209b in the first dielectric layer 209a On, and formed in conductive column through-hole 210c ' the second dielectric layer of Yu Suoshu 209b.As shown in Figure 10, re-form conductive column 210c and For conductive metal layer 210a in the second dielectric layer 209b, Figure 10 is shown as conductive metal layer 210a after etched features The structure presented.Silica or low k dielectric can be selected in the material of the first dielectric layer 209a.Second dielectric layer Silica or low k dielectric can be selected in the material of 209b.Please refer to Figure 11, execute step 203: formed passivation protection layer 212 in On the dielectric layer 209.

Specifically, being sequentially depositing oxide skin(coating) 212a, silicon nitride layer 212b from bottom to top as the passivation protection layer Silica can be selected in the material of 212, the oxide skin(coating) 212a.

Figure 12 is please referred to, step 204 is executed: forming photoresist layer 219 in the passivation protection layer 212.

It is also further using photoetching processes such as exposure, developments that the photoresist layer 219 is graphical in the present embodiment, it obtains Be open 219b to be open 219a and the second photoresist layer of the first photoresist layer, wherein the first photoresist layer opening 219a with The position of the bond pad 211 is corresponding, and the second photoresist layer opening 219b is ring-type, is located at the chip perimeter area Domain II.The first photoresist layer opening 219a and the second photoresist layer opening 219b can pass through chemical wet etching or laser opening etc. Method is formed.

Figure 13 is please referred to, step S205 is executed: being that exposure mask etches down with the patterned photoresist layer 219, is formed Aperture 215 in the chip body region I with expose the bond pad 211, and synchronize to be formed moat groove structure in The chip perimeter region II is to block wafer cutting stress to transmit toward the chip body region I, the moat groove knot Structure is in alignment with the moat ring structure and the grooved ring 214 including at least two discrete settings, wherein the grooved ring 214 from 212 top surface of the passivation protection layer opening, and extended in the dielectric layer 209 down, but do not run through the diffusion barrier layer 208, the aperture 215 is open from 212 top surface of passivation protection layer, and extends to the surface of the bond pad 211 down.

In the present embodiment, it includes institute on the top surface of the diffusion barrier layer 208 that the bottom surface of the grooved ring 214, which is relatively located at, Give an account of the non-through surface of electric layer 209a.

Figure 14 is please referred to, step S206 is executed: forming side wall and bottom surface and institute of the conforma layer 220 in the grooved ring 214 State the top surface of passivation protection layer 212.

In the present embodiment, the material of the conforma layer 220 preferably uses carbon (Carbon), the reason is that, described in the formation When conforma layer 220, the conforma layer 220 can also be deposited on bond pad surface simultaneously, according to conventional conforma layer material, then Other one of etch process is needed to etch conforma layer again to open bond pad, and according to carbon materials matter, due to carbon materials The more crisp attribute of matter, it is easy to be lifted or scratch, there is no need to use other one of etch process, advantageously reduce and be produced into This.

As shown in figure 15, it executes step S207: forming filled layer 13 in the conformal layer surface, the filled layer 213 is filled out It is charged into the remaining space of the grooved ring 214.In the present embodiment, it is remaining that the filled layer 213 is filled into the aperture 215 simultaneously Space.

Specifically, the material of the filled layer 213 includes but is not limited to the flexible materials such as polyimides, can effectively absorb Wafer cuts stress, transmits so that wafer be blocked to cut stress toward chip body region, prevents the generation of slight crack in chip.

So far, moat structure in chip has been prepared.It should be pointed out that in other embodiments, the metal Interconnection structure 210 can also have more layers metal, and its manufacturing process is also not necessarily limited to above-mentioned process flow, such as can basis It needs to select single Damascus technics or dual damascene process, should not excessively limit the protection scope of the utility model herein.

Moat structure arranges grooved ring in chip perimeter region in the chip of the utility model, and grooved ring is around chip body area Domain, and polymeric layer is filled in grooved ring, which is flexible material, wafer cutting stress can be effectively absorbed, thus It blocks wafer to cut stress to transmit toward chip body region, prevents the generation of slight crack in chip.Due to using polymer in grooved ring Layer is filled instead of conventional multiple layer metal, it is possible to reduce the use of metal material can not only reduce process complexity, be promoted Yield also helps reduction production cost.Meanwhile polymeric layer is filled in grooved ring the stability that can also increase structure.

Embodiment two

The present embodiment and embodiment one use essentially identical technical solution, the difference is that, described in embodiment one Grooved ring 214 is open from 212 top surface of passivation protection layer, and is extended in the dielectric layer 209 down, and the grooved ring 214 Bottom surface be located relatively on the top surface of the diffusion barrier layer 208 include the dielectric layer 209a non-through surface.And this reality It applies in example, the grooved ring 214 runs through the dielectric layer 209, and the bottom surface of the grooved ring 214 includes the diffusion barrier layer 208 Exposing surface, as shown in figure 16.

Embodiment three

The present embodiment and embodiment one use essentially identical technical solution, the difference is that, it is described in the present embodiment There is upper layer diffusion barrier layer 216, the upper layer diffusion barrier layer 216 is located therein one layer of conductive gold in dielectric layer 209 Belong to the top of layer, to prevent the diffusion of this layer of conductive metal layer.Figure 17 is please referred to, core described in the present embodiment is shown as The schematic diagram of the section structure that moat structure is presented in piece, as an example, the upper layer diffusion barrier layer 216 is located at described lead Above metal layer 210b, and the bottom surface of the grooved ring 214 is located relatively on the top surface of the upper layer diffusion barrier layer 216 and includes The non-through surface of the dielectric layer 209b.The material of the upper layer diffusion barrier layer 216 includes but is not limited to carbonitride of silicium.

The present embodiment is suitable for the situation that the conductive metal layer 210b selects Cu or other easy diffusion materials.

Example IV

The present embodiment and embodiment three use essentially identical technical solution, the difference is that, described in embodiment three Grooved ring 214 is open from 212 top surface of passivation protection layer, and is extended in the dielectric layer 209 down, and the grooved ring 214 Bottom surface be located relatively on the top surface of the upper layer diffusion barrier layer 216 include the dielectric layer 209b non-through surface.And In the present embodiment, the bottom surface of the grooved ring 214 includes the exposing surface of the upper layer diffusion barrier layer 216, as shown in figure 18.

Embodiment five

The present embodiment and embodiment three use essentially identical technical solution, the difference is that, described in the present embodiment Metal interconnection structure 210 further include the second becket 217 for being aligned at least two discrete settings in the moat structure and In the dielectric layer 209 in the chip perimeter region, second becket 217 is located at multiple second metal plugs 218 216 lower section of upper layer diffusion barrier layer, second metal plug 218 are connected to 217 lower section of the second becket, such as scheme Shown in 19.

In the present embodiment, the chip perimeter region II has grooved ring 214 and becket 217 simultaneously, has taken into account the two Advantage, and reduce the use of metal material, process complexity can be not only reduced, yield is promoted, also helps reduction production Cost.

Embodiment six

The present embodiment and embodiment five use essentially identical technical solution, the difference is that, described in embodiment five Grooved ring 214 is open from 212 top surface of passivation protection layer, and is extended in the dielectric layer 209 down, and the grooved ring 214 Bottom surface be located relatively on the top surface of the upper layer diffusion barrier layer 216 include the dielectric layer 209b non-through surface.And In the present embodiment, the bottom surface of the grooved ring 214 includes the exposing surface of the upper layer diffusion barrier layer 216, as shown in figure 20.

Embodiment seven

In the present embodiment, moat structure fabrication is on a wafer in chip.Figure 21 is please referred to, the wafer is shown as Partial top view is provided with moat structure in multiple chips in the wafer, passes through between moat structure in adjacent chips Cutting Road 300 is spaced.

As shown in figure 21, the definition of moat structure has chip body region I and around the chip body in the chip The chip perimeter region II of region I, the chip perimeter region II are equipped with moat groove structure, the moat groove structure Grooved ring 314 including at least two discrete settings, the grooved ring 314 is around the chip body region I, to block wafer to cut Stress is cut to transmit toward the chip body region I.In the present embodiment, using straight-flanked ring, (Figure 21 illustrates only square to the grooved ring 314 Two sides of shape ring), and the quantity of the grooved ring 314 is 3, however in other embodiments, the shape of the grooved ring 314 It can be adjusted according to the actual profile and device layout of chip, the quantity of the grooved ring 314 also can according to need progress Adjustment, should not excessively limit the protection scope of the utility model herein by for example, 2~10.

Figure 22 is please referred to, is shown as the B-B ' of Figure 21 to sectional view, it is seen that in addition to the moat groove structure, the core Moat structure further includes substrate 301, diffusion barrier layer 308, dielectric layer 309, metal interconnection structure 310, bond pad in piece 311, passivation protection layer 212, aperture 315, sealer (being made of 320 grades of filled layers 313 of conforma layer), air gap 321 and poly- Close nitride layer 322, wherein the diffusion barrier layer 308 is located at 301 surface of substrate, is embedded with moat in the substrate 301 Ring structure, the moat ring structure are located in the chip perimeter region II and cover under the diffusion barrier layer 308, The moat ring structure includes the first becket 305 and multiple first conductive plungers 306 of at least two discrete settings, described The interface of first conductive plunger 306 and the substrate 301 has adhesion coating 307, and the diffusion barrier layer 308 covers described first Becket 305, the conductive plunger 306 are connected to 305 lower section of the first becket.In the present embodiment, the moat is recessed Slot structure is in alignment with the moat ring structure, and the grooved ring 314 is longitudinally aligned with first becket 305.It is given an account of Electric layer 309 is located at 308 surface of diffusion barrier layer, and the metal interconnection structure 310 and the bond pad 311 are located at described In dielectric layer 309, the conductive metal layer and the bond pad 311 of the metal interconnection structure 310 are located at the chip body In the I of region, in the present embodiment, the bond pad 311 is used for packaging and testing close to the chip body region edge I.It is described Passivation protection layer 312 is located at 309 surface of dielectric layer, and the grooved ring 314 is open from 312 top surface of passivation protection layer, and It is extended in the dielectric layer 309 down, but does not run through the diffusion barrier layer 308, the conforma layer 320 is coated on the slot The side wall of ring 314 and bottom surface and the top surface of the passivation protection layer 312, the filled layer 313 are coated on the conforma layer 320 Surface, and the remaining space of the grooved ring 314 is filled into close the opening of the grooved ring 314, and the filled layer 313 is located at Part in the grooved ring 314 has air gap 321, and the polymeric layer 322 is located on the filled layer.315 shape of aperture Chip body region described in Cheng Yu is to expose the bond pad 311, and in the present embodiment, the aperture 315 is from the polymerization 322 top surface of nitride layer opening, and the surface of the bond pad 311 is extended to down, to expose the bond pad 311.

Specifically, the width W range of the grooved ring is 1~3 μm, the height H range of the grooved ring is 2~10 μm, adjacent The space D range of the grooved ring is 4~90 μm.In the present embodiment, the bottom surface of the grooved ring 314 is located relatively at the diffusion barrier It include the non-through surface of the dielectric layer 309 on the top surface of layer 308.

Specifically, the metal interconnection structure 310 includes at least two conductive metal layer.In the present embodiment, the metal Interconnection structure 310 includes two conductive metal layer 310a, 310b, passes through conductive column between conductive metal layer described in adjacent two layers 310c connection, and be located at below the conductive metal layer 310b of bottom and be connected with bottom conductive column 310d.The conductive metal The material of layer 310a, 310b and conductive column 310c includes but is not limited to tungsten, copper, aluminium etc..

It is located at together specifically, being more formed in the substrate of the chip body region I with the moat ring structure The bottom conductive metal layer 302 and multiple bottom conductive plungers 303 of one layer of structure, the bottom conductive plunger 303 are connected to the bottom and lead Below metal layer 302, diffusion barrier layer 308 described in 310 break-through of metal interconnection structure, and it is connected to the bottom conductive gold Belong to 302 top of layer.The material of the bottom conductive metal layer 302 and the bottom conductive plunger 303 includes but is not limited to tungsten, copper, aluminium Deng.

Specifically, the passivation protection layer 312 and the material of filled layer 313 include but is not limited to oxide, the oxidation Object can be silica, and the material of the conforma layer 320 includes but is not limited to silicon nitride.The material packet of the polymeric layer 322 Polyimides is included but is not limited to, the material of the diffusion barrier layer 308 includes but is not limited to carbonitride of silicium.

As an example, manufacture moat structure in the chip the following steps are included:

Figure 23 and Figure 24 is please referred to, step S301 is executed: a substrate 301 is provided, the substrate surface has a diffusion resistance Barrier 308, and definition has chip body region I and the chip perimeter region around the chip body region on the substrate II is embedded with moat ring structure in the substrate, is located in the chip perimeter region II and covers in the diffusion barrier Under layer 308.The moat ring structure includes that the first becket 305 of at least two discrete settings and multiple first conductions are inserted The interface of plug 306, first conductive plunger 306 and the substrate 301 has adhesion coating 307, and the diffusion barrier layer 308 covers First becket 305 is covered, the conductive plunger 306 is connected to 305 lower section of the first becket.In the present embodiment, institute Moat groove structure is stated in alignment with the moat ring structure, and the grooved ring 314 is longitudinally aligned with first becket 305.The bottom that structure is located on the same floor with the moat ring structure is more formed in the substrate of the chip body region I Conductive metal layer 302 and multiple bottom conductive plungers 303, the bottom conductive plunger 303 are connected under the bottom conductive metal layer 302 Side is as an example, as shown in figure 23, be initially formed multiple bottom conductive plungers 303 and multiple first conductive plungers 306 in the substrate In 301, the bottom conductive plunger 303 is located in the substrate of the chip body region I, first conductive plunger 306 In the substrate of the chip perimeter region II.As shown in figure 24, bottom conductive metal layer 302 is then formed in the bottom On conductive plunger 303, formed the first becket 305 on first conductive plunger 306, re-form diffusion barrier layer 308 in On the substrate.

Specifically, forming conductive plunger groove in the substrate by photoetching process and etching technics first, then sink In product conductive plunger material (such as W) Yu Suoshu conductive plunger groove, and institute is removed by chemical attack or chemical mechanical grinding State conductive plunger material extra outside conductive plunger groove.In order to enhance the conductive plunger 303 and first conductive plunger Combination between 306 and the substrate 301, and the diffusion of conductive plunger material is reduced, it can first sink before depositing conductive plunger Bottom surface and side wall of one adhesion coating 304,307 of product in the conductive plunger groove.The diffusion barrier layer 308 is described for preventing The diffusion of bottom conductive metal layer 302,305 material of the first becket.The material of the diffusion barrier layer 308 includes but unlimited In carbonitride of silicium.

It please refers to Figure 25 to Figure 28, executes step S302: forming dielectric layer 309 on the diffusion barrier layer, and formed Metal interconnection structure 310 and bond pad 311 are in the dielectric layer 309, the conductive metal layer of the metal interconnection structure 310 And the bond pad 311 is located at the chip body region I, the bond pad 311 is close to the chip body region side I Edge.

Specifically, the metal interconnection structure 310 includes at least two conductive metal layer.In the present embodiment, the metal Interconnection structure 310 includes two conductive metal layer 310a, 310b, passes through conductive column between conductive metal layer described in adjacent two layers 310c connection, and be located at below the conductive metal layer 310b of bottom and be connected with bottom conductive column 310d.The conductive metal The material of layer 310a, 310b and conductive column 310c includes but is not limited to tungsten, copper, aluminium etc..

As an example, as shown in figure 25, being initially formed the first dielectric layer 309a on the diffusion barrier layer 308, and formed Bottom conductive column 310d in the first dielectric layer 309a of the chip body region I, the bottom conductive column 310d's Tungsten can be selected in material, and Figure 25 is shown as the structure that the bottom conductive column 310d is presented after chemically mechanical polishing.Such as figure Shown in 26, conductive metal layer 310b is then formed on the bottom conductive column 310d, Figure 26 is shown as conductive metal layer 310b The structure presented after etched features.As shown in figure 27, the second dielectric layer 309b is subsequently formed in first dielectric On layer 309a, and formed in conductive column through-hole 310c ' the second dielectric layer of Yu Suoshu 309b.As shown in figure 28, conductive column is re-formed For 310c and conductive metal layer 310a in the second dielectric layer 309b, Figure 28 is shown as conductive metal layer 310a through over etching figure The structure presented after shape.Silica or low k dielectric can be selected in the material of the first dielectric layer 309a.Described second is situated between Silica or low k dielectric can be selected in the material of electric layer 309b.

Figure 29 is please referred to, step 303 is executed: forming passivation protection layer 312 on the dielectric layer 309.In the present embodiment, The material selection oxide of the passivation protection layer 312, such as silica.

Figure 30 is please referred to, step 304 is executed: forming photoresist layer 319 in the passivation protection layer 312.

It is also further using photoetching processes such as exposure, developments that the photoresist layer 319 is graphical in the present embodiment, it obtains To photoresist layer opening 319 ', the photoresist layer opening 319 ' is ring-type, is located at the chip perimeter region II.The photoetching Glue-line opening ' it can be formed by the methods of chemical wet etching or laser opening.

Figure 31 is please referred to, step S305 is executed: being that exposure mask etches down with the patterned photoresist layer 319, is formed Moat groove structure is transmitted with blocking wafer to cut stress toward the chip body region I in the chip perimeter region II, The moat groove structure in alignment with the moat ring structure and the grooved ring 314 including at least two discrete settings, In, the grooved ring 314 is open from 312 top surface of passivation protection layer, and is extended in the dielectric layer 309 down, but do not pass through Wear the diffusion barrier layer 308.

In the present embodiment, it includes institute on the top surface of the diffusion barrier layer 308 that the bottom surface of the grooved ring 314, which is relatively located at, Give an account of the non-through surface of electric layer 309a.

In the present embodiment, during this step etches passivation protection layer 312, not simultaneously in bond pad The test aperture for exposing the bond pad is formed above (bond pad), but is filled out in subsequent process flow in etching Bond pad is exposed while filling layer.

Figure 32 is please referred to, step S306 is executed: forming side wall and bottom surface and institute of the conforma layer 320 in the grooved ring 314 State the top surface of passivation protection layer 312.In the present embodiment, the material selection silicon nitride of the conforma layer 320.

Figure 33 is please referred to, step S307 is executed: forming filled layer 313 in 320 surface of conforma layer, the filled layer 313 are filled into the remaining space of the grooved ring 314 to close the opening of the grooved ring 314, and the filled layer 313 is positioned at described Part in grooved ring 314 has air gap 321.

In the present embodiment, the material selection oxide of the filled layer 313, such as silica.

Figure 34 is please referred to, step S308 is executed: forming polymeric layer 322 in the top surface of the filled layer 313.The polymerization The material of nitride layer 212 includes but is not limited to polyimides.

It further include etching the polymeric layer 313 and the filled layer to form aperture 315 in the core in the present embodiment The step of piece body region, the aperture 315 extends to the surface of the bond pad down, as instrument connection.

So far, moat structure in chip has been prepared.It should be pointed out that in other embodiments, the metal Interconnection structure 310 can also have more layers metal, and its manufacturing process is also not necessarily limited to above-mentioned process flow, such as can basis It needs to select single Damascus technics or dual damascene process, should not excessively limit the protection scope of the utility model herein.

In the chip of the utility model moat structure chip perimeter region arrange grooved ring with surround chip body region, And passivation protection layer twice is filled in grooved ring, while air gap is formed in grooved ring, using in air gap baffle wafers cutting process Mechanical stress, thus block wafer cut stress toward chip body region transmit, the production of slight crack in chip can be effectively prevented It is raw, due to using passivation protection layer to fill instead of conventional multiple layer metal in grooved ring, it is possible to reduce the use of metal material, no Process complexity can be only reduced, yield is promoted, also helps reduction production cost, meanwhile, passivation protection layer is filled in grooved ring The interior stability that can also increase structure.

Embodiment eight

The present embodiment and embodiment seven use essentially identical technical solution, the difference is that, described in embodiment seven Grooved ring 314 is open from 312 top surface of passivation protection layer, and is extended in the dielectric layer 309 down, and the grooved ring 314 Bottom surface be located relatively on the top surface of the diffusion barrier layer 308 include the dielectric layer 309a non-through surface.And this reality It applies in example, the grooved ring 314 runs through the dielectric layer 309, and the bottom surface of the grooved ring 314 includes the diffusion barrier layer 308 Exposing surface, as shown in figure 35.

Embodiment nine

The present embodiment and embodiment seven use essentially identical technical solution, the difference is that, it is described in the present embodiment There is upper layer diffusion barrier layer 316, the upper layer diffusion barrier layer 316 is located therein one layer of conductive gold in dielectric layer 309 Belong to the top of layer, to prevent the diffusion of this layer of conductive metal layer.Figure 36 is please referred to, core described in the present embodiment is shown as The schematic diagram of the section structure that moat structure is presented in piece, as an example, the upper layer diffusion barrier layer 316 is located at described lead Above metal layer 310b, and the bottom surface of the grooved ring 314 is located relatively on the top surface of the upper layer diffusion barrier layer 316 and includes The non-through surface of the dielectric layer 309b.The material of the upper layer diffusion barrier layer 316 includes but is not limited to carbonitride of silicium.

The present embodiment is suitable for the situation that the conductive metal layer 310b selects Cu or other easy diffusion materials.

Embodiment ten

The present embodiment and embodiment nine use essentially identical technical solution, the difference is that, described in embodiment nine Grooved ring 314 is open from 312 top surface of passivation protection layer, and is extended in the dielectric layer 309 down, and the grooved ring 314 Bottom surface be located relatively on the top surface of the upper layer diffusion barrier layer 316 include the dielectric layer 309b non-through surface.And In the present embodiment, the bottom surface of the grooved ring 314 includes the exposing surface of the upper layer diffusion barrier layer 316, as shown in figure 37.

Embodiment 11

The present embodiment and embodiment nine use essentially identical technical solution, the difference is that, described in the present embodiment Metal interconnection structure 310 further include the second becket 317 for being aligned at least two discrete settings in the moat structure and In the dielectric layer 309 in the chip perimeter region, second becket 317 is located at multiple second metal plugs 318 316 lower section of upper layer diffusion barrier layer, second metal plug 318 are connected to 317 lower section of the second becket, such as scheme Shown in 38.

In the present embodiment, the chip perimeter region II has grooved ring 314 and becket 317 simultaneously, has taken into account the two Advantage, and reduce the use of metal material, process complexity can be not only reduced, yield is promoted, also helps reduction production Cost.

Embodiment 12

The present embodiment and embodiment 11 use essentially identical technical solution, the difference is that, in embodiment 11 The grooved ring 314 is open from 312 top surface of passivation protection layer, and is extended in the dielectric layer 309 down, and the grooved ring 314 bottom surface is located relatively at the non-through surface on the top surface of the upper layer diffusion barrier layer 316 including the dielectric layer 309b. And in the present embodiment, the bottom surface of the grooved ring 314 includes the exposing surface of the upper layer diffusion barrier layer 316, as shown in figure 39.

In conclusion moat structure is surround in chip perimeter region arrangement grooved ring, grooved ring in the chip of the utility model Chip body region, and there is conforma layer and filled layer in grooved ring, polymeric layer can be used in filled layer, which is flexibility Material can effectively absorb wafer cutting stress, transmit so that wafer be blocked to cut stress toward chip body region, prevent chip The generation of interior slight crack.Can also have air gap in filled layer, using the mechanical stress in air gap baffle wafers cutting process, to hinder Disconnected wafer cuts stress and transmits toward chip body region, and the generation of slight crack in chip can be effectively prevented.Due to being used in grooved ring Nonmetallic conforma layer and filled layer is filled instead of conventional multiple layer metal, it is possible to reduce the use of metal material not only may be used To reduce process complexity, yield is promoted, reduction production cost is also helped, meanwhile, conforma layer and filled layer are filled in grooved ring The interior stability that can also increase structure.So the utility model effectively overcomes various shortcoming in the prior art and has height Spend value of industrial utilization.

The above embodiments are only illustrative of the principle and efficacy of the utility model, and not for limitation, this is practical new Type.Any person skilled in the art can all carry out above-described embodiment under the spirit and scope without prejudice to the utility model Modifications and changes.Therefore, such as those of ordinary skill in the art without departing from the revealed essence of the utility model All equivalent modifications or change completed under mind and technical idea, should be covered by the claim of the utility model.

Claims (9)

1. moat structure in a kind of chip characterized by comprising

Substrate, definition has chip body region and the chip perimeter region around the chip body region on the substrate；

Diffusion barrier layer is located at the substrate surface, is embedded with moat ring structure in the substrate, is located at the chip perimeter In region and cover under the diffusion barrier layer；

Dielectric layer is located at the diffusion barrier layer surface；

Metal interconnection structure is located in the dielectric layer, and the conductive metal layer of the metal interconnection structure is located at the chip master In body region；

Passivation protection layer is located at the dielectric layer surface；

Moat groove structure is formed in the chip perimeter region and in alignment with the moat ring structure, the shield city River groove structure includes the grooved ring of at least two discrete settings, and the grooved ring extends in the dielectric layer down, but do not run through The diffusion barrier layer；

Sealer is located in the passivation protection layer, and the sealer successively includes conforma layer and fills out from bottom to top Layer is filled, the conforma layer is also formed into side wall and the bottom of the grooved ring, and the filled layer also inserts the grooved ring.

2. moat structure in chip according to claim 1, it is characterised in that: the filled layer includes polymeric layer, The conforma layer includes carbon-coating.

3. moat structure in chip according to claim 1, it is characterised in that: the passivation protection layer from bottom to top according to Secondary includes silicon dioxide layer and silicon nitride layer.

4. moat structure in chip according to claim 1, it is characterised in that: the filled layer is located in the grooved ring Part have air gap.

5. moat structure in chip according to claim 1, it is characterised in that: the passivation protection layer includes titanium dioxide Silicon layer, the conforma layer include silicon nitride layer, and the filled layer includes silicon dioxide layer, and moat structure is more wrapped in the chip Polymeric layer is included, is located on the filled layer.

6. moat structure in chip according to claim 1, it is characterised in that: the moat ring structure includes at least The first becket and multiple first conductive plungers of two discrete settings, the diffusion barrier layer cover first becket, The conductive plunger is connected to below the becket, and the grooved ring is longitudinally aligned with first becket.

7. moat structure in chip according to claim 6, it is characterised in that: have upper layer diffusion in the dielectric layer Barrier layer, the upper layer diffusion barrier layer is located at the top of the metal interconnection structure wherein one layer of conductive metal layer, to prevent The diffusion of underlying conductive metal layer, the metal interconnection structure, which further includes, is aligned on the moat ring structure at least two points The second becket set and multiple second metal plugs are erected in the dielectric layer in the chip perimeter region, described second Becket is located at below the upper layer diffusion barrier layer, and second metal plug is connected to below second becket.

8. moat structure in chip described in any one according to claim 1~6, it is characterised in that: the bottom of the grooved ring Face is located relatively at the non-through surface on the top surface of the diffusion barrier layer including the dielectric layer.

9. moat structure in chip described in any one according to claim 1~6, it is characterised in that: the grooved ring runs through The dielectric layer, and the bottom surface of the grooved ring includes the exposing surface of the diffusion barrier layer.