CN208738220U - Moat structure in chip - Google Patents
Moat structure in chip Download PDFInfo
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- CN208738220U CN208738220U CN201821582800.9U CN201821582800U CN208738220U CN 208738220 U CN208738220 U CN 208738220U CN 201821582800 U CN201821582800 U CN 201821582800U CN 208738220 U CN208738220 U CN 208738220U
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Abstract
The utility model provides moat structure in a kind of chip; including substrate, diffusion barrier layer, dielectric layer, metal interconnection structure, bond pad and passivation protection layer; wherein, definition has chip body region and the chip perimeter region around chip body region on substrate；Moat structure has moat groove structure in chip, is formed in chip perimeter region and in alignment with moat ring structure, to block wafer cutting stress to transmit toward the chip body region；Moat groove structure includes the grooved ring of at least two discrete settings, wherein grooved ring extends in dielectric layer down, but does not run through diffusion barrier layer.The utility model arranges that grooved ring, grooved ring can effectively block wafer to cut stress and transmit toward chip body region, to prevent the generation of slight crack in chip around chip body region in chip perimeter region.The utility model reduces the use of metal material, can not only reduce process complexity, promotes yield, also helps reduction production cost.
Description
Technical field
The utility model belongs to semiconductor integrated circuit field, is related to moat structure in a kind of chip.
Background technique
In manufacture of semiconductor, the wafer for being formed with integrated circuit is usually cut into chip (chip) one by one, so
The semiconductor package that these chip manufacturings are different at function afterwards.As shown in Figure 1, it is shown as the partial top view of wafer,
Include multiple chips 101 in wafer, is separated by between adjacent two chip with Cutting Road 102 (Scribe line or scribe line).
Each chip includes the device architecture being formed on the substrate by techniques such as deposition, photoetching, etching, doping and heat treatments, interconnection
Structure and weld pad etc..Later, wafer is cut into multiple independent chips along Cutting Road.
When being cut to wafer, mechanical stress can be applied on the wafer, therefore, be easy made of cutting
Slight crack is caused in chip.In the prior art, damage of the semiconductor chip by cutting technique in order to prevent, can be in each chip
Device region and Cutting Road between formed surround chip protection ring 103 (Guard Ring).
As shown in Fig. 2, being shown as the A-A ' of Fig. 1 to sectional view, it is seen then that protection ring in the prior art is from bottom to top successively
Including contact bolt 104, the first becket 105, the first plug 106, the second becket 107, the second plug 108, third becket
109 and passivation protection layer 110, wherein surrounded around contact bolt and the first becket by dielectric layer 111, the first plug, the second gold medal
Belong to and being surrounded around ring, the second plug and third becket by dielectric layer 112, has one between dielectric layer 111 and dielectric layer 112
SiCN diffusion barrier layer 113, passivation protection layer successively include that oxide skin(coating) 1101, silicon nitride layer 1102 and polyamides are sub- from bottom to top
W can be used in the material of amine layer 1103, contact bolt and the first plug, and Cu, the second becket, can be used in the material of the first becket
Aluminium can be used in the material of two plugs and third becket.In order to reinforce the connection between metal and medium, each contact bolt, plug and
Also there is adhesion coating 114 between second, third becket and dielectric layer.
Due to, in existing chip protection ring structure include more metal layers, manufacture craft is complex, cost also compared with
Therefore how height provides a kind of new safeguard structure, to reduce process complexity, and reduces cost, while providing good core
Piece protection effect becomes those skilled in the art's important technological problems urgently to be resolved.
Utility model content
In view of the foregoing deficiencies of prior art, the purpose of this utility model is to provide moat knots in a kind of chip
Structure, for solving the problems, such as chip protection ring structure fabrication processes complexity, higher cost in the prior art.
In order to achieve the above objects and other related objects, the utility model provides moat structure in a kind of chip, comprising:
Substrate, definition has chip body region and the chip perimeter area around the chip body region on the substrate
Domain；
Diffusion barrier layer is located at the substrate surface, is embedded with moat ring structure in the substrate, is located at the chip
In neighboring area and cover under the diffusion barrier layer；
Dielectric layer is located at the diffusion barrier layer surface；
Metal interconnection structure and bond pad are located in the dielectric layer, the conductive metal layer of the metal interconnection structure
And the bond pad is located in the chip body region；
Passivation protection layer is located at the dielectric layer surface；
Wherein, moat structure there is aperture to be formed in the chip body region to expose described connect in the chip
Close weld pad；Moat structure also has moat groove structure in the chip, is formed in the chip perimeter region and right
Standard is in the moat ring structure, to block wafer cutting stress to transmit toward the chip body region；The moat groove
Structure includes the grooved ring of at least two discrete settings, wherein the grooved ring is extended to down in the dielectric layer, but does not run through institute
Diffusion barrier layer is stated, the aperture extends to the surface of the bond pad down.
Optionally, the moat ring structure includes the first becket of at least two discrete settings and multiple first conductive
Plug, the diffusion barrier layer cover first becket, and the conductive plunger is connected to below the becket, the slot
Ring is longitudinally aligned with first becket.
Optionally, the metal interconnection structure includes at least two conductive metal layer, in the dielectric layer there is upper layer to expand
Barrier layer is dissipated, the upper layer diffusion barrier layer is located therein the top of one layer of conductive metal layer, to prevent described in this layer
The diffusion of conductive metal layer, it includes the dielectric on the top surface of the upper layer diffusion barrier layer that the bottom surface of the grooved ring, which is located relatively at,
The non-through surface of layer.
Optionally, the metal interconnection structure, which further includes, is aligned at least two discrete settings on the moat ring structure
The second becket and multiple second metal plugs in the dielectric layer in the chip perimeter region, second becket
Below the upper layer diffusion barrier layer, second metal plug is connected to below second becket.
Optionally, the metal interconnection structure includes at least two conductive metal layer, in the dielectric layer there is upper layer to expand
Barrier layer is dissipated, the upper layer diffusion barrier layer is located therein the top of one layer of conductive metal layer, to prevent described in this layer
The diffusion of conductive metal layer, the bottom surface of the grooved ring include the exposing surface of the upper layer diffusion barrier layer.
Optionally, the metal interconnection structure, which further includes, is aligned at least two discrete settings on the moat ring structure
The second becket and multiple second metal plugs in the dielectric layer in the chip perimeter region, second becket
Below the upper layer diffusion barrier layer, second metal plug is connected to below second becket.
Optionally, the bottom surface of the grooved ring is located relatively at non-including the dielectric layer on the top surface of the diffusion barrier layer
Through surface.
Optionally, the grooved ring runs through the dielectric layer, and the bottom surface of the grooved ring includes the dew of the diffusion barrier layer
Surface out.
Optionally, the width range of the grooved ring is 1~3 μm, and the altitude range of the grooved ring is 2~10 μm, adjacent institute
The spacing range for stating grooved ring is 4~90 μm.
Optionally, the metal interconnection structure includes at least two conductive metal layer, conductive metal layer described in adjacent two layers
Between by conductive column connect, and be located at bottom the conductive metal layer below be connected with bottom conductive column.
Optionally, it is more formed in the substrate in the chip body region with the moat ring structure positioned at same
The conductive metal layer and multiple conductive plungers of layer structure, the conductive plunger are connected to below the conductive metal layer, the gold
Belong to diffusion barrier layer described in interconnection structure break-through and is connected to above the conductive metal layer.
Optionally, the passivation protection layer successively includes the first silicon dioxide layer, silicon nitride layer and the two or two from bottom to top
Silicon oxide layer.
Optionally, moat structure further includes polymeric layer in the chip, is located in the passivation protection layer, the slot
Ring is open from the polymeric layer top surface, and the aperture is open from the polymeric layer top surface.
As described above, moat structure in the chip of the utility model, has the advantages that the core of the utility model
Moat structure arranges that grooved ring, grooved ring effectively can block wafer to cut around chip body region in chip perimeter region in piece
It cuts stress to transmit toward chip body region, to prevent the generation of slight crack in chip.The utility model reduces metal material
It uses, can not only reduce process complexity, promote yield, also help reduction production cost.
Detailed description of the invention
Fig. 1 is shown as the partial top view of wafer in the prior art.
Fig. 2 is shown as the A-A ' of Fig. 1 to sectional view.
Fig. 3 is shown as the partial top view of the utility model wafer in embodiment one.
Fig. 4 is shown as the B-B ' of Fig. 3 to sectional view.
Fig. 5-Figure 13 is shown as the schematic diagram of the section structure that each step is presented in embodiment one.
Figure 14 is shown as the sectional structure chart that moat structure is presented in embodiment two in the chip of the utility model.
Figure 15 is shown as the sectional structure chart that moat structure is presented in embodiment three in the chip of the utility model.
Figure 16 is shown as the sectional structure chart that moat structure is presented in example IV in the chip of the utility model.
Figure 17 is shown as the sectional structure chart that moat structure is presented in embodiment five in the chip of the utility model.
Figure 18 is shown as the sectional structure chart that moat structure is presented in embodiment six in the chip of the utility model.
Component label instructions
101 chips
102 Cutting Roads
103 protection rings
104 contact bolts
105 first beckets
106 first plugs
107 second beckets
108 second plugs
109 third beckets
110 passivation protection layers
1101 oxide skin(coating)s
1102 silicon nitride layers
1103 polyimide layers
111,112 dielectric layers
113 SiCN diffusion barrier layers
114 adhesion coatings
200 Cutting Roads
I chip body region
II chip perimeter region
201 substrates
202 conductive metal layers
203 conductive plungers
204 adhesion coatings
205 first beckets
206 first conductive plungers
207 adhesion coatings
208 diffusion barrier layers
209 dielectric layers
The first dielectric layer of 209a
The second dielectric layer of 209b
210 metal interconnection structures
210a, 210b conductive metal layer
210c conductive column
210c ' conductive column through-hole
210d bottom conductive column
211 bond pads
212 passivation protection layers
The first oxide skin(coating) of 212a
212b silicon nitride layer
The second oxide skin(coating) of 212c
213 polymeric layers
213a first polymer layer opening
213b the second polymer layer opening
214 grooved rings
215 apertures
216 upper layer diffusion barrier layers
217 second beckets
218 second metal plugs
The width of W grooved ring
The height of H grooved ring
The spacing of D grooved ring
Specific embodiment
Illustrate the embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this theory
Content disclosed by bright book understands other advantages and effect of the utility model easily.The utility model can also be by addition
Different specific embodiments are embodied or practiced, and the various details in this specification can also be based on different viewpoints and answer
With carrying out various modifications or alterations under the spirit without departing from the utility model.
Fig. 3 is please referred to Figure 18.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of utility model is only shown with related component in the utility model rather than when according to actual implementation in schema then
Component count, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind
Become, and its assembly layout kenel may also be increasingly complex.
Embodiment one
In the present embodiment, moat structure fabrication is on a wafer in chip.Referring to Fig. 3, being shown as the wafer
Partial top view is provided with moat structure in multiple chips in the wafer, passes through between moat structure in adjacent chips
Cutting Road 200 is spaced.
As shown in figure 3, the definition of moat structure has chip body region I and around the chip body area in the chip
The chip perimeter region II of domain I, the chip perimeter region II are equipped with moat groove structure, the moat groove structure packet
The grooved ring 214 of at least two discrete settings is included, the grooved ring 214 is around the chip body region I, to block wafer to cut
Stress is transmitted toward the chip body region I.In the present embodiment, using straight-flanked ring, (Fig. 3 illustrates only rectangle to the grooved ring 214
Two sides of ring), and the quantity of the grooved ring 214 is 3, however in other embodiments, the shape of the grooved ring 214 can also
To be adjusted according to the actual profile and device layout of chip, the quantity of the grooved ring 214, which also can according to need, to be adjusted
It is whole, for example, 2~10, the protection scope of the utility model should not be excessively limited herein.
Referring to Fig. 4, being shown as the B-B ' of Fig. 3 to sectional view, it is seen that in addition to the moat groove structure, the chip
Interior moat structure further includes substrate 201, diffusion barrier layer 208, dielectric layer 209, metal interconnection structure 210, bond pad
211, passivation protection layer 212, polymeric layer 213 and aperture 215, wherein the diffusion barrier layer 208 is located at the substrate
201 surfaces are embedded with moat ring structure in the substrate 201, and the moat ring structure is located at the chip perimeter region
It in II and covers under the diffusion barrier layer 208, the moat ring structure includes the first of at least two discrete settings
The interface of becket 205 and multiple first conductive plungers 206, first conductive plunger 206 and the substrate 201 has adhesion
Layer 207, the diffusion barrier layer 208 covers first becket 205, and the conductive plunger 206 is connected to first gold medal
Belong to 205 lower section of ring.In the present embodiment, the moat groove structure is in alignment with the moat ring structure, and the grooved ring 214
It is longitudinally aligned with first becket 205.The dielectric layer 209 is located at 208 surface of diffusion barrier layer, and the metal is mutual
Connection structure 210 and the bond pad 211 are located in the dielectric layer 209, the conductive metal layer of the metal interconnection structure 210
And the bond pad 211 is located in the chip body region I, in the present embodiment, the bond pad 211 is close to the core
The edge piece body region I.The passivation protection layer 212 is located at 209 surface of dielectric layer, and the polymeric layer 213 is located at institute
Passivation protection layer surface is stated, the grooved ring 214 is open from 213 top surface of polymeric layer, and extends to the dielectric layer down
In 209, but do not run through the diffusion barrier layer 208, the aperture 215 is open from 213 top surface of polymeric layer, and past downward
The surface of the bond pad 211 is extended to, to expose the bond pad 211.
Specifically, the width W range of the grooved ring is 1~3 μm, the height H range of the grooved ring is 2~10 μm, adjacent
The space D range of the grooved ring is 4~90 μm.In the present embodiment, the bottom surface of the grooved ring 214 is located relatively at the diffusion barrier
It include the non-through surface of the dielectric layer 209 on the top surface of layer 208.
Specifically, the metal interconnection structure 210 includes at least two conductive metal layer.In the present embodiment, the metal
Interconnection structure 210 includes two conductive metal layer 210a, 210b, passes through conductive column between conductive metal layer described in adjacent two layers
210c connection, and be located at below the conductive metal layer 210b of bottom and be connected with bottom conductive column 210d.The conductive metal
The material of layer 210a, 210b and conductive column 210c includes but is not limited to tungsten, copper, aluminium etc..
It is located at together specifically, being more formed in the substrate of the chip body region I with the moat ring structure
The conductive metal layer 202 and multiple conductive plungers 203 of one layer of structure, the conductive plunger 203 are connected to the conductive metal layer
Below 202, diffusion barrier layer 208 described in 210 break-through of metal interconnection structure, and be connected on the conductive metal layer 202
Side.The material of the conductive metal layer 202 and the conductive plunger 203 includes but is not limited to tungsten, copper, aluminium etc..
Specifically, the passivation protection layer 212 successively includes the first oxide skin(coating) 212a, silicon nitride layer 212b from bottom to top
And the second oxide skin(coating) 212c.The material of the first oxide skin(coating) 212a and the second oxide skin(coating) 212c includes but unlimited
In the material of silica, the polymeric layer 213 include but is not limited to polyimides, the material of the diffusion barrier layer 208
Including but not limited to carbonitride of silicium.
As an example, manufacture moat structure in the chip the following steps are included:
Fig. 5 and Fig. 6 is please referred to, step S201 is executed: a substrate 201 is provided, the substrate surface has a diffusion barrier
Layer 208, and definition has the chip body region I and chip perimeter region II around the chip body region on the substrate,
It is embedded with moat ring structure in the substrate, be located in the chip perimeter region II and covers in the diffusion barrier layer
Under 208.The moat ring structure includes the first becket 205 and multiple first conductive plungers of at least two discrete settings
206, the interface of first conductive plunger 206 and the substrate 201 has adhesion coating 207, and the diffusion barrier layer 208 covers
First becket 205, the conductive plunger 206 are connected to 205 lower section of the first becket.It is described in the present embodiment
Moat groove structure is in alignment with the moat ring structure, and the grooved ring 214 is longitudinally aligned with first becket
205.It is more formed in the substrate of the chip body region I and is located on the same floor leading for structure with the moat ring structure
Metal layer 202 and multiple conductive plungers 203, the conductive plunger 203 are connected to 202 lower section of conductive metal layer.As
Example, as shown in figure 5, multiple conductive plungers 203 and multiple first conductive plungers 206 are initially formed in the substrate 201, it is described
Conductive plunger 203 is located in the substrate of the chip body region I, and first conductive plunger 206 is located at the chip
In the substrate of neighboring area II.As shown in fig. 6, then form conductive metal layer 202 on the conductive plunger 203, shape
At the first becket 205 on first conductive plunger 206, diffusion barrier layer 208 is re-formed on the substrate.
Specifically, forming conductive plunger groove in the substrate by photoetching process and etching technics first, then sink
In product conductive plunger material (such as W) Yu Suoshu conductive plunger groove, and institute is removed by chemical attack or chemical mechanical grinding
State conductive plunger material extra outside conductive plunger groove.In order to enhance the conductive plunger 203 and first conductive plunger
Combination between 206 and the substrate 201, and the diffusion of conductive plunger material is reduced, it can first sink before depositing conductive plunger
Bottom surface and side wall of one adhesion coating 204,207 of product in the conductive plunger groove.The diffusion barrier layer 208 is described for preventing
The diffusion of conductive metal layer 202,205 material of the first becket.The material of the diffusion barrier layer 208 includes but is not limited to
Carbonitride of silicium.
It please refers to Fig. 7 to Figure 10, executes step S202: forming dielectric layer 209 on the diffusion barrier layer, and form gold
Belong to interconnection structure 210 and bond pad 211 in the dielectric layer 209, the conductive metal layer of the metal interconnection structure 210 and
The bond pad 211 is located at the chip body region I, and the bond pad 211 is close to the chip body region side I
Edge.
Specifically, the metal interconnection structure 210 includes at least two conductive metal layer.In the present embodiment, the metal
Interconnection structure 210 includes two conductive metal layer 210a, 210b, passes through conductive column between conductive metal layer described in adjacent two layers
210c connection, and be located at below the conductive metal layer 210b of bottom and be connected with bottom conductive column 210d.The conductive metal
The material of layer 210a, 210b and conductive column 210c includes but is not limited to tungsten, copper, aluminium etc..
As an example, as shown in fig. 7, be initially formed the first dielectric layer 209a on the diffusion barrier layer 208, and form bottom
Layer conductive column 210d is in the first dielectric layer 209a of the chip body region I, the material of the bottom conductive column 210d
Tungsten can be selected in matter, and Fig. 7 is shown as the structure that the bottom conductive column 210d is presented after chemically mechanical polishing.Such as Fig. 8 institute
Show, then forms conductive metal layer 210b on the bottom conductive column 210d, Fig. 8 is shown as conductive metal layer 210b by carving
The structure presented after erosion is graphical.As shown in figure 9, being subsequently formed the second dielectric layer 209b in the first dielectric layer 209a
On, and formed in conductive column through-hole 210c ' the second dielectric layer of Yu Suoshu 209b.As shown in Figure 10, re-form conductive column 210c and
For conductive metal layer 210a in the second dielectric layer 209b, Figure 10 is shown as conductive metal layer 210a after etched features
The structure presented.Silica or low k dielectric can be selected in the material of the first dielectric layer 209a.Second dielectric layer
Silica or low k dielectric can be selected in the material of 209b.
In the present embodiment, also it is further formed in bond pad 211 (bond pad) the second dielectric layer of Yu Suoshu 209b, institute
Bond pad 211 is stated close to the chip body region edge I, is used for packaging and testing.
Figure 11 is please referred to, step 203 is executed: forming passivation protection layer 212 on the dielectric layer 209.
Specifically, being sequentially depositing the first oxide skin(coating) 212a, silicon nitride layer 212b and the second oxide skin(coating) from bottom to top
For 212c as the passivation protection layer 212, the material of the first oxide skin(coating) 212a and the second oxide skin(coating) 212c can
Select silica.
Figure 12 is please referred to, step 204 is executed: forming polymeric layer 213 in the passivation protection layer 212.
Specifically, the material of the polymeric layer 213 includes but is not limited to polyimides.It is also further in the present embodiment
The polymeric layer 213 is graphical, obtain first polymer layer opening 213a and the second polymer layer opening 213b, wherein
The first polymer layer opening 213a is corresponding with the position of the bond pad 211, the second polymer layer opening
213b is ring-type, is located at the chip perimeter region II.The first polymer layer opening 213a and the second polymer layer opening
213b can be formed by the methods of chemical wet etching or laser opening.
Figure 13 is please referred to, step S205 is executed: forming aperture 215 in the chip body region I to expose described connect
Weld pad 211 is closed, and synchronizes and to form moat groove structure in the chip perimeter region II to block wafer to cut stress toward institute
Chip body region I transmitting is stated, the moat groove structure is in alignment with the moat ring structure and including at least two
The grooved ring 214 of discrete setting, wherein the grooved ring 214 is open from 213 top surface of polymeric layer, and extends to down described
In dielectric layer 209, but not running through the diffusion barrier layer 208, the aperture 215 is open from 213 top surface of polymeric layer, and
The surface of the bond pad 211 is extended to down.
Specifically, first polymer layer opening 213a is extended to the bond pad 211 down by etching
Surface extends to the second polymer layer opening 213b in the dielectric layer 209 down.In the present embodiment, the grooved ring
214 bottom surface is relatively located at the non-through surface on the top surface of the diffusion barrier layer 208 including the dielectric layer 209a.
So far, moat structure in chip has been prepared.It should be pointed out that in other embodiments, the metal
Interconnection structure 210 can also have more layers metal, and its manufacturing process is also not necessarily limited to above-mentioned process flow, such as can basis
It needs to select single Damascus technics or dual damascene process, should not excessively limit the protection scope of the utility model herein.
Moat structure arranges grooved ring in chip perimeter region in the chip of the utility model, and grooved ring is around chip body area
Domain can effectively block wafer to cut stress and transmit toward chip body region, to prevent the generation of slight crack in chip.Due to slot
It is filled in ring without metal, it is possible to reduce the use of metal material can not only reduce process complexity, promote yield, also
Conducive to reduction production cost.
Embodiment two
The present embodiment and embodiment one use essentially identical technical solution, the difference is that, described in embodiment one
Grooved ring 214 is open from 213 top surface of polymeric layer, and is extended in the dielectric layer 209 down, and the grooved ring 214
Bottom surface is located relatively at the non-through surface on the top surface of the diffusion barrier layer 208 including the dielectric layer 209a.And this implementation
In example, the grooved ring 214 runs through the dielectric layer 209, and the bottom surface of the grooved ring 214 includes the diffusion barrier layer 208
Exposing surface, as shown in figure 14.
Embodiment three
The present embodiment and embodiment one use essentially identical technical solution, the difference is that, it is described in the present embodiment
There is upper layer diffusion barrier layer 216, the upper layer diffusion barrier layer 216 is located therein one layer of conductive gold in dielectric layer 209
Belong to the top of layer, to prevent the diffusion of this layer of conductive metal layer.Figure 15 is please referred to, core described in the present embodiment is shown as
The schematic diagram of the section structure that moat structure is presented in piece, as an example, the upper layer diffusion barrier layer 216 is located at described lead
Above metal layer 210b, and the bottom surface of the grooved ring 214 is located relatively on the top surface of the upper layer diffusion barrier layer 216 and includes
The non-through surface of the dielectric layer 209b.The material of the upper layer diffusion barrier layer 216 includes but is not limited to carbonitride of silicium.
The present embodiment is suitable for the situation that the conductive metal layer 210b selects Cu or other easy diffusion materials.
Example IV
The present embodiment and embodiment three use essentially identical technical solution, the difference is that, described in embodiment three
Grooved ring 214 is open from 213 top surface of polymeric layer, and is extended in the dielectric layer 209 down, and the grooved ring 214
Bottom surface is located relatively at the non-through surface on the top surface of the upper layer diffusion barrier layer 216 including the dielectric layer 209b.And this
In embodiment, the bottom surface of the grooved ring 214 includes the exposing surface of the upper layer diffusion barrier layer 216, as shown in figure 16.
Embodiment five
The present embodiment and embodiment three use essentially identical technical solution, the difference is that, described in the present embodiment
Metal interconnection structure 210 further include the second becket 217 for being aligned at least two discrete settings in the moat structure and
In the dielectric layer 209 in the chip perimeter region, second becket 217 is located at multiple second metal plugs 218
216 lower section of upper layer diffusion barrier layer, second metal plug 218 are connected to 217 lower section of the second becket, such as scheme
Shown in 17.
In the present embodiment, the chip perimeter region II has grooved ring 214 and becket 217 simultaneously, has taken into account the two
Advantage, and reduce the use of metal material, process complexity can be not only reduced, yield is promoted, also helps reduction production
Cost.
Embodiment six
The present embodiment and embodiment five use essentially identical technical solution, the difference is that, described in embodiment five
Grooved ring 214 is open from 213 top surface of polymeric layer, and is extended in the dielectric layer 209 down, and the grooved ring 214
Bottom surface is located relatively at the non-through surface on the top surface of the upper layer diffusion barrier layer 216 including the dielectric layer 209b.And this
In embodiment, the bottom surface of the grooved ring 214 includes the exposing surface of the upper layer diffusion barrier layer 216, as shown in figure 18.
In conclusion moat structure passes through the neighboring area arrangement of grooves in chip body layer in the chip of the utility model
Ring, grooved ring can effectively block wafer to cut stress and transmit toward chip interior, thus anti-around the intermediate region of chip body layer
Only in chip slight crack generation.Due to being filled in grooved ring without metal, it is possible to reduce the use of metal material can not only reduce
Process complexity promotes yield, also helps reduction production cost.So the utility model effectively overcomes in the prior art
Various shortcoming and have high industrial utilization value.
The above embodiments are only illustrative of the principle and efficacy of the utility model, and not for limitation, this is practical new
Type.Any person skilled in the art can all carry out above-described embodiment under the spirit and scope without prejudice to the utility model
Modifications and changes.Therefore, such as those of ordinary skill in the art without departing from the revealed essence of the utility model
All equivalent modifications or change completed under mind and technical idea, should be covered by the claim of the utility model.
Claims (13)
1. moat structure in a kind of chip characterized by comprising
Substrate, definition has chip body region and the chip perimeter region around the chip body region on the substrate；
Diffusion barrier layer is located at the substrate surface, is embedded with moat ring structure in the substrate, is located at the chip perimeter
In region and cover under the diffusion barrier layer；
Dielectric layer is located at the diffusion barrier layer surface；
Metal interconnection structure and bond pad are located in the dielectric layer, the conductive metal layer of the metal interconnection structure and institute
Bond pad is stated to be located in the chip body region；
Passivation protection layer is located at the dielectric layer surface；
Wherein, there is moat structure aperture to be formed in the chip body region to expose the seam welding in the chip
Pad；Moat structure also has moat groove structure in the chip, be formed in the chip perimeter region and in alignment with
The moat ring structure, to block wafer cutting stress to transmit toward the chip body region；The moat groove structure
Grooved ring including at least two discrete settings, wherein the grooved ring is extended to down in the dielectric layer, but does not run through the expansion
Barrier layer is dissipated, the aperture extends to the surface of the bond pad down.
2. moat structure in chip according to claim 1, it is characterised in that: the moat ring structure includes at least
The first becket and multiple first conductive plungers of two discrete settings, the diffusion barrier layer cover first becket,
The conductive plunger is connected to below the becket, and the grooved ring is longitudinally aligned with first becket.
3. moat structure in chip according to claim 2, it is characterised in that: the metal interconnection structure includes at least
Two conductive metal layer, has upper layer diffusion barrier layer in the dielectric layer, and the upper layer diffusion barrier layer is located therein one layer
The top of the conductive metal layer, to prevent the diffusion of this layer of conductive metal layer, the bottom surface of the grooved ring is located relatively at
It include the non-through surface of the dielectric layer on the top surface of the upper layer diffusion barrier layer.
4. moat structure in chip according to claim 3, it is characterised in that: the metal interconnection structure further includes pair
Standard on the moat ring structure the second becket of at least two discrete settings and multiple second metal plugs in the core
In the dielectric layer of piece neighboring area, second becket is located at below the upper layer diffusion barrier layer, second gold medal
Belong to plug to be connected to below second becket.
5. moat structure in chip according to claim 2, it is characterised in that: the metal interconnection structure includes at least
Two conductive metal layer, has upper layer diffusion barrier layer in the dielectric layer, and the upper layer diffusion barrier layer is located therein one layer
The top of the conductive metal layer, to prevent the diffusion of this layer of conductive metal layer, the bottom surface of the grooved ring includes described
The exposing surface of upper layer diffusion barrier layer.
6. moat structure in chip according to claim 5, it is characterised in that: the metal interconnection structure further includes pair
Standard on the moat ring structure the second becket of at least two discrete settings and multiple second metal plugs in the core
In the dielectric layer of piece neighboring area, second becket is located at below the upper layer diffusion barrier layer, second gold medal
Belong to plug to be connected to below second becket.
7. moat structure in chip according to claim 1, it is characterised in that: the bottom surface of the grooved ring is located relatively at institute
State the non-through surface on the top surface of diffusion barrier layer including the dielectric layer.
8. moat structure in chip according to claim 1, it is characterised in that: the grooved ring runs through the dielectric layer,
And the bottom surface of the grooved ring includes the exposing surface of the diffusion barrier layer.
9. moat structure in chip according to claim 1, it is characterised in that: the width range of the grooved ring is 1~3
μm, the altitude range of the grooved ring is 2~10 μm, and the spacing range of the adjacent grooved ring is 4~90 μm.
10. moat structure in chip according to claim 1, it is characterised in that: the metal interconnection structure includes extremely
Lack two conductive metal layer, connected between conductive metal layer described in adjacent two layers by conductive column, and is located at the described of bottom and leads
Bottom conductive column is connected with below metal layer.
11. moat structure in chip according to claim 1, it is characterised in that: the chip body region it is described
The conductive metal layer and multiple conductive plungers that structure is located on the same floor with the moat ring structure are more formed in substrate, it is described
Conductive plunger is connected to below the conductive metal layer, and diffusion barrier layer described in the metal interconnection structure break-through is simultaneously connected to institute
It states above conductive metal layer.
12. moat structure in chip according to claim 1, it is characterised in that: the passivation protection layer is from bottom to top
It successively include the first silicon dioxide layer, silicon nitride layer and the second silicon dioxide layer.
13. moat structure in chip according to claim 1, it is characterised in that: moat structure is more in the chip
Including polymeric layer, it is located in the passivation protection layer, the grooved ring is open from the polymeric layer top surface, and the aperture is from institute
State polymeric layer top surface opening.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110518002A (en) * | 2019-07-26 | 2019-11-29 | 通富微电子股份有限公司 | The forming method of encapsulating structure |
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| CN110518002A (en) * | 2019-07-26 | 2019-11-29 | 通富微电子股份有限公司 | The forming method of encapsulating structure |
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