CN106898580B - Chip protection ring, semiconductor chip, semiconductor crystal wafer and packaging method - Google Patents
Chip protection ring, semiconductor chip, semiconductor crystal wafer and packaging method Download PDFInfo
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- CN106898580B CN106898580B CN201510960946.7A CN201510960946A CN106898580B CN 106898580 B CN106898580 B CN 106898580B CN 201510960946 A CN201510960946 A CN 201510960946A CN 106898580 B CN106898580 B CN 106898580B
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- chip
- becket
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- ring
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 80
- 238000000034 method Methods 0.000 title claims abstract description 29
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 14
- 239000013078 crystal Substances 0.000 title claims abstract description 10
- 238000005538 encapsulation Methods 0.000 claims abstract description 18
- 239000010410 layer Substances 0.000 claims description 79
- 239000000758 substrate Substances 0.000 claims description 39
- 229910052751 metal Inorganic materials 0.000 claims description 36
- 239000002184 metal Substances 0.000 claims description 36
- 238000005520 cutting process Methods 0.000 claims description 29
- 239000011229 interlayer Substances 0.000 claims description 16
- 239000011241 protective layer Substances 0.000 claims description 11
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 8
- 238000005516 engineering process Methods 0.000 claims description 8
- 230000002093 peripheral effect Effects 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 239000011521 glass Substances 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 239000004411 aluminium Substances 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 238000006396 nitration reaction Methods 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- 229910003978 SiClx Inorganic materials 0.000 claims 1
- CKUAXEQHGKSLHN-UHFFFAOYSA-N [C].[N] Chemical compound [C].[N] CKUAXEQHGKSLHN-UHFFFAOYSA-N 0.000 claims 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- 238000003475 lamination Methods 0.000 claims 1
- 229910052760 oxygen Inorganic materials 0.000 claims 1
- 239000001301 oxygen Substances 0.000 claims 1
- 239000004020 conductor Substances 0.000 abstract description 4
- 238000002955 isolation Methods 0.000 abstract description 4
- 230000001681 protective effect Effects 0.000 abstract description 4
- 238000005549 size reduction Methods 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 18
- 239000002585 base Substances 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000003466 welding Methods 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 244000247747 Coptis groenlandica Species 0.000 description 1
- 235000002991 Coptis groenlandica Nutrition 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- HUTDUHSNJYTCAR-UHFFFAOYSA-N ancymidol Chemical compound C1=CC(OC)=CC=C1C(O)(C=1C=NC=NC=1)C1CC1 HUTDUHSNJYTCAR-UHFFFAOYSA-N 0.000 description 1
- 239000011324 bead Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000003776 cleavage reaction Methods 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000004021 metal welding Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- 230000007017 scission Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention provides a kind of chip protection ring, semiconductor chip, semiconductor crystal wafer and packaging method; by the way that the top becket of the protection ring near each bond pad is disconnected; simultaneously by the size reduction of secondary top-level metallic ring; make other metallic rings contacts of top conductive plunger not with secondary top-level metallic ring and lower section; to keep the isolation of top becket hanging; even if so that bonding wire and protection ring top metallic rings contact in welded encapsulation; will not be short-circuit, avoiding the protective effect that protection ring is still ensured that while weldering short-circuit between conductors.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of chip protection ring, semiconductor chip, semiconductors
Wafer and packaging method.
Background technique
In manufacture of semiconductor, the wafer for being formed with integrated circuit is usually cut into chip (chip) one by one, so
The semiconductor package that these chip manufacturings are different at function afterwards.It is the top view of wafer, wafer referring in particular to Fig. 1, Fig. 1
It is made of multiple chips 10, and with Cutting Road (scribe line or scribe line, block) 11 phases between adjacent two chip 10
Every.Each chip 10 includes the device being formed on the substrate by techniques such as deposition, photoetching (lithographic), etching, doping and heat treatments
Part structure, interconnection structure and weld pad etc..Later, wafer is cut into multiple independent chips 10 along Cutting Road 11.Therefore exist
Functional element is not present at corresponding 11 position of Cutting Road, generally only includes the interlayer dielectric layer in substrate.
However, can be applied to mechanical stress on the wafer when cutting wafer, therefore, it is easy cutting
Made of cause to be cracked in chip.Furthermore it is formed with multiple semiconductor devices in usual substrate, is partly led to be dielectrically separated from these
Body device needs to deposit stacked insulating layer (Stacked Insulating Films) during making semiconductor subassembly,
Such as metal interlamination medium layer (IMD, Inter-metal Dielectric), interlayer dielectric layer (ILD, Inter-layer
Dielectric), these stacked insulating layers can be covered on Cutting Road, thus, its side will be exposed when cutting to wafer
Wall surface, the stacked insulating layer and its sidewall surfaces exposed constitute the path that aqueous vapor penetrates, and then lead to semiconductor
Device failure.
Please refer to Fig. 2 and Fig. 3, in the prior art, in order to prevent semiconductor chip by cutting technique damage and keep away
Exempt from the situation that aqueous vapor causes deterioration, the protection for surrounding chip 10 can be formed between the device region and Cutting Road 11 of each chip 10
Ring (seal ring, also referred to as sealing ring, protective ring) 12, protection ring 12 is in multilayered structure, by metal layer and insulating layer according to one
Fixed rule is alternately stacked, specifically, include diffusion layer (diff layer) 121 in the interlayer dielectric layer 122,
The conductive plunger of more metal layers (metal layer), adjacent two metal layer 123 of electrical connection above diffusion layer 121
(contact) 124 and insulating protective layer (passivation layer) 125, the more metal layers include from the bottom to top according to
Bottom metal layer 1231, intermediate metal layer 1232 and the top layer metallic layer 1233 of secondary formation, the insulating protective layer 125 are located at
On top layer metallic layer 1233.Wherein, for Cutting Road 11 between adjacent two protection ring 12, protection ring 12 can stop aqueous vapor to be permeated
Or such as the chemical damage of the diffusion containing pollution sources sour object, object containing alkali, play the role of protecting chip 10.
Fig. 3 and 4 are please referred to, the packaging method of chip 10 is usually that chip 10 is pasted on to the center of encapsulation base plate,
Then the bond pad on the weld pad (Pad) 13 and pedestal on chip 10, bonding are connected using bonding wires 14 such as gold thread, aluminum steel or copper wire
Each pin of pad and pedestal corresponds, and is finally completed chip package.Bonding wire 14 is connected to bonding usually using pressure welding method
On pad and weld pad 13, i.e., directly bonding wire 14 is pressed together on the weld pad 13 of chip by external force.Inventors have found that due to bonding wire 14
10 surface of off-chip piece is very close, and protection ring 12 is also very close to apart from weld pad 13, may be due to work during pressure welding
The factors such as skill conditional instability lead to that soldered ball is excessive, offset, so be in contact it is easy to appear bonding wire 14 and protection ring 12
Situation causes the protective layer 125 above protection ring to be crushed, and bonding wire 14 and the top layer metallic layer 1233 of protection ring 12 directly connect
Touching.If similar situation also occurs for other bonding wires, this two root beads line 14 due to simultaneously contact protection ring 12 top-level metallic
Layer 1233 and short circuit occurs, it is most likely that cause chip 10 to fail, such as the certain function cisco unity malfunctions or core of chip 10
The requirement of design is not achieved in the performance of piece.And the wafer for remanufacturing same process condition will spend a large amount of manpower financial capacity.
If with acid liquid corrosion soldered ball, the aluminium on weld pad 13 can also be corroded, can not pressure welding again.
Summary of the invention
The purpose of the present invention is to provide a kind of chip protection ring, semiconductor chip, semiconductor crystal wafer and packaging method, energy
Bonding wire when chip package is enough avoided to touch protection ring and short-circuit problem occurs.
To solve the above problems, the present invention proposes a kind of chip protection ring, it is formed in around a chip and with the chip
With in semi-conductive substrate, the chip protection ring includes several metals stacked gradually supported by the semiconductor substrate
Ring and the conductive plunger being set between adjacent metal ring, and each becket surrounds the chip setting；Top gold
Category ring be discontinuous becket, the chip adjacent bond weld pad it is separated；The outer edge of secondary top-level metallic ring half
Diameter is smaller than the outer edge radius of top becket, the inward flange of the inward flange radius ratio top becket of secondary top-level metallic ring
Radius is big, and top conductive plunger is distributed in the periphery of the secondary top-level metallic ring, only with top metallic rings contact, remainder layer
Conductive plunger connect adjacent becket.
Further, the upper surface of the top becket flushes or is higher by institute with the upper surface of the bond pad
State the upper surface of bond pad.
Further, the height of the bottom of the top conductive plunger is lower than time height at the top of top-level metallic ring.
Further, the top becket is in the separated gap width of the adjacent bond weld pad of the chip
The width of width~0.5 bond pad of 0.05 bond pad.
Further, the chip protection ring further includes the expansion between the semiconductor substrate and bottom becket
Dissipate ring and the protective layer positioned at top becket upper surface.
Further, composite layer made of the protective layer is oxide layer, nitration case or is stacked as oxide layer and nitration case
Structure.
Further, interlayer dielectric layer is provided between adjacent two layers becket, the conductive plunger is formed in the layer
Between in dielectric layer.
Further, the material of the becket and conductive plunger includes copper, tungsten, aluminium or nickel.
Further, the interlayer dielectric layer include silicon oxide film, silicon carbonitride film, silicon oxynitride film, silicon nitride film and
At least one of organic glass.
Further, the depth of the becket is 5~50 microns, and width is 0.2 micron~5 microns.
Further, each layer conductive plunger below the secondary top-level metallic ring is aligned or staggered row in vertical direction
Column.
Further, in each layer conductive plunger below the secondary top-level metallic ring, it is located at outside each layer becket
The conductive plunger of edge and the outer peripheral distance of the becket are 0~1 conductive plunger width.
The present invention also provides a kind of semiconductor chips, comprising:
Semiconductor substrate；
It is set to the circuit module in the semiconductor substrate and being supported by it, the circuit module includes the more of encapsulation
A bond pad；And
Around the above-mentioned chip protection ring of the circuit module.
The present invention also provides a kind of semiconductor crystal wafers, comprising:
Semiconductor substrate,
The multiple semiconductor chips for being set in the semiconductor substrate and being supported by it, the semiconductor chip have upper
The chip protection ring stated；And
Between adjacent semiconductor chips and the Cutting Road of each semiconductor chip is defined, the Cutting Road is located at described
On the outside of chip protection ring.
The present invention also provides a kind of chip packaging methods, comprising:
Semiconductor chip is provided, the semiconductor chip includes semiconductor substrate and is set to the semiconductor substrate
In and the circuit module that is supported by it；
The bond pad of multiple chip packages is formed in the circuit module periphery, the bond pad connects circuit mould
Block；
The chip protection ring as described in the present invention for surrounding the semiconductor chip is formed in the bond pad periphery；With
And
One encapsulation base plate with bond pad is provided, and the semiconductor chip is pasted on to the center of the encapsulation base plate
Position；
Each bond pad is connected with bond pad corresponding on encapsulation base plate using metal wire.
Further, the connection of the metal wire and bond pad is realized using bond technology.
Further, the bond technology includes:
Metal connecting line ball is played on the bond pad；
The metal wire is pressed on the metal connecting line ball.
Compared with prior art, chip protection ring provided by the invention, semiconductor chip, semiconductor crystal wafer and encapsulation side
Method, by disconnecting the top becket of the protection ring near each bond pad, while by the size of secondary top-level metallic ring
It reduces, makes other metallic rings contacts of top conductive plunger not with secondary top-level metallic ring and lower section, to make top metal
Ring isolation is hanging, even if so that in welded encapsulation bonding wire and protection ring top metallic rings contact, will not short circuit, avoiding
Weld the protective effect that protection ring is still ensured that while short-circuit between conductors.
Detailed description of the invention
Fig. 1 is a kind of overlooking structure diagram of semiconductor crystal wafer of the prior art；
Fig. 2 is the overlooking structure diagram of existing chip protection ring；
Fig. 3 is the schematic cross-sectional view of existing chip protection ring；
Fig. 4 is existing chip package schematic diagram；
Fig. 5 A and 5B are the overlooking structure diagrams of the chip protection ring of the specific embodiment of the invention；
Fig. 5 C is the schematic cross-sectional view of the XX ' line along Fig. 5 B；
Fig. 5 D is the schematic cross-sectional view of the YY ' line along Fig. 5 B；
Fig. 6 is the semiconductor chip packaging method flow diagram of the specific embodiment of the invention.
Specific embodiment
To be clearer and more comprehensible the purpose of the present invention, feature, a specific embodiment of the invention is made with reference to the accompanying drawing
Further instruction, however, the present invention can be realized with different forms, it should not be to be confined to the embodiment described.
Please also refer to Fig. 5 A to 5D, the present invention proposes a kind of chip protection ring (seal ring) 12, sets around a chip
It sets and is formed on same semi-conductive substrate (not shown) with the chip, the chip protection ring 12 includes being served as a contrast by the semiconductor
Several beckets stacked gradually 123 of bottom support and the conductive plunger 124 being set between adjacent metal ring, and it is each
A becket 123 is arranged around the chip, wherein top becket (top metal, TM) 1231 is discontinuous gold
Belong to ring, in separated, the radius ratio top gold of secondary top-level metallic ring 1232 of the adjacent bond weld pad (Pad) 13 of the chip
The radius for belonging to ring 1231 is small, and top conductive plunger 1241 is distributed in the periphery of the secondary top-level metallic ring, only golden with top
Belong to ring 1231 to contact, the conductive plunger of remainder layer connects adjacent becket.
Wherein, the semiconductor substrate can be silicon substrate, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator (SOI) lining
Bottom, germanium on insulator (GOI) substrate, glass substrate or III-V compound substrate (such as silicon nitride or GaAs etc.) etc., tool
There is the device region to form the chip 10, cut around the protection ring region of the device region and around protection ring region and device region
The area Ge Dao 11, surface have interlayer dielectric layer 122, and the interlayer dielectric layer 122 includes silicon oxide film, silicon carbonitride film, low Jie
One or more (multilayer film is laminated), low-dielectric constant dielectric medium film can be phosphorosilicate glass in K dielectric film etc.
(PSG), boron-phosphorosilicate glass (BPSG), fluorine silica glass (FSG), spin-coating glass, spin on polymers etc..The semiconductor of the device region
Substrate surface is formed with 10 circuit of chip, and the Cutting Road area 11 is to be formed after chip circuit, carries out the position of cutting technique,
Several device regions of semiconductor substrate are separated from each other by the cutting technique, and become independent chip 10, and described are cut
The area Ge Dao 11 is removed in cutting technique.The chip protection ring 12 is formed in the interlayer dielectric layer 122 of protection ring region,
Chip protection ring 12 can stop 122 sidewall surfaces of interlayer dielectric layer exposed after steam or impurity Self cleavage technique to enter
Device region avoids the problem that cutting causes the pollution of 10 circuit of chip of device region, while protection has partly leading for chip circuit
Body substrate is be easy to cause the chip circuit of device region to be damaged in the cutting technique by biggish mechanical force or stress
The problem of hurting.
The material of each layer becket of chip protection ring 12 includes copper, tungsten, aluminium, cobalt or nickel, the material of each layer becket 123
Can be identical or not identical, each layer becket 123 overlaps, by interlayer dielectric layer between adjacent two layers becket 123
122 isolation.
Specifically, as shown in Figure 5A, top becket 1231 is made of several discrete metal wires, adjacent wires
Between be isolated by interlayer dielectric layer 122, i.e., top becket 1231 be discontinuous becket, metal wire is in the chip
Adjacent bond weld pad (Pad) 13 it is separated, make the top becket of the chip protection ring on 13 side of each bond pad
1231 all mutually it is independent, be mutually not connected to, thus can to avoid after packaging and routing bonding wire short circuit is formed by chip protection ring.
In preferred version, top becket 1231 need to disconnect the size of very little, so as not to influencing the guarantor of seal ring
The gap size W of shield effect, disconnection depends on craft precision, especially bond technology precision, for example, 0.05 bond pad
The width of 13 width~0.5 bond pad 13, when bond pad width is 0.5 μm, the gap size W of disconnection is 0.25
μm~0.5 μm.In order to prevent aqueous vapor to the greatest extent, minimum metal spacing as defined in design rule can be designed as, such as weld
Disk minimum spacing is 0.18 μm, then W=0.18 μm, can also be specifically arranged according to the actual conditions of manufacturing process, the present invention is to this
Not limit.
It please refers to Fig. 5 B to Fig. 5 D, in the present embodiment, conductive plunger 124 is provided between adjacent two layers becket 123.
It is set between top becket 1231 and time top-level metallic ring 1232 (becket of the arest neighbors i.e. below top becket)
Top conductive plunger (top via or conductive plunger) 1241 structures are equipped with, the top contact of top conductive plunger 1241 is most
Top-level metallic ring 1231, bottom is vacantly in interlayer dielectric layer 122.Concrete methods of realizing are as follows: reduce time top-level metallic ring 1232
Size (in Fig. 5 C time top-level metallic ring 1232 smaller than the radius of top becket 1231), by top conductive plunger
(top via) 1241 is distributed in the peripheral two sides of time top-level metallic ring 1232, so that it will not with secondary top-level metallic ring 1232 and
Other beckets 123 of lower section contact.Since top conductive plunger 1241 is hindered without becket (metal layer) below
Gear, in practical manufacturing process, the through-hole (top via) that top conductive plunger 1241 is filled can etch the deep of (etch)
A bit, it but will not generally touch in secondary top-level metallic ring 1232, i.e. the bottom of top conductive plunger 1241 is lower than time top layer
The top of becket 1232.Top becket 1231 may be implemented in this way to be isolated with each becket of lower section, and then will be every
The top becket 1231 of chip protection ring 12 around a bond pad 13 is isolated vacantly, accordingly even when the bonding wire in routing
Top becket 1231 is touched, weldering short-circuit between conductors will not be caused.In addition, the bottom of top conductive plunger is located at time top
The periphery of layer becket 1232, and do not contacted with other beckets 123, so as to enhance top becket 1231 and most push up
Mechanical strength between layer conductive plunger, the mechanical strength are enough to prevent when Cutting Road 11 carries out the cutting technique of chip, cut
The rupture or be layered to the extension of chip 10 that 11st area Ge Dao generates, preferably protect chip 10, guarantee by after cutting technique
Chip circuit it is functional.Therefore hanging top conductive plunger structure improves chip protection ring 12 to the guarantor of chip 10
Shield effect.
In the present embodiment, each layer becket can be formed with conductive plunger by dual damascene process.The becket
Depth be 5~50 microns, width be 0.2 micron~5 microns, i.e., in dual damascene process etch interlayer dielectric layer 122
When forming the deep trench for making becket, the etching depth of the deep trench is 5~50 microns, and width is 0.2 micron~5 micro-
Rice,
Please refer to Fig. 5 C to Fig. 5 D, in the present embodiment, in secondary top-level metallic ring 1232 and each becket below, phase
Multiple conductive plungers 124 are set between adjacent double layer of metal ring 123, and top and the upper layer becket bottom of these conductive plungers connect
It is contacted at the top of touching, bottom and lower metal ring, so that the connection of adjacent two layers becket is realized, under this secondary top-level metallic is circumferential
The structure of interconnection can shield the electromagnetic interference outside chip 10, while aqueous vapor being stopped to invade from side fracture, and that improves chip can
By property.Wherein, each layer conductive plunger 124 of 1232 lower section of secondary top-level metallic ring can be mutually aligned in vertical direction,
It can also be staggered, preferably be staggered, to improve the density and quantity of conductive plunger 124, and then improve chip protection
The mechanical strength of ring 12.And in each layer conductive plunger 124 of secondary 1232 lower section of top-level metallic ring, it is located at each layer becket
123 outer peripheral conductive plungers 124 and this layer of outer peripheral distance of becket 123 are 0~1 conductive plunger width, such as when
The transverse width of conductive plunger 124 is 0.25 μm, is located at each layer outer peripheral conductive plunger 124 of the becket 123 and the layer
The outer peripheral distance of becket 123 is 0~0.25 μm.
In the present embodiment, diffusion is additionally provided between the bottom becket (first layer metal ring M1) and semiconductor substrate
Electrostatic caused by cutting at Cutting Road 11 can be grounded by ring 121 nearby, by electrostatic and cutting stress to chip 10
Impact is minimized.In addition, 1231 upper surface of top becket is additionally provided with protective layer 125 (or passivation layer), protective layer 125
For silicon oxide film, nitride film or the silicon oxide film and silicon nitride film that are laminated in sequence, 125 covering protection ring 12 of protective layer
Top becket 1231 and bond pad 13 is also partly covered, to form the pressure welding position for exposing bond pad 13
Opening.Preferably, the upper surface of the top becket 1231 flushes or is higher by with the upper surface of the bond pad 13
Prevented with limiting the tin ball position of pressure welding by the opening of protective layer 125 and height the upper surface of the bond pad 13
Only tin ball is excessive.
Please continue to refer to Fig. 5 A to 5D, the present invention also provides a kind of semiconductor chips, comprising:
Semiconductor substrate (not shown)；
It is set to the circuit module in the semiconductor substrate and being supported by it, the circuit module includes the more of encapsulation
A bond pad 13 (being output and input for signal)；And
Around the said chip protection ring 12 of the circuit module.
Please continue to refer to Fig. 5 A to 5D, the present invention also provides a kind of semiconductor crystal wafers, comprising:
Semiconductor substrate (not shown)；
The multiple semiconductor chips 10 for being set in the semiconductor substrate and being supported by it, the semiconductor chip have
Above-mentioned chip protection ring 12；And
Between adjacent semiconductor chips and the Cutting Road 11 of each semiconductor chip is defined, the Cutting Road 11 is located at
12 outside of chip protection ring.
Fig. 5 A to 5D and Fig. 6 is please referred to, the present invention also provides a kind of chip packaging methods, comprising:
S1, provides semiconductor chip 10, and the semiconductor chip includes that semiconductor substrate and being set to described is partly led
In body substrate and the circuit module that is supported by it；
S2 forms the bond pad 13 of multiple chip packages in the circuit module periphery, and the bond pad 13 connects
Connect circuit module；
S3 forms the said chip protection ring 12 for surrounding the circuit module in 13 periphery of bond pad；And
S4 provides an encapsulation base plate with bond pad, and the semiconductor chip is pasted on the encapsulation base plate
Center；
S5 is connected each bond pad with bond pad corresponding on encapsulation base plate using metal wire.
In the present embodiment, step S1 provides a wafer with multiple semiconductor chips.Step S2 is each on wafer
Chip, which is formed, is used for external bond pad, and step S3 is each chip manufacturing encapsulation protection ring, between step S4, by
The Cutting Road of chip chamber is cut, and each semiconductor chip is separated into independent chip individual.In step s 5, the metal welding
The connection of line and bond pad realizes that the bond technology includes: using bond technology
Metal connecting line ball is played on the bond pad；
The metal wire is pressed on the metal connecting line ball.
In conclusion chip protection ring provided by the invention, semiconductor chip, semiconductor crystal wafer and packaging method, pass through
The top becket of protection ring near each bond pad disconnects to the size of very little, while by the ruler of secondary top-level metallic ring
Very little diminution makes other metallic rings contacts of top conductive plunger not with secondary top-level metallic ring and lower section, to keep top golden
It is hanging to belong to ring isolation, even if so that in welded encapsulation bonding wire and protection ring top metallic rings contact, will not short circuit；Simultaneously
Since top becket can disconnect the size of very little, so still ensuring that protection ring while avoiding weldering short-circuit between conductors
Protective effect.
Obviously, those skilled in the art can carry out various modification and variations without departing from spirit of the invention to invention
And range.If in this way, these modifications and changes of the present invention belong to the claims in the present invention and its equivalent technologies range it
Interior, then the present invention is also intended to include these modifications and variations.
Claims (17)
1. a kind of chip protection ring is formed on the same semiconductor substrate around a chip and with the chip, which is characterized in that
Including several beckets stacked gradually supported by the semiconductor substrate and it is set to leading between adjacent metal ring
Electric plug, and each becket surrounds the chip setting；Top becket is discontinuous becket, in the chip
Adjacent bond weld pad it is separated；The outer edge radius of the outer edge radius ratio top becket of secondary top-level metallic ring is small,
The inward flange radius of the inward flange radius ratio top becket of secondary top-level metallic ring is big, and top conductive plunger is distributed in described
The periphery of secondary top-level metallic ring, only with top metallic rings contact, the conductive plunger of remainder layer connects adjacent becket.
2. chip protection ring as described in claim 1, which is characterized in that the upper surface of the top becket connects with described
The upper surface for closing weld pad flushes or is higher by the upper surface of the bond pad.
3. chip protection ring as described in claim 1, which is characterized in that the height of the bottom of the top conductive plunger is low
Height in the top of secondary top-level metallic ring.
4. chip protection ring as described in claim 1, which is characterized in that the top becket is in the adjacent of the chip
The separated gap width of bond pad is the width of width~0.5 bond pad of 0.05 bond pad.
5. chip protection ring as described in claim 1, which is characterized in that the chip protection ring further includes partly leading positioned at described
Diffuser ring between body substrate and bottom becket and the protective layer positioned at top becket upper surface.
6. chip protection ring as claimed in claim 5, which is characterized in that the protective layer is for oxide layer, nitration case or by oxygen
Change lamination layer structure made of layer and nitration case stacking.
7. chip protection ring as described in claim 1, which is characterized in that be provided with inter-level dielectric between adjacent two layers becket
Layer, the conductive plunger are formed in the interlayer dielectric layer.
8. chip protection ring as claimed in claim 1 or 7, which is characterized in that the material of the becket includes copper, tungsten, aluminium
Or nickel；The material of the conductive plunger includes copper, tungsten, aluminium or nickel.
9. chip protection ring as claimed in claim 7, which is characterized in that the interlayer dielectric layer includes silicon oxide film, carbon nitrogen
At least one of SiClx film, silicon oxynitride film, silicon nitride film and organic glass.
10. chip protection ring as described in claim 1, which is characterized in that the depth of the becket is 5~50 microns, wide
Degree is 0.2 micron~5 microns.
11. chip protection ring as described in claim 1, which is characterized in that each layer below the secondary top-level metallic ring is conductive
Plug is aligned or is staggered in vertical direction.
12. the chip protection ring as described in claim 1 or 11, which is characterized in that each layer below the secondary top-level metallic ring
In conductive plunger, it is located at the outer peripheral conductive plunger of each layer becket and the outer peripheral distance of the becket is 0~1
Conductive plunger width.
13. a kind of semiconductor chip characterized by comprising
Semiconductor substrate；
It is set to the circuit module in the semiconductor substrate and being supported by it, the circuit module includes that the multiple of encapsulation connect
Close weld pad；And
Around the chip protection ring as described in any one of claims 1 to 12 of the circuit module.
14. a kind of semiconductor crystal wafer characterized by comprising
Semiconductor substrate,
The multiple semiconductor chips for being set in the semiconductor substrate and being supported by it, the semiconductor chip have such as right
It is required that chip protection ring described in any one of 1 to 12；And
Between adjacent semiconductor chips and the Cutting Road of each semiconductor chip is defined, the Cutting Road is located at the chip
On the outside of protection ring.
15. a kind of chip packaging method characterized by comprising
Semiconductor chip is provided, the semiconductor chip includes semiconductor substrate and is set in the semiconductor substrate simultaneously
The circuit module being supported by it；
The bond pad of multiple chip packages is formed in the circuit module periphery, the bond pad connects circuit module；
The core as described in any one of claims 1 to 12 for surrounding the semiconductor chip is formed in the bond pad periphery
Piece protection ring；And
One encapsulation base plate with bond pad is provided, and the semiconductor chip is pasted on to the centre bit of the encapsulation base plate
It sets；
Each bond pad is connected with bond pad corresponding on encapsulation base plate using metal wire.
16. chip packaging method as claimed in claim 15, which is characterized in that the connection of the metal wire and bond pad
It is realized using bond technology.
17. chip packaging method as claimed in claim 16, which is characterized in that the bond technology includes:
Metal connecting line ball is played on the bond pad；
The metal wire is pressed on the metal connecting line ball.
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| CN107706119B (en) * | 2017-09-21 | 2019-10-22 | 信利（惠州）智能显示有限公司 | Packaging method |
| CN109935548B (en) * | 2017-12-19 | 2020-12-22 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| JP7102609B2 (en) | 2018-09-04 | 2022-07-19 | 中芯集成電路（寧波）有限公司 | Wafer level system packaging method and packaging structure |
| CN110875281B (en) * | 2018-09-04 | 2022-03-18 | 中芯集成电路（宁波）有限公司 | Wafer level system packaging method and packaging structure |
| CN110534535A (en) * | 2019-08-01 | 2019-12-03 | 德淮半导体有限公司 | The wiring layer and preparation method thereof for preventing steam from spreading |
| CN110610934B (en) * | 2019-09-17 | 2021-11-16 | 珠海格力电器股份有限公司 | Power semiconductor device, packaging structure thereof, manufacturing method thereof and packaging method thereof |
| US11107807B1 (en) * | 2020-02-13 | 2021-08-31 | Nanya Technology Corporation | IC package having a metal die for ESP protection |
| CN113035835B (en) * | 2021-03-01 | 2022-04-01 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
| CN113410214B (en) * | 2021-05-27 | 2022-04-19 | 深圳市时代速信科技有限公司 | Semiconductor device structure and manufacturing method thereof |
| CN113764355B (en) * | 2021-09-06 | 2023-12-05 | 长江存储科技有限责任公司 | semiconductor structure |
| CN116454053B (en) * | 2023-06-16 | 2023-09-19 | 西安紫光国芯半导体股份有限公司 | Functional chip, wafer, module equipment and testing method |
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