JP2006269837A - Semiconductor element assembly, semiconductor element manufacturing method, and semiconductor element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique which prevents lowering of reliability by preventing chipping and peeling of a layer insulating film generated in a scribe line region in dicing, by preventing yield deterioration due to contamination and damage on a semiconductor device thereby caused by restraining water intrusion from an exposed part and by preventing the layer insulating film of the semiconductor element from being exposed. <P>SOLUTION: In a semiconductor element assembly wherein a plurality of semiconductor elements are constituted, a layer insulating film on a substrate provided to the semiconductor element is removed in a dicing part between the semiconductor element and an adjacent semiconductor element. A substrate surface exposed by the removal and an edge face of the layer insulating film are covered with a passivation film. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device.

  The scribe line in the semiconductor wafer (semiconductor element assembly) becomes an end portion of the semiconductor chip after cutting. By the way, in a process such as dicing or resin molding, it is one of the important factors not to cause chipping or insulating film peeling.

  Now, the interlayer insulating film and the passivation film in the semiconductor element are composed of films such as p-SiO, p-SiN, p-SiC, and p-SiCN formed by CVD (Chemical Vapor Deposition), for example. In many cases, these films keep the stacked structure in the scribe line portion of the semiconductor element assembly in the semiconductor element manufacturing process. These films have high strength and high adhesion between the films in the laminated structure. For this reason, chipping and film peeling that occur during dicing using a diamond blade are hardly a problem.

  Nowadays, in order to improve the processing speed of signals, the wiring design rules for semiconductor devices have been greatly miniaturized and narrowed. As miniaturization and narrowing proceed, signal delay, particularly RC delay, has become a problem. In order to solve this problem, it has been proposed that the interlayer insulating film between the wirings is made of a material having a low dielectric constant. Specifically, it has been proposed that the dielectric constant k be made of a low material of 3.5 or less. In general, such low dielectric constant materials often have a porous structure with weak mechanical strength and a small adhesion between films. Therefore, when dicing is performed on a semiconductor element assembly having a structure in which an interlayer insulating film having such characteristics is stacked even in a scribe line region, large-scale chipping or film peeling occurs in the interlayer insulating film, and the semiconductor element Yield decreases due to damage and contamination. For this reason, it is necessary to suppress chipping of the fragile interlayer insulating film in the scribe line region.

From this point of view, the semiconductor device has an element region provided on the semiconductor substrate, a scribe region provided around the element region, an interlayer insulating film and a passivation film sequentially provided in the element region and the scribe region. In the semiconductor device, a semiconductor device is proposed in which a groove that penetrates the passivation film and reaches at least the bottom surface of the interlayer insulating film is provided at an end of the scribe region adjacent to the element region (Japanese Patent Laid-Open No. Hei. 6-77315). That is, as shown in FIG. 3, a technique has been proposed in which a trench that penetrates the passivation film and reaches the interlayer insulating film is provided. In FIG. 3, 21 is a Si substrate, 22 is a field oxide film, 23 is a first interlayer insulating film, 24 is a second interlayer insulating film, 25 is a third interlayer insulating film, and 26 is a third metal. A wiring film 27 is a passivation film, and 28 is a groove formed in the scribe line region.
JP-A-6-77315

  The proposed technique separates the fragile interlayer insulating film between the element region and the scribe line region before dicing, so that cracks or the like generated in the scribe line region due to dicing are difficult to propagate to the element region. It has become a thing.

  However, since the interlayer insulating film remains in the scribe line region, cutting waste of the interlayer insulating film is generated by dicing, and the problem of contamination caused by this remains.

  Moreover, the interlayer insulating film is exposed on the surface at the portion where the interlayer insulating film is removed. For this reason, there is a problem that moisture or the like enters from the end face of the interlayer insulating film having a porous structure, leading to a decrease in reliability of the semiconductor element.

  Therefore, the problem to be solved by the present invention is to prevent chipping or peeling of the interlayer insulating film that occurs in the scribe line region during dicing, and to prevent the yield reduction due to damage or contamination to the semiconductor element due to this, and It is an object of the present invention to provide a technique for preventing exposure of an interlayer insulating film of a semiconductor element, suppressing moisture intrusion from an exposed portion, and preventing deterioration in reliability.

The above-mentioned problem is a semiconductor element assembly in which a plurality of semiconductor elements are configured.
The interlayer insulating film on the substrate provided in the semiconductor element is removed in the dicing portion between the semiconductor element and the adjacent semiconductor element,
The semiconductor element assembly is characterized in that the substrate surface exposed by the removal and the end surface of the interlayer insulating film are covered with a passivation film.

Also, an element region forming step of providing a plurality of semiconductor element element regions on the substrate;
A wiring film forming step of providing a wiring film after the element region forming step;
An interlayer insulating film forming step of providing an interlayer insulating film after the element region forming step;
An interlayer insulating film removing step for removing the interlayer insulating film in the dicing portion between the element region portion and the element region portion after the interlayer insulating film forming step;
A passivation film forming step of providing a passivation film after the interlayer insulating film removing step;
The semiconductor device manufacturing method includes a dicing step of dicing in a dicing portion where the interlayer insulating film is removed after the passivation film forming step.

Further, a semiconductor element manufactured by the above-described semiconductor element manufacturing method,
The semiconductor element is
The interlayer insulating film provided in the semiconductor element is removed at the edge of the semiconductor element,
The semiconductor element is characterized in that the substrate surface exposed by the removal and the end face of the interlayer insulating film are covered with a passivation film.

  In the present invention, the passivation film is made of a low moisture-permeable material such as SiO, SiN, SiC, or SiCN.

  According to the present invention, the interlayer insulating film is not exposed on the side surface of the chip after dicing, and the structure is covered with the passivation film having low moisture permeability. Therefore, the penetration of moisture from the chip side surface into the element region is effectively prevented.

  1 and 2 show an embodiment of the present invention. FIG. 1 is a cross-sectional explanatory view in the vicinity of a scribe line region in a stage before dicing, and FIG. 2 is a cross-sectional explanatory view in a stage after dicing.

  In each figure, 1 is a Si substrate, 2 is an element region formed by impurity diffusion, 3 is a barrier film, 4 is an interlayer insulating film having a porous structure, 5 is a cap film, 6 is a barrier film, and 7 is a porous structure. Interlayer insulating film, 8 is a cap film, 9 is a barrier film, 10 is a porous interlayer insulating film, 11 is a cap film, 12 is a barrier film, 13 is a passivation film, 14 is a metal wiring film constituting a bonding pad, etc. Reference numeral 15 denotes a passivation film made of a low moisture-permeable material such as SiO, SiN, SiC, or SiCN, and these are sequentially laminated.

  Incidentally, the configuration of the damascene wiring film structure as indicated by the reference numerals 1 to 15 has been known in the art, and thus detailed description thereof will be omitted.

  In the present invention, as shown in FIG. 1, in the stage before dicing, the barrier film 3, the interlayer insulating film 4, the cap film 5, the barrier film 6, the interlayer insulating film 7, One feature is that the cap film 8, the barrier film 9, the interlayer insulating film 10, the cap film 11, and the barrier film 12 are all removed. That is, after the wiring film and the insulating film are formed, these parts are removed in the scribe line region.

  Then, as shown in FIG. 1, a passivation film 15 is provided with a low moisture-permeable material such as SiO, SiN, SiC, or SiCN.

  After that, it is divided as shown in FIG.

  At the time of this division, when the occurrence rate of the chipping phenomenon of the interlayer insulating film is examined based on the distance L from the chip side surface to the element region (interlayer insulating film end), almost no chipping occurs when L ≧ 4 μm. It was. It has been found that dicing should be performed with a margin of 5 μm as L, more preferably 20 μm as L.

  When the semiconductor element is configured as described above, the interlayer insulating film or the like forming the multilayer wiring layer is not exposed in the cross section of the chip after dicing, and the entire element region including the wiring layer is transparent. It is in the form of being covered with a low-humidity passivation film. As a result, the chipping or peeling phenomenon of the interlayer insulating film during dicing is effectively suppressed, and moisture intrusion from the side surface of the chip is suppressed.

The cross-sectional explanatory drawing in the scribe line area | region vicinity which shows one Embodiment of this invention in the stage before dicing The cross-sectional explanatory drawing in the post-dicing stage, showing an embodiment of the present invention Schematic cross-sectional view of a conventional semiconductor device

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Si substrate 2 Element area | region 3, 6, 9, 12 Barrier film 4, 7, 10 Interlayer insulation film 5, 8, 11 Cap film 13, 15 Passivation film 14 Metal wiring film

Representative Katsumi Udaka

Claims (7)

In a semiconductor element assembly comprising a plurality of semiconductor elements,
The interlayer insulating film on the substrate provided in the semiconductor element is removed in the dicing portion between the semiconductor element and the adjacent semiconductor element,
A semiconductor element assembly, wherein a substrate surface exposed by the removal and an end surface of an interlayer insulating film are covered with a passivation film.   2. The semiconductor element assembly according to claim 1, wherein the passivation film is made of a low moisture-permeable material.   3. The semiconductor element assembly according to claim 1, wherein the passivation film is made of at least one selected from the group consisting of SiO, SiN, SiC and SiCN. An element region forming step of providing an element region portion of a plurality of semiconductor elements on a substrate;
A wiring film forming step of providing a wiring film after the element region forming step;
An interlayer insulating film forming step of providing an interlayer insulating film after the element region forming step;
An interlayer insulating film removing step for removing the interlayer insulating film in the dicing portion between the element region portion and the element region portion after the interlayer insulating film forming step;
A passivation film forming step of providing a passivation film after the interlayer insulating film removing step;
And a dicing step of dicing in a dicing portion from which the interlayer insulating film has been removed after the passivation film forming step.   5. The method of manufacturing a semiconductor element according to claim 4, wherein the passivation film is made of a low moisture-permeable material.   6. The method of manufacturing a semiconductor element according to claim 4, wherein the passivation film is made of at least one selected from the group consisting of SiO, SiN, SiC and SiCN. A semiconductor element manufactured by the method for manufacturing a semiconductor element according to any one of claims 4 to 6,
The semiconductor element is
The interlayer insulating film provided in the semiconductor element is removed at the edge of the semiconductor element,
A semiconductor element comprising a substrate surface exposed by the removal and an end face of an interlayer insulating film covered with a passivation film.

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