JP2010093273A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a missing article from being produced from a removal surface when parts corresponding to a dicing street among a layered structure of a low-permittivity film and wiring formed on a semiconductor wafer, and a passivation film are removed by irradiation of a laser beam. <P>SOLUTION: Four layers of low-permittivity films 4 and the same number of layers of wiring 5 are alternately formed on the upper surface of a semiconductor wafer 21, and a passivation film 7 formed of silicon nitride or the like is formed on top of it. Then, the passivation film 7, the low-permittivity film 4 and the wiring 5 in a region corresponding to dicing streets 23 are removed by irradiation of a laser beam to form grooves 26. Then, a protective film 9 formed of a polyimide resin or the like is formed on them including the insides of the grooves 26. Accordingly, since the removal surfaces by the irradiation of the laser beam of the passivation film 7, the low-permittivity film 4 and the wiring 5 are covered with the protective film 9, a missing article is reliably prevented from being produced from the removal surfaces in an early stage as much as possible. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  A CSP (Chip Size Package) having almost the same size (size & dimension) as a semiconductor substrate is known as a semiconductor device mounted on a small electronic device typified by a portable electronic device. Among CSPs, those that have been packaged in a wafer state and separated into individual semiconductor devices by dicing are also referred to as WLP (Wafer Level Package).

  In such a conventional semiconductor device, wiring is provided on the upper surface of the insulating film provided on the semiconductor substrate, a columnar electrode is provided on the upper surface of the connection pad portion of the wiring, and sealing is performed on the upper surface of the insulating film including the wiring. There is a film in which a top surface thereof is flush with a top surface of a columnar electrode, and a solder ball is disposed on the top surface of the columnar electrode (see, for example, Patent Document 1).

JP 2004-349461 A

  By the way, some semiconductor devices as described above are provided with an interlayer insulating film wiring laminated structure portion having a laminated structure of an interlayer insulating film and wiring between a semiconductor substrate and an insulating film. In this case, when the interval between the wirings of the interlayer insulating film wiring laminated structure portion is reduced with the miniaturization, the capacitance between the wirings is increased, and the delay of the signal transmitted through the wirings is increased.

In order to improve this point, as a material for the interlayer insulating film, a low-k material having a dielectric constant lower than that of silicon oxide 4.2 to 4.0 generally used as a material for the interlayer insulating film Low dielectric constant materials such as those mentioned are attracting attention. Examples of the low-k material include SiOC in which carbon (C) is doped into silicon oxide (SiO ₂ ), SiOCH containing H, and the like. Further, in order to further lower the dielectric constant, a porous (porous) low dielectric constant film containing air has been studied. By the way, in a method of manufacturing a semiconductor device having a low dielectric constant film wiring laminated structure portion composed of a laminated structure of a low dielectric constant film and wiring as an interlayer insulating film, a low dielectric constant film and wiring are formed on a semiconductor substrate in a wafer state. Then, an insulating film, an upper layer wiring, a columnar electrode, a sealing film, and a solder ball are formed thereon, and then separated into individual semiconductor devices by dicing.

  However, when the low dielectric constant film is cut with a dicing blade, the low dielectric constant film is fragile, and a large number of notches and breaks occur on the cut surface of the low dielectric constant film. Therefore, the portion of the low dielectric constant film formed on the semiconductor substrate in the wafer state corresponds to the dicing street together with the passivation film made of an inorganic material such as silicon nitride formed thereon, at a relatively early stage. Consideration of removal by irradiation has also been made.

  However, a semiconductor device in which a portion corresponding to a dicing street in a low dielectric constant film formed on a semiconductor substrate in a wafer state is removed together with a passivation film formed thereon by laser beam irradiation at a relatively early stage. In this manufacturing method, the adhesion strength between the low dielectric constant film and the passivation film on the surface to be removed by the laser beam irradiation is low, and a missing part may be generated from the surface to be removed. Such missing parts cause some trouble in the subsequent processes.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device, which can make it difficult for missing parts to be generated from a surface removed by laser beam irradiation such as a low dielectric constant film.

The invention according to claim 1 is provided with a low dielectric constant film wiring laminated structure in which a low dielectric constant film and wiring are laminated on a semiconductor substrate, a passivation film made of an inorganic material, and a protective film made of an organic material, In a method of manufacturing a semiconductor device in which an upper layer wiring connected to the wiring is provided on the protective film, a semiconductor wafer having a plurality of semiconductor device forming regions each including a necessary semiconductor device forming region and an unnecessary semiconductor device forming region A step of preparing the low dielectric constant film and the wiring on one surface and forming the passivation film thereon; and the passivation film in a region corresponding to at least a part of the dicing street Removing the wiring and the low dielectric constant film by irradiating a laser beam to form a groove; and a semiconductor required for the semiconductor wafer Forming the protective film in the groove of the unnecessary semiconductor device forming region of the semiconductor wafer and on the passivation film so that the removal surface in the groove of the device forming region is exposed, and on the protective film, The method includes a step of forming an upper layer wiring by connecting to the wiring, and a step of cutting at least the protective film and the semiconductor wafer along the dicing street.
According to a second aspect of the present invention, in the first aspect of the present invention, the unnecessary semiconductor device formation region of the semiconductor wafer has a region overlapping the dicing street.
According to a third aspect of the present invention, in the invention according to the second aspect of the present invention, in the prepared one, a part of the region overlapping the dicing street of the unnecessary semiconductor device forming region of the semiconductor wafer is not included in the low-level region. A dielectric film and the wiring are formed.
According to a fourth aspect of the present invention, in the invention according to the third aspect, in the prepared one, the region corresponding to the dicing street around the necessary semiconductor device formation region of the semiconductor wafer is provided with the low dielectric constant. The rate film is formed, but the wiring is not formed.
According to a fifth aspect of the present invention, in the invention of the fourth aspect, at least the passivation film, the wiring, and the low dielectric constant film in a region corresponding to a part of the dicing street are removed by laser beam irradiation. Forming the first groove by removing the passivation film in the region corresponding to the dicing street around the necessary semiconductor device formation region of the semiconductor wafer by photolithography, and forming the first groove. The low dielectric constant film exposed through the groove is removed by laser beam irradiation to form a second groove, and the passivation film, the wiring, and the other region corresponding to the dicing street are formed. The step of removing the low dielectric constant film by laser beam irradiation to form a groove. The one in which the features.
According to a sixth aspect of the invention, in the fifth aspect of the invention, the step of forming the protective film on the passivation film including at least a part of the groove is other than the first and second grooves. The protective film is formed on the passivation film including the inside of the groove.
According to a seventh aspect of the present invention, in the fifth aspect of the invention, the step of forming the protective film on the passivation film including at least a part of the groove includes the first and second grooves. In this step, the protective film is formed on the passivation film including all the grooves.
The invention according to claim 8 is the invention according to claim 1, wherein after forming the upper layer wiring, a columnar electrode is formed on a connection pad portion of the upper layer wiring, and a sealing film is formed around the columnar electrode. , Forming solder balls on the columnar electrodes, and cutting the sealing film, the protective film, and the semiconductor wafer along the dicing street.
According to a ninth aspect of the present invention, in the first aspect of the present invention, the low dielectric constant film includes a polysiloxane-based material having a Si-O bond and a Si-H bond, a Si-O bond, and a Si-CH _3. Any one of a polysiloxane-based material having a bond, carbon-added silicon oxide, and an organic polymer-based low-k material, or a fluorine-type silicon oxide, boron-added silicon oxide, or silicon oxide, which is a porous type It is characterized by including things.
The invention described in claim 10 is the invention described in claim 1, characterized in that the glass transition temperature of the low dielectric constant film is 400 ° C. or higher.

  According to the present invention, the passivation film, the wiring, and the low dielectric constant film in the region corresponding to at least a part of the dicing street are removed by laser beam irradiation to form a groove, and the passivation film includes at least a part of the groove. Since the protective film is formed on the surface, at least a part of the surface to be removed by the laser beam irradiation such as a low dielectric constant film is covered with the protective film, and therefore it is possible to prevent the removal surface from being easily lost. it can.

Sectional drawing of an example of the semiconductor device manufactured by the manufacturing method as 1st Embodiment of this invention. The top view shown in order to demonstrate the one part planar state of the semiconductor wafer for trial manufacture. The top view shown in order to demonstrate the dicing street with respect to the semiconductor wafer shown in FIG. 1A and 1B are cross-sectional views of what was initially prepared in manufacturing the semiconductor device shown in FIG. 1, wherein FIG. 1A is a cross-sectional view of a necessary semiconductor device formation region along a line IVA-IVA in FIG. Sectional drawing of the part of the unnecessary semiconductor device formation area in the part in alignment with the IVB-IVB line of 3. FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. FIG. 9 is a cross-sectional view of the process following FIG. 8. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. FIG. 15 is a sectional view of a step following FIG. 14. Sectional drawing of an example of the semiconductor device manufactured by the manufacturing method as 2nd Embodiment of this invention. FIG. 17 is a cross-sectional view of a predetermined process similar to FIG. 4 in manufacturing the semiconductor device shown in FIG. 16. FIG. 18 is a cross-sectional view of the process following FIG. 17. FIG. 19 is a cross-sectional view of the process following FIG. 18. FIG. 20 is a cross-sectional view of the process following FIG. 19. Sectional drawing of an example of the semiconductor device manufactured by the manufacturing method as 3rd Embodiment of this invention.

(First embodiment)
FIG. 1 shows a cross-sectional view of an example of a semiconductor device manufactured by the manufacturing method as the first embodiment of the present invention. This semiconductor device includes a silicon substrate (semiconductor substrate) 1. An integrated circuit (not shown) having a predetermined function is provided on the upper surface of the silicon substrate 1, and only two of them are shown in the periphery of the upper surface, but a large number of connection pads 2 made of aluminum metal or the like are actually shown. Are connected to the integrated circuit.

  On the upper surface of the silicon substrate 1, a low dielectric constant film wiring laminated structure 3 is provided. The low dielectric constant film wiring laminated structure 3 has a structure in which a plurality of layers, for example, four low dielectric constant films 4 and the same number of wirings 5 made of an aluminum metal or the like are alternately laminated. In this case, the wiring 5 of each layer is mutually connected between layers. One end of the lowermost wiring 5 is connected to the connection pad 2 through an opening 6 provided in the lower dielectric constant film 4. The connection pad portion 5 a of the uppermost layer wiring 5 is arranged in the periphery of the upper surface of the uppermost low dielectric constant film 4.

As a material of the low dielectric constant film 4, a polysiloxane-based material (HSQ: Hydrogen silsesquioxane, relative dielectric constant 3.0) having Si—O bond and Si—H bond, Si—O bond and Si—CH ₃ bond are used. Polysiloxane material (MSQ: Methyl silsesquioxane, relative dielectric constant 2.7 to 2.9), carbon doped silicon oxide (SiOC: Carbon dioxide, 2.7 to 2.9), organic polymer system Low-k materials and the like, and those having a relative dielectric constant of 3.0 or less and a glass transition temperature of 400 ° C. or more can be used.

  Examples of the organic polymer low-k material include “SiLK (relative permittivity: 2.6)” manufactured by Dow Chemical, “FLARE (relative permittivity: 2.8)” manufactured by Honeywell Electronic Materials, and the like. Here, the glass transition temperature being 400 ° C. or more is to sufficiently withstand the temperature in the manufacturing process described later. In addition, the porous type | mold of said each material can also be used.

  In addition to the above, the material of the low dielectric constant film 4 has a relative dielectric constant of greater than 3.0 in a normal state. Those having a transition temperature of 400 ° C. or higher can be used. For example, fluorine-doped silicon oxide (FSG: Fluorinated Silicate Glass, relative dielectric constant: 3.5 to 3.7), boron-doped silicon oxide (BSG: Boron-doped Silicate Glass, relative dielectric constant: 3.5), silicon oxide (ratio) The dielectric constant is 4.0 to 4.2).

  A passivation film 7 made of an inorganic material such as silicon nitride is provided on the upper surface of the uppermost low dielectric constant film 4 including the uppermost wiring 5. An opening 8 is provided in the passivation film 7 in a portion corresponding to the connection pad portion 5 a of the uppermost wiring 5. A protective film 9 made of an organic material such as polyimide resin is provided on the upper surface of the passivation film 7. An opening 10 is provided in the protective film 9 in a portion corresponding to the opening 8 of the passivation film 7.

  An upper wiring 11 is provided on the upper surface of the protective film 9. The upper layer wiring 11 has a two-layer structure of a base metal layer 12 made of copper or the like provided on the upper surface of the protective film 9 and an upper metal layer 13 made of copper provided on the upper surface of the base metal layer 12. . One end of the upper wiring 11 is connected to the connection pad 5 a of the uppermost wiring 5 through the openings 8 and 10 of the passivation film 7 and the protective film 9.

  A columnar electrode 14 made of copper is provided on the upper surface of the connection pad portion of the upper layer wiring 11. A sealing film 15 made of an organic material such as an epoxy resin is provided on the upper surface of the protective film 9 including the upper layer wiring 11 so that the upper surface is flush with the upper surface of the columnar electrode 14. A solder ball 16 is provided on the upper surface of the columnar electrode 14.

  Next, an example of a method for manufacturing this semiconductor device will be described. In this case, as shown in FIG. 2, a part of the rectangular region 22 of the silicon substrate in the wafer state (hereinafter referred to as the semiconductor wafer 21) has a plurality of plane shapes (square shape or rectangular shape) and different sizes. A necessary semiconductor device forming region 22a, an unnecessary semiconductor device forming region 22b, and other surplus regions 22c are formed.

  Various integrated circuits (not shown) are formed in the semiconductor device formation regions 22 a and 22 b on the upper surface of the semiconductor wafer 21. In this regard, the semiconductor wafer 21 is obtained by forming a large number of types of integrated circuits on a single semiconductor wafer 21 in order to manufacture a semiconductor device for small-scale production or trial manufacture. Only the semiconductor device is taken out. Here, the two necessary semiconductor device formation regions indicated by reference numeral 22a are regions that are required this time and are formed with integrated circuits to be taken out from the semiconductor wafer 21, and other unnecessary reference points indicated by reference numeral 22b. It is assumed that the semiconductor device forming region is a region where an integrated circuit that does not need to be taken out as an integrated circuit device is formed this time.

  Under such conditions, the two necessary semiconductor device formation regions indicated by reference numeral 22a are finally separated into pieces, and the unnecessary semiconductor device formation region and surplus region 22c indicated by reference numeral 22b are ignored. Will do. As a result, as indicated by a two-dot chain line in FIG. 3, the linear dicing street 23 is a region along each of the four sides of the two necessary semiconductor device forming regions 22a, and the unnecessary semiconductor device forming region 22b and the surplus region are formed. There is no problem even if it overlaps with 22c.

  When manufacturing the semiconductor device shown in FIG. 1 from the necessary semiconductor device formation region 22a of the semiconductor wafer 21, the one shown in FIGS. 4A and 4B is first prepared. In this case, FIG. 4A is a cross-sectional view of the necessary semiconductor device formation region 22a in the portion along the line IVA-IVA in FIG. 3, and FIG. 4B is the portion along the line IVB-IVB in FIG. It is sectional drawing of the part of the unnecessary semiconductor device formation area 22b in FIG.

  In this preparation, in both the necessary semiconductor device formation region 22a and the unnecessary semiconductor device formation region 22b, the connection pad 2, the low dielectric constant film 4 of each of the four layers, A wiring 5 and a passivation film 7 are formed, and a central portion of the connection pad portion 5 a of the uppermost wiring 5 is exposed through an opening 8 formed in the passivation film 7.

  Examples of the material for the low dielectric constant film 4 include those described above, including those having a porous type, those having a relative dielectric constant of 3.0 and a glass transition temperature of 400 ° C. or higher. Can do. In FIGS. 4A and 4B, an area indicated by reference numeral 23 is an area corresponding to dicing street.

  Here, in the necessary semiconductor device formation region 22 a in the portion along the line IVA-IVA in FIG. 3, the region along the four sides is a region corresponding to the dicing street 23. In the unnecessary semiconductor device forming region 22b along the IVB-IVB line in FIG. 3, only the region along the right side corresponds to the dicing street 23, but the left side and the upper side are the dicing street. 23 overlaps with the area.

  Therefore, the connection pad 2 and the wiring 5 are disposed inside the dicing street 23 in the necessary semiconductor device formation region 22a shown in FIG. On the other hand, in the unnecessary semiconductor device formation region 22b shown in FIG. 4B, the right connection pad 2 is arranged inside the dicing street 23, but the left connection pad 2 is outside the dicing street 23 ( The wiring 5 is partly overlapped with the dicing street 23.

  4A and 4B, the region corresponding to the dicing street 23 along the four sides of the necessary semiconductor device formation region 22a is next prepared as shown in FIG. 5A. A first groove 24 is formed in the passivation film 7 by using a photolithography method. In this case, as shown in FIG. 5B, such a groove is not formed in the passivation film 7 in the unnecessary semiconductor device formation region 22b.

  Next, as shown in FIG. 6A, in the necessary semiconductor device formation region 22a, the first groove 24 (that is, the dicing street 23) of the passivation film 7 is dealt with by laser processing with laser beam irradiation. A second groove 25 is formed in the four-layer low dielectric constant film 4 in the region. In this state, the upper surface of the semiconductor wafer 21 on the dicing street 23 is exposed through the first and second grooves 24 and 25. Further, the four layers of the low dielectric constant film 4 and the passivation film 7 laminated on the semiconductor wafer 21 are separated by the first and second grooves 24 and 25, whereby the low dielectric constant film wiring laminate shown in FIG. The structure part 3 is formed.

  Further, as shown in FIG. 6B, the passivation film 7 on the dicing street 23 and the four layers of the low dielectric constant film 4 are formed on the dicing street 23 by laser processing that irradiates a laser beam in the unnecessary semiconductor device formation region 22b. A groove 26 is formed. In this case, in the unnecessary semiconductor device formation region 22b, a part of the wiring 5 overlaps with the dicing street 23, so the wiring 5 in the overlapping part is removed. In this state, the upper surface of the semiconductor wafer 21 on the dicing street 23 is exposed through the groove 26.

  Here, when the second groove 25 and the groove 26 are processed by laser beam irradiation, when the upper surface of the semiconductor wafer 21 is irradiated with the laser beam, the upper surface of the semiconductor wafer 21 melts and jumps up from the semiconductor wafer 21. Since it falls on the semiconductor wafer 21, the bottom surfaces of the second groove 25 and the groove 26 are uneven.

  By the way, in the part of the unnecessary semiconductor device formation region 22b, the passivation film 7, the low dielectric constant film 4 and the wiring 5 are removed by irradiation with a laser beam in a part on the dicing street 23 to form the groove 26. Therefore, these removal surfaces are exposed. In this case, the adhesion strength between the low dielectric constant film 4 and the passivation film 7 and the wiring 5 is low, and a missing part may be generated from the removal surface. In the remaining portion on the dicing street 23, for example, as shown on the right side of FIG. 6B, the removal surface of the passivation film 7 and the low dielectric constant film 4 is exposed, and a missing part may be generated from the removal surface. is there.

  On the other hand, in the necessary semiconductor device formation region 22a, on the dicing street 23 along the four sides, the first groove 24 is formed in the passivation film 7 by the photolithography method, and then the four layers are formed by laser beam irradiation. Since only the dielectric constant film 4 is removed to form the second groove 25, the adhesion strength between the removed surfaces of the four layers of the low dielectric constant film 4 is higher than the adhesion strength between the different materials. Loss is relatively less likely to occur from the removal surface.

  Therefore, next, as shown in FIGS. 7A and 7B, the top surface exposed through the opening 8 of the passivation film 7 in the necessary semiconductor device formation region 22a by screen printing, spin coating, or the like. Passivation including the upper surface of the connection pad portion 5a of the upper wiring 5, the upper surface of the semiconductor wafer 21 exposed through the first and second grooves 24 and 25, and the upper surface of the semiconductor wafer 21 exposed through the groove 26. A protective film 9 made of an organic material such as polyimide resin is formed on the upper surface of the film 7.

  Next, as shown in FIG. 8A, in the portion of the necessary semiconductor device formation region 22a, the protective film 9 and the passivation film 7 in the portion corresponding to the connection pad portion 5a of the uppermost wiring 5 are formed by photolithography. And the grooves 27 are formed in the protective film 9, the passivation film 7 and the four layers of the low dielectric constant film 4 only on the dicing street 23 along the four sides of the necessary semiconductor device formation region 22a. As shown in FIG. 8B, for example, such a groove is not formed on the dicing street 23 in the other region.

  Therefore, in this state, as shown on the left side of FIG. 8B, for example, the removal surface of the passivation film 7, the low dielectric constant film 4 and the wiring 5 by the laser beam irradiation is covered with the protective film 9. It is possible to reliably prevent the occurrence of missing parts from the removal surface as early as possible. Further, for example, as shown on the right side of FIG. 8B, the removal surfaces of the passivation film 7 and the low dielectric constant film 4 that are irradiated with the laser beam are covered with the protective film 9, so that there are missing objects from the removal surfaces. It can be surely prevented from occurring as early as possible.

  On the other hand, as shown in FIG. 8A, in the portion of the necessary semiconductor device formation region 22a, the removal surface of the low dielectric constant film 4 by the laser beam irradiation is exposed through the groove 27, but as described above. Since missing parts are relatively unlikely to be generated from the removal surface, there is no major problem even if it remains as it is. In the step shown in FIG. 8A, only the openings 8 and 10 may be formed and the groove 27 may not be formed. In such a case, it is possible to reliably prevent the missing material from being generated from the removal surface.

  Next, as shown in FIGS. 9A and 9B, connection of the uppermost wiring 5 exposed through the openings 8 and 10 of the passivation film 7 and the protective film 9 in the necessary semiconductor device formation region 22a. A base metal layer 12 is formed on the entire upper surface of the protective film 9 including the upper surface of the pad portion 5 a and the upper surface of the semiconductor wafer 21 exposed through the groove 27. In this case, the base metal layer 12 may be only a copper layer formed by electroless plating, or may be only a copper layer formed by sputtering, and a thin film such as titanium formed by sputtering. A copper layer may be formed on the layer by sputtering.

  Next, a plating resist film 28 is patterned on the upper surface of the base metal layer 12. In this case, an opening 29 is formed in the plating resist film 28 in a portion corresponding to the upper metal layer 13 formation region of the necessary semiconductor device formation region 22a. Next, the upper metal layer 13 is formed on the upper surface of the base metal layer 12 in the opening 29 of the plating resist film 28 by performing electrolytic plating of copper using the base metal layer 12 as a plating current path. Next, the plating resist film 28 is peeled off.

  Next, as shown in FIGS. 10A and 10B, a plating resist film 30 is patterned on the upper surface of the base metal layer 12 including the upper metal layer 13. In this case, an opening 31 is formed in the plating resist film 30 in a portion corresponding to the connection pad portion (columnar electrode 14 formation region) of the upper metal layer 13. Next, a columnar electrode having a height of 50 to 150 μm is formed on the upper surface of the connection pad portion of the upper metal layer 13 in the opening 31 of the plating resist film 30 by performing electrolytic plating of copper using the base metal layer 12 as a plating current path. 14 is formed.

  Next, the plating resist film 30 is peeled off, and then unnecessary portions of the base metal layer 12 are removed by etching using the upper metal layer 13 as a mask. As shown in FIG. Only the base metal layer 12 remains. In this state, the upper layer wiring 11 having a two-layer structure is formed by the base metal layer 12 and the upper metal layer 13. Here, as shown in FIG. 11B, the unnecessary semiconductor device formation region 22b is an unnecessary region, and therefore, the upper layer wiring and the columnar electrode are not formed.

  Next, as shown in FIGS. 12A and 12B, the upper layer wiring 11 and the upper surface of the protective film 9 including the columnar electrode 14 and the groove 27 are exposed by a screen printing method, a spin coating method, or the like. A sealing film 15 made of an organic material such as epoxy resin is formed on the upper surface of the semiconductor wafer 21 so that the thickness thereof is greater than the height of the columnar electrode 14. Therefore, in this state, the upper surface of the columnar electrode 14 is covered with the sealing film 15.

  Next, the upper surface side of the sealing film 15 is appropriately ground to expose the upper surface of the columnar electrode 14 as shown in FIGS. 13A and 13B, and the exposed upper surface of the columnar electrode 14. The upper surface of the sealing film 15 containing is flattened. When planarizing the upper surface of the sealing film 15, the upper surface portion of the columnar electrode 14 may be ground together with the sealing film 15 by several μm to several tens of μm.

  Next, as shown in FIGS. 14A and 14B, solder balls 16 are formed on the upper surfaces of the columnar electrodes 14. Next, as shown in FIGS. 15A and 15B, the sealing film 15, the protective film 9, and the semiconductor wafer 21 are cut along the dicing street 23. Then, the semiconductor device shown in FIG. 1 is obtained from the necessary semiconductor device formation region 22a, and an unnecessary semiconductor device is obtained from the unnecessary semiconductor device formation region 22b.

(Second Embodiment)
FIG. 16 is a sectional view showing an example of a semiconductor device manufactured by the manufacturing method according to the second embodiment of the present invention. This semiconductor device is different from the semiconductor device shown in FIG. 1 in that a low dielectric constant film wiring laminated structure portion 3 is provided in a region excluding the peripheral portion outside the connection pad 2 on the upper surface of the silicon substrate 1. The sealing film 15 is provided on the upper surface of the peripheral part of the silicon substrate 1 outside the wiring laminated structure part 3.

  Next, an example of a method for manufacturing this semiconductor device will be described. In this case, after preparing what is shown in FIGS. 4A and 4B, as shown in FIG. 17A, on the dicing street 23 along the four sides of the necessary semiconductor device formation region 22a and on both sides thereof. A first groove 41 is formed in the passivation film 7 in the region by photolithography. Also in this case, as shown in FIG. 17B, such a groove is not formed in the passivation film 7 in the unnecessary semiconductor device formation region 22b.

  Next, as shown in FIG. 18A, in the necessary semiconductor device formation region 22a, the first groove 41 (that is, on the dicing street 23 and on both sides thereof) of the passivation film 7 is formed by laser processing with laser beam irradiation. The second groove 42 is formed in the four-layer low dielectric constant film 4 in the region corresponding to the region (1). In this state, the upper surface of the semiconductor wafer 21 on the dicing street 23 and on both sides thereof is exposed through the first and second grooves 41 and 42.

  Further, as shown in FIG. 18B, in the unnecessary semiconductor device formation region 22b, the low-dielectric of the passivation film 7 and the four layers in the dicing street 23 and the regions on both sides of the dicing street 23 by laser processing with laser beam irradiation. Grooves 43 are formed in the rate film 4. Also in this case, in the unnecessary semiconductor device formation region 22b, a part of the wiring 5 overlaps with the dicing street 23, so the wiring 5 in the overlapping part is removed. In this state, the upper surface of the semiconductor wafer 21 on the dicing street 23 and the regions on both sides thereof is exposed through the grooves 43.

  Next, as shown in FIGS. 19A and 19B, the uppermost layer exposed through the opening 8 of the passivation film 7 in the required semiconductor device formation region 22a by screen printing, spin coating, or the like. The passivation film 7 includes the upper surface of the connection pad portion 5 a of the wiring 5, the upper surface of the semiconductor wafer 21 exposed through the first and second grooves 41 and 42, and the upper surface of the semiconductor wafer 21 exposed through the groove 43. A protective film 9 made of an organic material such as polyimide resin is formed on the upper surface of the substrate.

  Next, as shown in FIG. 20A, the protective film 9 and the passivation film 7 in the portion corresponding to the connection pad portion 5a of the uppermost wiring 5 are formed by photolithography in the necessary semiconductor device formation region 22a. Are formed on the dicing street 23 along the four sides of the necessary semiconductor device formation region 22a and only in the regions on both sides thereof, the passivation film 7 and the four layers of low dielectric constant films. A groove 44 is formed in the groove 4, and such a groove is not formed on the dicing street 23 in the other region and regions on both sides thereof, as shown in FIG. 20B, for example.

  Thereafter, through the same steps as in the first embodiment, the semiconductor device shown in FIG. 16 is obtained from the portion of the necessary semiconductor device formation region 22a, and an unnecessary semiconductor is formed from the portion of the unnecessary semiconductor device formation region 22b. A device is obtained. By the way, in the semiconductor device shown in FIG. 16 obtained from the necessary semiconductor device formation region 22a, the low dielectric constant film wiring laminated structure portion 3 is provided in a region excluding the peripheral portion on the silicon substrate 1 in a completed state. Since the side surfaces of the low dielectric constant film wiring multilayer structure portion 3, the passivation film 7 and the protective film 9 are covered with the sealing film 15, the low dielectric constant film wiring multilayer structure portion 3 is difficult to peel off from the silicon substrate 1. It can be.

(Third embodiment)
FIG. 21 is a sectional view showing an example of a semiconductor device manufactured by the manufacturing method according to the third embodiment of the present invention. This semiconductor device is different from the semiconductor device shown in FIG. 1 in that a low dielectric constant film wiring laminated structure portion 3 is provided in a region excluding the peripheral portion outside the connection pad 2 on the upper surface of the silicon substrate 1. The protective film 9 is provided on the upper surface of the peripheral part of the silicon substrate 1 outside the wiring laminated structure part 3.

  Next, an example of a method for manufacturing this semiconductor device will be described. In this case, in the step shown in FIG. 20, only the openings 8 and 10 are formed, and the groove 44 is not formed. Thereafter, through the same steps as in the first embodiment, the semiconductor device shown in FIG. 21 is obtained from the necessary semiconductor device formation region 22a, and an unnecessary semiconductor device is obtained from the unnecessary semiconductor device formation region 22b. A device is obtained. By the way, in the semiconductor device shown in FIG. 21 obtained from the necessary semiconductor device forming region 22a, the low dielectric constant film wiring laminated structure portion 3 is provided in a region excluding the peripheral portion on the silicon substrate 1 in a completed state. Since the side surfaces of the low dielectric constant film wiring laminated structure 3 and the passivation film 7 are covered with the protective film 9, the low dielectric constant film wiring laminated structure 3 can be made difficult to peel off from the silicon substrate 1. .

(Other embodiments)
Each of the above embodiments has a structure in which the upper layer wiring 11 is formed on the protective film 9 and the columnar electrode 14 is formed on the connection pad portion of the upper layer wiring 11. The present invention can also be applied to a structure in which an upper layer wiring composed only of a connection pad portion is formed and an external connection bump electrode such as a solder ball 16 is formed on the upper layer wiring composed only of the connection pad portion.

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Connection pad 3 Low dielectric constant film wiring laminated structure part 4 Low dielectric constant film 5 Wiring 7 Passivation film 9 Protective film 11 Upper layer wiring 14 Columnar electrode 15 Sealing film 16 Solder ball 21 Semiconductor wafer 22a Necessary semiconductor device formation region 22b Unnecessary semiconductor device formation region 22c Surplus region 23 Dicing street

Claims (10)

Low dielectric constant film wiring laminated structure in which a low dielectric constant film and wiring are laminated on a semiconductor substrate, a passivation film made of an inorganic material, and a protective film made of an organic material are provided and connected to the wiring on the protective film In the manufacturing method of the semiconductor device provided with the upper layer wiring to be performed,
The low dielectric constant film and the wiring are stacked on one surface of a semiconductor wafer having a plurality of semiconductor device forming regions each including a necessary semiconductor device forming region and an unnecessary semiconductor device forming region, and the passivation is formed thereon. Preparing a film-formed one;
Removing the passivation film, the wiring, and the low dielectric constant film in a region corresponding to at least a part of the dicing street by laser beam irradiation to form a groove;
Forming the protective film in the groove of the unnecessary semiconductor device formation region of the semiconductor wafer and on the passivation film so that the removal surface in the groove of the semiconductor device formation region of the semiconductor wafer is exposed;
Forming the upper wiring on the protective film by connecting to the wiring;
Cutting at least the protective film and the semiconductor wafer along the dicing street;
A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein an unnecessary semiconductor device formation region of the semiconductor wafer has a region overlapping with the dicing street.   The low dielectric constant film and the wiring are formed in a part of the prepared semiconductor device where the unnecessary semiconductor device formation region of the semiconductor wafer overlaps the dicing street. A method for manufacturing a semiconductor device.   In the invention according to claim 3, in the prepared one, the low dielectric constant film is formed in a region corresponding to the dicing street around the necessary semiconductor device formation region of the semiconductor wafer. A method of manufacturing a semiconductor device, wherein the wiring is not formed.   In the invention according to claim 4, the step of forming the groove by removing the passivation film, the wiring and the low dielectric constant film in a region corresponding to at least a part of the dicing street by irradiation with a laser beam, The passivation film in a region corresponding to the dicing street around the necessary semiconductor device formation region of the semiconductor wafer is removed by photolithography to form a first groove, and the first groove exposed through the first groove The low dielectric constant film is removed by irradiation with a laser beam to form a second groove, and the passivation film, the wiring, and the low dielectric constant film in a region corresponding to the other dicing street are removed from the laser beam. A semiconductor device characterized in that it is a step of forming a groove by removal by irradiation Manufacturing method.   6. The passivation film according to claim 5, wherein the step of forming the protective film on the passivation film including at least a part of the groove includes the inside of the groove other than the first and second grooves. A method for manufacturing a semiconductor device, comprising the step of forming the protective film thereon.   6. The method of claim 5, wherein the step of forming the protective film on the passivation film including at least a part of the groove includes all of the grooves including the first and second grooves. A method for manufacturing a semiconductor device, comprising forming the protective film on a passivation film.   In the invention according to claim 1, after forming the upper layer wiring, a columnar electrode is formed on a connection pad portion of the upper layer wiring, a sealing film is formed around the columnar electrode, and the columnar electrode is formed on the columnar electrode. A method of manufacturing a semiconductor device, comprising: forming a solder ball, and cutting the sealing film, the protective film, and the semiconductor wafer along the dicing street. _{3. The} low dielectric constant film according to claim 1, wherein the low dielectric constant film is a polysiloxane material having Si—O bonds and Si—H bonds, a polysiloxane material having Si—O bonds and Si—CH ₃ bonds, and carbon. A semiconductor characterized in that it contains any one of added silicon oxide and organic polymer-based low-k materials, or includes fluorine-type silicon oxide, boron-added silicon oxide, and silicon oxide that is porous. Device manufacturing method.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the low dielectric constant film has a glass transition temperature of 400 ° C. or higher.

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