JP2008140829A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent penetration of water into the inside of a semiconductor device (chip) while increase in the chip area is controlled. <P>SOLUTION: A multilayer wiring structure is formed by laminating multiple layers of interlayer insulating films 15, 17, and 19 using a Low-k film having a porous structure to assure low dielectricity and laser dicing is conducted along a scribe line until the front surface of a semiconductor substrate 11 is exposed. After a side wall protection film 22 is formed with a film having more difficulty in water penetration than the Low-k film, a side surface of the semiconductor device is protected with the side wall protection film 22 by exposing a metal pad 20 by etching back the side wall protection film 22, leaving this side wall protection film 22 formed at the side surface of the semiconductor device. As explained above, the need for forming a seal ring in the surrounding of a circuit forming region of the semiconductor device is eliminated to reduce the size of the semiconductor chip by controlling penetration of water from the side surface of the semiconductor device with the side wall protection film 22. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a multilayer wiring structure using an insulating film such as an interlayer insulating film, and a manufacturing method thereof.

  A plurality of semiconductor devices arranged on a semiconductor substrate in a wafer state are separated by a scribe line region arranged in a lattice shape. Then, after passing through the first half manufacturing process, it is diced along the scribe line and divided into individual semiconductor devices (chips). In such a case, in a mechanical cutting method such as blade dicing, a circuit forming portion around the scribe line may be partially cracked, chipped, or peeled off due to mechanical impact during dicing.

  In particular, a Low-k film having a low relative dielectric constant has recently been used as an interlayer insulating film of a semiconductor device in order to increase the device speed. However, since the Low-k film generally has a porous structure in order to ensure low dielectric properties, its mechanical strength and adhesion are significantly weaker than those of a silicon oxide film. For this reason, mechanical cutting such as normal blade dicing significantly causes film peeling and cracks.

  For the problem of film peeling or cracking in the Low-k film due to mechanical impact during blade dicing, there is a method of using laser dicing without mechanical impact for dividing into individual chips. Has been taken.

  The method of dividing into chips by laser dicing includes a method of melting and cutting by irradiating a laser beam focusing point on the surface of a semiconductor device formed on a semiconductor substrate (wafer), and a laser beam focusing point. There is a method of cleaving a semiconductor substrate after forming a modified region by multiphoton absorption by aligning the position with the inside of the semiconductor substrate (wafer). In the former method in which the laser beam condensing point is aligned with the surface of the semiconductor device and melted and cut, by adjusting the laser beam output, for example, only the portion of the semiconductor device is cut without cutting the semiconductor substrate. The cutting depth can be set. The laser dicing technique is disclosed in Japanese Patent Application Laid-Open No. 2004-111428 (Patent Document 1) and the like.

  As described above, by using the laser dicing, film peeling and cracking of the interlayer insulating film of the semiconductor device are suppressed, but moisture intrusion from the side surface of the semiconductor device exposed by the dicing is suppressed. I can't. In order to suppress moisture intrusion from the side surface of the cut semiconductor device, a seal ring is provided between the circuit formation portion and the scribe line (dicing region portion) of the semiconductor device so as to surround the circuit formation portion. Has been done. This seal ring is formed at the same time as the wiring or the connection hole wiring when forming the wiring of the circuit forming portion and when forming the connection hole wiring for connecting the upper wiring and the lower wiring. In addition, by suppressing moisture permeation with the seal ring, deterioration of device characteristics and corrosion of metal wiring are suppressed. The seal ring technology is disclosed in Japanese Unexamined Patent Application Publication No. 2000-232104 (Patent Document 2) and Japanese Unexamined Patent Application Publication No. 2004-297022 (Patent Document 3).

  13 shows a longitudinal section of the semiconductor device provided with the seal ring, and FIG. 14 shows a plan view of the semiconductor device provided with the seal ring. 13 and 14, a plurality of insulating films 2 to 5 made of the Low-k film or the like are formed on the semiconductor substrate 1, and the elements and wirings 6 and 7 formed on the insulating films 2 to 5, A circuit forming region 9 in which a connection hole wiring 8 for connecting the upper wiring 6 and the lower wiring 7 is formed, and a seal ring region 10 formed so as to surround the circuit forming region 9 are provided. . The width of the seal ring region 10 is generally about 20 μm including the space between the seal ring region 10 and the circuit forming region 9.

However, in the conventional semiconductor devices disclosed in Patent Document 2 and Patent Document 3, the porous Low-k film exposed to the side surface of the semiconductor device after the chip is divided by dicing or the Low As shown in FIG. 13 and FIG. 14, moisture entering from the close contact surface (interface) of the k film is prevented by the seal ring region 10 formed so as to surround the circuit forming region 9. The area of the semiconductor device (chip) increases by the area of the seal ring region 10, which is one of the factors that hinder the reduction of the chip area.
JP 2004-111428 A Japanese Patent Application Laid-Open No. 2000-232104 JP 2004-297022 A

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device capable of preventing the intrusion of moisture into the inside while suppressing an increase in the area of the semiconductor device (chip) and a method for manufacturing the same.

In order to solve the above problems, a semiconductor device of the present invention is
A base interlayer film is formed on a semiconductor substrate on which an electronic element including a transistor element is formed,
On the base interlayer film, one or more interlayer insulating films having metal wiring are laminated and formed.
On the surface of the interlayer insulating film located in the uppermost layer among the stacked interlayer insulating films, a takeout electrode for taking out a signal from the metal wiring is formed,
A surface protective film formed so as to cover the entire region except the extraction electrode on the surface of the uppermost interlayer insulating film;
And a sidewall protective film formed so as to cover the entire sidewall of the base interlayer film and the interlayer insulating film.

  According to the above configuration, the extraction electrode on the surface of the uppermost interlayer insulating film in the base interlayer film formed on the semiconductor substrate on which the electronic element is formed and one or more interlayer insulating films having metal wirings The entire region except for is covered with a surface protective film, and the entire side walls of the base interlayer film and the interlayer insulating film are covered with a side wall protective film. Therefore, after being divided into individual semiconductor devices (chips) by laser dicing, moisture and the like are prevented from entering from the surface of the uppermost interlayer insulating film and the underlying interlayer film and the sidewalls of the interlayer insulating film. be able to.

  In other words, according to the present invention, it is not necessary to provide a seal ring for suppressing moisture ingress so as to surround the circuit forming portion between the circuit forming portion and the scribe line of the semiconductor device, and the semiconductor is correspondingly removed. It is possible to reduce the chip area of the device. Furthermore, by reducing the chip area, the number of semiconductor devices (chips) that can be formed on a semiconductor substrate (wafer) of the same area can be increased, and the efficiency of semiconductor device creation can be increased.

The semiconductor device of the present invention is
A base interlayer film is formed on a semiconductor substrate on which an electronic element including a transistor element is formed,
On the base interlayer film, one or more interlayer insulating films having metal wiring are laminated and formed.
On the surface of the interlayer insulating film located in the uppermost layer among the stacked interlayer insulating films, a takeout electrode for taking out a signal from the metal wiring is formed,
Side edges of the semiconductor substrate protrude outward from the side walls of the base interlayer film and the interlayer insulating film,
A surface protective film formed so as to cover the entire region except the extraction electrode on the surface of the uppermost interlayer insulating film;
A side wall protective film that covers the entire side wall of the base interlayer film and the interlayer insulating film, and that covers a protruding portion that protrudes outward from the side wall of the base interlayer film and the interlayer insulating film of the semiconductor substrate; It is characterized by having.

  According to the above configuration, the extraction electrode on the surface of the uppermost interlayer insulating film in the base interlayer film formed on the semiconductor substrate on which the electronic element is formed and one or more interlayer insulating films having metal wirings The entire region except for is covered with a surface protective film, and the entire side walls of the base interlayer film and the interlayer insulating film are covered with a side wall protective film. Therefore, after being divided into individual semiconductor devices (chips) by laser dicing, moisture and the like are prevented from entering from the surface of the uppermost interlayer insulating film and the underlying interlayer film and the sidewalls of the interlayer insulating film. be able to. Further, the sidewall protective film covers a protruding portion that protrudes outward from the sidewalls of the base interlayer film and the interlayer insulating film in the semiconductor substrate. Accordingly, it is possible to prevent moisture or the like from entering through the gap between the lower end of the sidewall protective film and the protruding portion of the semiconductor substrate.

  That is, according to the present invention, there is no need to provide a seal ring for suppressing moisture ingress so as to surround the circuit forming portion between the circuit forming portion and the scribe line of the semiconductor device, and the semiconductor is correspondingly provided. It is possible to reduce the chip area of the device. Furthermore, by reducing the chip area, the number of semiconductor devices (chips) that can be formed on a semiconductor substrate (wafer) of the same area can be increased, and the efficiency of semiconductor device creation can be increased.

In the semiconductor device of one embodiment,
The sidewall protective film is any one of a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, an aluminum nitride film, and a titanium oxide film.

  According to this embodiment, as the sidewall protective film, a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, an aluminum nitride film, and a titanium oxide film in which moisture is less likely to penetrate than the base interlayer film and the interlayer insulating film A film formed of any one of the above is used. Therefore, it is possible to reliably suppress moisture from entering from the side walls of the plurality of interlayer insulating films.

In the semiconductor device of one embodiment,
The total number of interlayer insulating films is less than 10 layers,
The sidewall protective film has a thickness of 20 nm or more and 200 nm or less.

  According to this embodiment, the entire side wall of the interlayer insulating film laminated with less than 10 layers is covered with the side wall protective film having a thickness of 20 nm or more and 200 nm or less. Therefore, it is possible to reliably suppress moisture from entering from the side walls of the plurality of interlayer insulating films.

In the semiconductor device of one embodiment,
The total number of the interlayer insulating films is at least 10 layers and 18 layers or less,
The thickness of the sidewall protective film is 200 nm or more and 900 nm or less.

  According to this embodiment, the entire side wall of the interlayer insulating film stacked with the number of layers of 10 layers or more and 18 layers or less is covered with the sidewall protection film having a thickness of 200 nm or more and 900 nm or less. Yes. Therefore, it is possible to reliably suppress moisture from entering from the side walls of the plurality of interlayer insulating films.

In the semiconductor device of one embodiment,
The length of the portion of the side wall protective film that covers the protruding portion of the semiconductor substrate from the side wall surface of the base interlayer film and each interlayer insulating film is not less than 5 μm and not more than 55 μm.

  According to this embodiment, the length of the side wall protective film covering the protruding portion of the semiconductor substrate from the side wall surface of the base interlayer film and each interlayer insulating film is 5 μm to 25 μm. Therefore, it is possible to reliably prevent moisture or the like that tends to enter from the gap between the lower end of the sidewall protective film and the protruding portion of the semiconductor substrate.

In the semiconductor device of one embodiment,
The inside of the side wall protective film is constituted only by a circuit formation region.

  According to this embodiment, the inside of the side wall protective film is configured only by the circuit formation region, and the seal ring is not configured. Therefore, it is possible to reduce the chip area of the semiconductor device by the amount that the seal ring is not formed. Even in such a case, moisture or the like from the side walls of the base interlayer film and the plurality of interlayer insulating films to the inside by the side wall protective film covering the entire side walls of the base interlayer film and the plurality of interlayer insulating films. Infiltration is suppressed.

In the semiconductor device of one embodiment,
At least one of the plurality of interlayer insulating films is composed of a low dielectric constant film.

  According to this embodiment, in order to speed up the device, at least one of the plurality of interlayer insulating films is composed of a low dielectric constant film having a porous structure such as a Low-k film. . Even in such a case, since the entire sidewalls of the plurality of interlayer insulating films are covered with the sidewall protective film, intrusion of moisture and the like from the sidewalls of the plurality of interlayer insulating films is suppressed.

In the semiconductor device of one embodiment,
The low dielectric constant film is a film having a porous structure.

  According to this embodiment, at least one of the plurality of interlayer insulating films is composed of a low dielectric constant film having a porous structure. Even in such a case, since the entire sidewalls of the plurality of interlayer insulating films are covered with the sidewall protective film, intrusion of moisture and the like from the sidewalls of the plurality of interlayer insulating films is suppressed.

In addition, a method for manufacturing a semiconductor device according to the present invention includes:
The low dielectric constant film is a film having a porous structure.

A step of laminating and forming one or more interlayer insulating films containing wiring on a semiconductor substrate;
Forming a wiring electrode pad for taking out a signal from the wiring on the surface of the uppermost interlayer insulating film;
Depositing a surface protective film on the surface of the uppermost interlayer insulating film;
Removing the surface protective film on the wiring electrode pad in the uppermost interlayer insulating film;
A first dicing step of removing the interlayer insulating film formed on the semiconductor substrate along the scribe line to a predetermined width;
Forming a sidewall protective film covering the entire surface including the exposed sidewall of the interlayer insulating film and the surface of the wiring electrode pad;
Removing the sidewall protective film by anisotropic etch back until the surface of the wiring electrode pad is exposed;
And a second dicing step of completely cutting up to the semiconductor substrate along the scribe line and dividing it into chips.

  According to the above configuration, the entire sidewall of the interlayer insulating film exposed by the first dicing process for removing the interlayer insulating film to a predetermined width along the scribe line is covered with the sidewall protective film. Accordingly, it is possible to prevent moisture and the like from entering from the side walls of the plurality of interlayer insulating films after being divided into chips by the second dicing step.

  In other words, according to the present invention, it is not necessary to provide a seal ring for suppressing moisture ingress so as to surround the circuit forming portion between the circuit forming portion and the scribe line of the semiconductor device, and the semiconductor is correspondingly removed. It is possible to reduce the chip area of the device. Furthermore, by reducing the chip area, the number of semiconductor devices (chips) that can be formed on a semiconductor substrate (wafer) of the same area can be increased, and the efficiency of semiconductor device creation can be increased.

In addition, a method for manufacturing a semiconductor device according to the present invention includes:
A step of laminating and forming one or more interlayer insulating films containing wiring on a semiconductor substrate;
Forming a wiring electrode pad for taking out a signal from the wiring on the surface of the uppermost interlayer insulating film;
Depositing a surface protective film on the surface of the uppermost interlayer insulating film;
A first dicing step of removing the interlayer insulating film formed on the semiconductor substrate along the scribe line to a predetermined width;
Forming a sidewall protective film covering the entire surface including the exposed sidewall of the interlayer insulating film;
Forming a mask having an opening only on the wiring electrode pad on the sidewall protective film;
Removing the surface protective film and the sidewall protective film by anisotropic etch back using the mask until the surface of the wiring electrode pad is exposed;
And a second dicing step of completely cutting up to the semiconductor substrate along the scribe line and dividing it into chips.

  According to the above configuration, the entire sidewall of the interlayer insulating film exposed by the first dicing process for removing the interlayer insulating film to a predetermined width along the scribe line is covered with the sidewall protective film. Accordingly, it is possible to prevent moisture and the like from entering from the side walls of the plurality of interlayer insulating films after being divided into chips by the second dicing step. Further, the sidewall protective film covers a protruding portion that protrudes outward from the sidewalls of the base interlayer film and the plurality of interlayer insulating films in the semiconductor substrate. Therefore, it is possible to prevent moisture and the like from entering through a gap between the lower end of the sidewall protective film and the protruding portion of the semiconductor substrate.

  In other words, according to the present invention, it is not necessary to provide a seal ring for suppressing moisture ingress so as to surround the circuit forming portion between the circuit forming portion and the scribe line of the semiconductor device, and the semiconductor is correspondingly removed. It is possible to reduce the chip area of the device. Furthermore, by reducing the chip area, the number of semiconductor devices (chips) that can be formed on a semiconductor substrate (wafer) of the same area can be increased, and the efficiency of semiconductor device creation can be increased.

In the manufacturing method of the semiconductor device of one embodiment,
The first dicing step is performed by laser dicing.

  According to this embodiment, since the first dicing step is performed by laser dicing, peeling of the interlayer insulating film, cracks, and the like are prevented. Further, the entire sidewall of the interlayer insulating film exposed by the laser dicing is covered with a sidewall protective film. Accordingly, it is possible to suppress moisture and the like from entering from the side walls of the plurality of interlayer insulating films when divided into chips by the second dicing step.

In the manufacturing method of the semiconductor device of one embodiment,
The second dicing step is performed by laser dicing.

  According to this embodiment, since the second dicing step of completely cutting up to the semiconductor substrate and dividing it into chips is performed by laser dicing, peeling or cracking of the semiconductor substrate to be cut is prevented. .

In the manufacturing method of the semiconductor device of one embodiment,
The second dicing step is performed by blade dicing.

  According to this embodiment, since the second dicing step of completely cutting up to the semiconductor substrate and dividing it into chips is performed by blade dicing, the manufacturing cost in the second dicing step can be reduced.

In the manufacturing method of the semiconductor device of one embodiment,
The removal of the interlayer insulating film in the first dicing step is performed up to the surface of the semiconductor substrate.

  According to this embodiment, the interlayer insulating film of all layers is removed by the first dicing process. Therefore, the sidewalls of the interlayer insulating film of all layers are covered with the sidewall protective film.

In the manufacturing method of the semiconductor device of one embodiment,
The removal of the interlayer insulating film in the first dicing step is performed until a part of the semiconductor substrate is removed.

  According to this embodiment, the interlayer insulating film of all layers is completely removed by the first dicing process. Therefore, the sidewalls of the interlayer insulating film of all layers are covered with the sidewall protective film.

In the manufacturing method of the semiconductor device of one embodiment,
The sidewall protective film is formed by a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, an aluminum nitride film, or a titanium oxide film.

  According to this embodiment, as the sidewall protective film, a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, an aluminum nitride film, and a titanium oxide film in which moisture is less likely to penetrate than the base interlayer film and the interlayer insulating film A film formed of any one of the above is used. Therefore, it is possible to reliably suppress moisture from entering from the side walls of the plurality of interlayer insulating films.

In the manufacturing method of the semiconductor device of one embodiment,
At least one of the interlayer insulating films is formed of a low dielectric constant film.

  According to this embodiment, in order to increase the speed of the device, at least one of the interlayer insulating films is composed of a low dielectric constant film having a porous structure such as a Low-k film. Even in this case, since the entire side wall of the interlayer insulating film is covered with the side wall protective film, intrusion of moisture and the like from the side walls of the plurality of interlayer insulating films is suppressed.

In the manufacturing method of the semiconductor device of one embodiment,
The scribe line width in the second dicing step is 20 μm or more and 60 μm or less,
The kerf width in the second dicing step is 10 μm or more and 40 μm or less,
As a result of the second dicing step, the lower end portion of the sidewall protective film covering the sidewall of the interlayer insulating film has a length of 5 μm or more and 25 μm or less from the sidewall of the interlayer insulating film. It extends in the present direction and covers the surface of the semiconductor substrate.

  According to this embodiment, the length of the extending portion in the extending direction of the surface of the semiconductor substrate from the sidewall of the interlayer insulating film at the lower end portion of the sidewall protective film covering the sidewall of the interlayer insulating film Is 5 μm or more and 25 μm or less. Therefore, the surface of the semiconductor substrate can be sufficiently covered with the side wall protective film even in consideration of misalignment during scribing.

In the manufacturing method of the semiconductor device of one embodiment,
The scribe line width in the second dicing step is 60 μm or more and 120 μm or less,
The kerf width in the second dicing step is 10 μm or more and 40 μm or less,
As a result of the second dicing step, the lower end portion of the sidewall protective film covering the sidewall of the interlayer insulating film has a length of 10 μm or more and 55 μm or less from the sidewall of the interlayer insulating film. It extends in the present direction and covers the surface of the semiconductor substrate.

  According to this embodiment, the length of the extending portion in the extending direction of the surface of the semiconductor substrate from the sidewall of the interlayer insulating film at the lower end portion of the sidewall protective film covering the sidewall of the interlayer insulating film Is 10 μm or more and 55 μm or less. Therefore, the surface of the semiconductor substrate can be sufficiently covered with the side wall protective film even in consideration of misalignment during scribing.

  As is clear from the above, the semiconductor device of the present invention is the uppermost layer in the base interlayer film formed on the semiconductor substrate on which the electronic element is formed and one or more interlayer insulating films having metal wiring. The entire area of the surface of the interlayer insulating film except for the extraction electrode is covered with a surface protective film, and the entire side wall of the base interlayer film and the interlayer insulating film is covered with a side wall protective film. After being divided into (chips), it is possible to prevent moisture and the like from entering from the surface of the uppermost interlayer insulating film, the base interlayer film, and the side walls of the interlayer insulating film.

  Therefore, according to the present invention, there is no need to provide a seal ring for preventing moisture permeation so as to surround the circuit forming portion between the circuit forming portion and the scribe line of the semiconductor device, and the semiconductor is correspondingly provided. The chip area of the device can be reduced. Furthermore, by reducing the chip area, the number of semiconductor devices (chips) that can be formed on a semiconductor substrate (wafer) of the same area can be increased, and the efficiency of semiconductor device creation can be increased.

  According to another aspect of the present invention, there is provided a semiconductor device comprising: a base interlayer film formed on a semiconductor substrate on which an electronic element is formed; and one or more interlayer insulating films having a metal wiring. In addition to covering the entire area except the take-out electrode with a surface protective film, and covering the entire side wall of the base interlayer film and the interlayer insulating film with a side wall protective film, it is divided into individual semiconductor devices (chips) by laser dicing. Then, it is possible to prevent moisture and the like from entering from the surface of the uppermost interlayer insulating film, the base interlayer film, and the sidewalls of the interlayer insulating film. Furthermore, since the side wall protective film covers the protruding portion that protrudes outward from the side walls of the base interlayer film and the interlayer insulating film in the semiconductor substrate, the lower end of the side wall protective film and the semiconductor substrate It is possible to prevent moisture and the like from entering through the gap with the protrusion.

  Therefore, according to the present invention, there is no need to provide a seal ring for suppressing moisture ingress so as to surround the circuit forming portion between the circuit forming portion and the scribe line of the semiconductor device, and the semiconductor is correspondingly provided. The chip area of the device can be reduced. Furthermore, by reducing the chip area, the number of semiconductor devices (chips) that can be formed on a semiconductor substrate (wafer) of the same area can be increased, and the efficiency of semiconductor device creation can be increased.

  In the method of manufacturing a semiconductor device according to the present invention, the entire sidewall of the interlayer insulating film exposed by the first dicing process for removing the interlayer insulating film to a predetermined width along the scribe line is covered with the sidewall protective film. It is possible to prevent moisture and the like from entering from the side walls of the plurality of interlayer insulating films after being divided into chips by the two dicing process.

  In other words, according to the present invention, it is not necessary to provide a seal ring for suppressing moisture ingress so as to surround the circuit forming portion between the circuit forming portion and the scribe line of the semiconductor device, and the semiconductor is correspondingly removed. The chip area of the device can be reduced. Furthermore, by reducing the chip area, the number of semiconductor devices (chips) that can be formed on a semiconductor substrate (wafer) of the same area can be increased, and the efficiency of semiconductor device creation can be increased.

  In the method of manufacturing a semiconductor device according to the present invention, the entire sidewall of the interlayer insulating film exposed by the first dicing process for removing the interlayer insulating film to a predetermined width along the scribe line is covered with the sidewall protective film. It is possible to prevent moisture and the like from entering from the side walls of the plurality of interlayer insulating films after being divided into chips by the two dicing process.

  Furthermore, since the side wall protective film covers the protruding portion that protrudes outward from the side walls of the base interlayer film and the interlayer insulating film in the semiconductor substrate, the lower end of the side wall protective film and the semiconductor substrate It is possible to prevent moisture or the like from entering through the gap with the protrusion.

  In other words, according to the present invention, it is not necessary to provide a seal ring for suppressing moisture ingress so as to surround the circuit forming portion between the circuit forming portion and the scribe line of the semiconductor device, and the semiconductor is correspondingly removed. It is possible to reduce the chip area of the device. Furthermore, by reducing the chip area, the number of semiconductor devices (chips) that can be formed on a semiconductor substrate (wafer) of the same area can be increased, and the efficiency of semiconductor device creation can be increased.

  Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

First Embodiment FIG. 1 is a longitudinal sectional view of a semiconductor device according to the present embodiment. As shown in FIG. 1, in this semiconductor device, various elements such as a transistor element 12 are formed on a semiconductor substrate 11, and a base interlayer film 13 is formed so as to cover the various elements including the transistor element 12. A first interlayer insulating film 15 having a metal wiring 14 such as a copper wiring is formed on the film 13. Further, a second interlayer insulating film 17 having a metal wiring 16 such as a copper wiring formed on the surface is formed on the first interlayer insulating film 15, and further a copper is formed on the surface of the second interlayer insulating film 17. A third interlayer insulating film 19 in which metal wiring 18 such as wiring is formed is formed. Further, on the surface of the third interlayer insulating film 19, a metal pad 20 for taking out an electric signal from the metal wiring 16 formed on the surface of the lower second interlayer insulating film 17 is formed.

  A surface protective film 21 is formed on the entire surface of the third interlayer insulating film 19 except for the portion of the metal pad 20. A sidewall protective film 22 is formed on the sidewalls of the base interlayer film 13, the first interlayer insulating film 15, the second interlayer insulating film 17, and the third interlayer insulating film 19. Thus, the surface of the third interlayer insulating film 19 and the side walls of the base interlayer film 13, the first interlayer insulating film 15, the second interlayer insulating film 17, and the third interlayer insulating film 19 are protected by the protective film. Is configured.

  In the present embodiment, the interlayer insulating film is formed in four layers, but the number of layers of the interlayer insulating film is not particularly limited, and it is a single layer or 4 layers or more and 12 layers or less. Any number of layers can be stacked.

  2A to 5J show cross sections of the semiconductor device in each step of the method for manufacturing the semiconductor device according to the present embodiment. Hereinafter, the method for manufacturing the semiconductor device will be described with reference to FIGS. 2 (a) to 5 (j).

First, as shown in FIG. 2A, after various elements such as a transistor element 12 are formed on a semiconductor substrate 11, a base interlayer film 13 is laminated on the whole. The underlying interlayer film 13 includes a BPSG (Boro-phosphosilicate glass) film, a PSG (Phospho Silicate glass) film, a plasma SiN film, a CVD (Chemical Vapor Deposition) SiO ₂ film, It is formed of a single layer of SiC film or SiCC film which is a Low-k film. Alternatively, these layers are formed.

  Next, for example, after the contact element 23 connected to the source electrode and the drain electrode of the transistor element 12 is formed on the base interlayer film 13, the first interlayer insulating film 15 is formed on the entire surface of the base interlayer film 13. The first interlayer insulating film 15 in the present embodiment is the Low-k film and has a laminated structure of a SiC film and a SiCC film. However, the SiOC film is formed by a CVD method with a film thickness of 10 nm to 70 nm, and then the SiOC film is formed with a film thickness of 150 nm to 500 nm by the CVD method.

  Next, in order to form a wiring trench, the SiOC film constituting the first interlayer insulating film 15 is removed by dry etching using a photoresist (not shown) as a mask, and then the photoresist is removed by ashing. . Further, the SiC film forming a part of the first interlayer insulating film 15 exposed by removing the SiOC film is removed by dry etching. Thus, the first wiring groove 24 is formed as shown in FIG. At this time, the photoresist mask may be removed after the SiC film is removed.

  Next, after forming a copper diffusion preventing metal film and a copper seed layer on the entire surface, copper is formed on the entire surface by electrolytic plating. Then, the metal film other than the inside of the first wiring groove 24 is removed by a chemical mechanical polishing method (CMP method), and the first wiring groove 24 is formed into a copper diffusion preventing metal film and a copper as shown in FIG. The metal wiring 14 is formed. However, in FIG. 2C, the copper diffusion preventing metal film and the copper seed layer are not shown. In this embodiment, tantalum nitride is formed by sputtering as the copper diffusion preventing metal film. Similarly, a copper seed layer is also formed by sputtering.

  Next, as shown in FIG. 3D, a second interlayer insulating film 17 is formed on the entire surface. In the present embodiment, the second interlayer insulating film 17 is the Low-k film and has a stacked structure of an SiC film and an SiC film. However, the SiOC film is formed with a thickness of 10 nm to 70 nm by the CVD method, and then the SiOC film is formed with a thickness of 500 nm to 1000 nm by the CVD method.

  Next, as shown in FIG. 3E, via holes 25a are formed in the second interlayer insulating film 17 by dry etching using a photoresist (not shown) as a mask, and then the photoresist is removed by ashing. At this time, the SiC film remains at the bottom of the via hole 25a, and becomes an etching stop film at the time of wiring groove etching performed later.

  Next, a second wiring groove 26 is formed in the second interlayer insulating film 17 by dry etching using a photoresist (not shown) for forming the second wiring groove as a mask, and then the photoresist is removed by ashing. Thereafter, the SiC film present at the bottom of the via hole 25a is removed by dry etching. At this time, the photoresist mask may be removed after removing the SiC film. FIG. 3E shows a state after the via hole 25a and the second wiring groove 26 are formed.

  Next, after forming a copper diffusion preventing metal film and a copper seed layer on the entire surface, copper is formed on the entire surface by electrolytic plating to fill the via hole 25a and the second wiring groove 26 with copper. Then, the metal film other than the inside of the second wiring trench 26 is removed by the CMP method, and the metal wiring 16 and the via hole connection wiring 25 are formed as shown in FIG. However, the metal film for preventing copper diffusion and the copper seed layer are not shown in FIG. By repeating the above steps, as shown in FIG. 4G, the third interlayer insulating film 19 in which the metal wiring 18 made of copper, the metal pad 20 and the via hole connection wiring 27 are formed is formed. Furthermore, it is possible to form a multilayer wiring structure having four or more layers.

  In the present embodiment, after forming the metal wiring 18, the metal pad 20, and the via hole connection wiring 27 on the uppermost interlayer insulating film (third interlayer insulating film 19), the surface protective film 21 is formed on the entire surface, As shown in FIG. 4 (g), a surface protective film 21 formed on the surface of the metal pad 20 is formed by known photolithography and RIE (Reactive Ion Etching: reactive ions) in order to make electrical connection with the outside. The pad surface exposed portion is obtained by providing an opening 28 in the upper part of the metal pad 20 by removing by etching.

  Next, laser dicing is performed along the scribe lines separating the respective semiconductor devices, and the semiconductor device is separated (diced) until the surface of the semiconductor substrate 11 is exposed as shown in FIG. In that case, a part of the semiconductor substrate 11 may be diced by the laser dicing.

Next, in order to protect each insulating film (the Low-k film) on the side surface of the semiconductor device exposed by the laser dicing, as shown in FIG. 4 (i), moisture permeates more than the Low-k film. The sidewall protective film 22 is formed as a whole with a difficult film. In the present embodiment, a SiON film or a SiN film is formed as the sidewall protective film 22 by a plasma CVD method. The thickness of the sidewall protective film 22 is about 20 nm to 200 nm. However, when the number of interlayer insulating films is 10 or more and 18 or less, the thickness of the sidewall protective film 22 needs to be about 200 nm to 900 nm. Here, the film thickness of the sidewall protective film 22 described above is a measured value at a flat location on the flat semiconductor substrate 11 or on the insulating film formed on the semiconductor substrate 11. Note that Al ₂ O ₃ , AlN, or TiO ₂ may be used as the sidewall protective film 22.

  After that, the side wall protective film 22 is etched back by RIE, so that the side wall protective film 22 formed in the opening 28 of the surface protective film 21 disappears as shown in FIG. Is exposed. In this case, as shown in FIG. 5J, the sidewall protective film 22 formed on the side surface of the semiconductor device does not disappear due to anisotropic etching by RIE. Further, the sidewall protective film 22 remains on the sidewall of the opening 28 in the surface protective film 21.

  Thereafter, a dicing sheet (not shown) is attached to the back surface of the semiconductor substrate (wafer) 11, and the semiconductor substrate 11 is cut to a width narrower than the dicing width shown in FIG. 4 (h) by blade dicing or laser dicing. Then, it is divided into individual semiconductor devices (chips).

  Through the above steps, as shown in FIG. 1, a semiconductor device in which the side wall is protected by the side wall protective film 22 can be formed.

  As described above, in the present embodiment, the interlayer insulating films 15, 17, and 19 using the low-k film having a porous structure in order to ensure low dielectric properties are stacked in multiple layers to obtain a multilayer wiring structure. When dicing is performed along scribe lines separating the respective semiconductor devices, laser dicing is first performed until the surface of the semiconductor substrate 11 is exposed. Then, after the sidewall protective film 22 is formed on the whole with a film that is less permeable to moisture than the Low-k film, the sidewall protective film 22 is etched back by RIE, whereby the metal pad 20 formed on the surface is removed. The side wall protective film 22 formed on the side surface of the semiconductor device is left exposed, and the side surface of the semiconductor device is protected by the side wall protective film 22.

  Therefore, the penetration of moisture from the side surface of the semiconductor device can be suppressed by the sidewall protective film 22. That is, according to this embodiment, it is not necessary to form a seal ring around the circuit formation region of the semiconductor device, and the semiconductor chip can be reduced in size.

  As an example, when the seal ring is eliminated from a 5 mm square semiconductor chip, the chip area can be reduced by about 2%.

  In the above embodiment, the side surface of the semiconductor device is protected by the side wall protective film 22 to eliminate the formation of a seal ring. However, as a matter of course, the present invention may be applied to a semiconductor device in which a seal ring is formed if the chip area is sufficient. FIG. 6 is a longitudinal sectional view of a semiconductor device when the present invention is applied to a semiconductor device in which a seal ring is formed. In FIG. 6, a seal ring region 30 is disposed around the circuit forming region 29, and the side surface of the semiconductor device on the outer side is covered with a sidewall protective film 22.

  In this case, the seal ring can be formed simultaneously with the formation of the metal wirings 14 and 16 in the circuit formation region and the via hole connection wiring 25 that connects the upper wiring 16 and the lower wiring 14. Therefore, it is not necessary to newly add a seal ring manufacturing procedure to the semiconductor device manufacturing procedure, and the presence or absence of the seal ring does not affect the semiconductor device manufacturing procedure. Therefore, it can be said that the presence or absence of the seal ring is determined by the design.

Second Embodiment In the first embodiment, the lower end of the sidewall protective film 22 is only in contact with the upper surface of the semiconductor substrate 11. Therefore, when there is a gap between the lower end of the sidewall protective film 22 and the upper surface of the semiconductor substrate 11, water or the like may enter from this gap. In the present embodiment, the side wall protective film 22 also covers the protruding portion that protrudes outward from the side wall of the base interlayer film 13 and the first interlayer insulating film 15 to the third interlayer insulating film 19 in the semiconductor substrate 11. Thus, water or the like is prevented from entering from the gap between the lower end of the sidewall protective film 22 and the upper surface of the semiconductor substrate 11.

  FIG. 7 is a longitudinal sectional view of the semiconductor device according to the present embodiment. However, the same members as those in the semiconductor device according to the first embodiment shown in FIG. As shown in FIG. 7, in this semiconductor device, various elements such as a transistor element 12 are formed on a semiconductor substrate 11, and a base interlayer film 13 is formed so as to cover the various elements including the transistor element 12. A first interlayer insulating film 15 having a metal wiring 14 such as a copper wiring is formed on the film 13. Further, a second interlayer insulating film 17 having a metal wiring 16 such as a copper wiring formed on the surface is formed on the first interlayer insulating film 15, and further a copper is formed on the surface of the second interlayer insulating film 17. A third interlayer insulating film 19 in which metal wiring 18 such as wiring is formed is formed. Further, on the surface of the third interlayer insulating film 19, a metal pad 20 for taking out an electric signal from the metal wiring 16 formed on the surface of the lower second interlayer insulating film 17 is formed.

  Then, the entire region of the surface of the third interlayer insulating film 19 excluding the metal pad 20, the entire side walls of the underlying interlayer film 13 and the interlayer insulating films 15, 17, 19, and the semiconductor substrate in the scribe line region A sidewall protective film 22 is formed so as to cover the semiconductor substrate 11 adjacent to the underlying interlayer film 13 on the substrate 11. Thus, the surfaces of the semiconductor substrate 11 and the third interlayer insulating film 19 adjacent to the base interlayer film 13 and the side walls of the base interlayer film 13, the first interlayer insulating film 15, the second interlayer insulating film 17, and the third interlayer insulating film 19. Constitutes a semiconductor device protected by a protective film.

  In the present embodiment, the interlayer insulating film is formed in four layers, but the number of layers of the interlayer insulating film is not particularly limited, and it is a single layer or 4 layers or more and 12 layers or less. Any number of layers can be stacked.

  8A to 11J show cross sections of the semiconductor device in each step of the method for manufacturing the semiconductor device in the present embodiment. Hereinafter, the method for manufacturing the semiconductor device will be described with reference to FIGS. 8 (a) to 11 (j).

First, as shown in FIG. 8A, after various elements such as the transistor element 12 are formed on the semiconductor substrate 11, a base interlayer film 13 is laminated on the whole. The underlying interlayer film 13 is formed as a single layer of a BPSG film, a PSG film, a plasma SiN film, a CVD SiO ₂ film, or the Low-k film (SiC film or SiOC film). Alternatively, these layers are formed.

  Next, for example, after the contact element 23 connected to the source electrode and the drain electrode of the transistor element 12 is formed on the base interlayer film 13, the first interlayer insulating film 15 is formed on the entire surface of the base interlayer film 13. The first interlayer insulating film 15 in the present embodiment is the Low-k film and has a laminated structure of a SiC film and a SiCC film. However, the SiOC film is formed by a CVD method with a film thickness of 10 nm to 70 nm, and then the SiOC film is formed with a film thickness of 150 nm to 500 nm by the CVD method.

  Next, in order to form a wiring trench, the SiOC film constituting the first interlayer insulating film 15 is removed by dry etching using a photoresist (not shown) as a mask, and then the photoresist is removed by ashing. . Further, the SiC film forming a part of the first interlayer insulating film 15 exposed by removing the SiOC film is removed by dry etching. In this way, the first wiring groove 24 is formed as shown in FIG. At this time, the photoresist mask may be removed after the SiC film is removed.

  Next, after forming a copper diffusion preventing metal film and a copper seed layer on the entire surface, copper is formed on the entire surface by electrolytic plating. Then, the metal film other than the inside of the first wiring groove 24 is removed by a chemical mechanical polishing method (CMP method), and the first wiring groove 24 is formed into a copper diffusion preventing metal film and a copper as shown in FIG. The metal wiring 14 is formed. However, in FIG. 8C, the copper diffusion preventing metal film and the copper seed layer are not shown. In this embodiment, tantalum nitride is formed by sputtering as the copper diffusion preventing metal film. Similarly, a copper seed layer is also formed by sputtering.

  Next, as shown in FIG. 9D, a second interlayer insulating film 17 is formed on the entire surface. In the present embodiment, the second interlayer insulating film 17 is the Low-k film and has a stacked structure of an SiC film and an SiC film. However, the SiOC film is formed with a thickness of 10 nm to 70 nm by the CVD method, and then the SiOC film is formed with a thickness of 500 nm to 1000 nm by the CVD method.

  Next, as shown in FIG. 9E, via holes 25a are formed in the second interlayer insulating film 17 by dry etching using a photoresist (not shown) as a mask, and then the photoresist is removed by ashing. At this time, the SiC film remains at the bottom of the via hole 25a, and becomes an etching stop film at the time of wiring groove etching performed later.

  Next, a second wiring groove 26 is formed in the second interlayer insulating film 17 by dry etching using a photoresist (not shown) for forming the second wiring groove as a mask, and then the photoresist is removed by ashing. Thereafter, the SiC film present at the bottom of the via hole 25a is removed by dry etching. At this time, the photoresist mask may be removed after removing the SiC film. FIG. 9E shows a state after the via hole 25a and the second wiring groove 26 are formed.

  Next, after forming a copper diffusion preventing metal film and a copper seed layer on the entire surface, copper is formed on the entire surface by electrolytic plating to fill the via hole 25a and the second wiring groove 26 with copper. Then, the metal film other than the inside of the second wiring trench 26 is removed by the CMP method, and the metal wiring 16 and the via hole connection wiring 25 are formed as shown in FIG. However, in FIG. 9 (f), the copper diffusion preventing metal film and the copper seed layer are not shown. By repeating the above steps, as shown in FIG. 10G, the third interlayer insulating film 19 in which the metal wiring 18 made of copper, the metal pad 20 and the via hole connection wiring 27 are formed is formed. Furthermore, it is possible to form a multilayer wiring structure having four or more layers.

  In this embodiment, after forming the metal wiring 18, the metal pad 20, and the via hole connection wiring 27 on the uppermost interlayer insulating film (third interlayer insulating film 19), as shown in FIG. A surface protective film 21 is formed on the entire surface.

  Next, laser dicing is performed along the scribe lines separating the respective semiconductor devices, and the semiconductor device is separated (diced) until the surface of the semiconductor substrate 11 is exposed as shown in FIG. In that case, a part of the semiconductor substrate 11 may be diced by the laser dicing.

Next, in order to protect each insulating film (the Low-k film) on the side surface of the semiconductor device exposed by the laser dicing, as shown in FIG. 10 (i), moisture penetrates more than the Low-k film. The sidewall protective film 22 is formed as a whole with a difficult film. In the present embodiment, a SiON film or a SiN film is formed as the sidewall protective film 22 by a plasma CVD method. The thickness of the sidewall protective film 22 is about 20 nm to 200 nm. However, when the number of interlayer insulating films is 10 or more and 18 or less, the thickness of the sidewall protective film 22 needs to be about 200 nm to 900 nm. Here, the film thickness of the sidewall protective film 22 described above is a measured value at a flat location on the flat semiconductor substrate 11 or on the insulating film formed on the semiconductor substrate 11. Note that Al ₂ O ₃ , AlN, or TiO ₂ may be used as the sidewall protective film 22.

  After that, as shown in FIG. 11 (j), the surface protection film 21 and the sidewall protection film 22 formed on the surface of the metal pad 20 are formed by known photolithography and RIE, in order to make electrical connection with the outside. And an opening 31 is provided in the upper part of the metal pad 20. Thus, the surface of the metal pad 20 is exposed.

  In the scribe line, the resist used at the time of photolithography when the opening 31 is provided on the metal pad 20 may be left or removed. FIG. 11 (j) shows the case where the resist (not shown) is left, and the side wall protective film 22 at the bottom of the scribe line is not removed during RIE for exposing the surface of the metal pad 20. However, even if the resist is removed and there is no resist in the scribe line, only the surface protective film 21 and the side wall protective film 22 on the metal pad 20 and the side wall protective film 22 at the bottom of the scribe line are removed. In addition, the sidewall protective film 22 formed on the side surface of the semiconductor device does not disappear due to anisotropic etching by RIE, as shown in FIG.

  Thereafter, a dicing sheet (not shown) is attached to the back surface of the semiconductor substrate (wafer) 11, and the semiconductor substrate 11 is cut to a width smaller than the dicing width shown in FIG. 10 (h) by blade dicing or laser dicing. Then, it is divided into individual semiconductor devices (chips).

  Through the above steps, as shown in FIG. 7, a semiconductor device in which the side wall is protected by the side wall protective film 22 can be formed. Further, as shown in FIG. 7, on the side surface of each divided semiconductor device, the side wall protective film 22 is formed on the side walls of the base interlayer film 13 and the first interlayer insulating film 15 to the third interlayer insulating film 19 in the semiconductor substrate 11. It also covers the protruding part that protrudes outward.

Table 1 shows the protruding length L of the portion where the sidewall protective film 22 covers the protruding portion of the semiconductor substrate 11.

  In Table 1, “a” is the scribe line width (μm), and “b” is the kerf width (μm). According to Table 1, the scribe line width on the semiconductor device is 20 μm to 120 μm, and the kerf width when scribing the scribe line using conventional plate dicing using water or wetless laser dicing (cutting) ( It can be seen that when the cutting width is 10 μm to 40 μm, the protruding length L is formed in the range of approximately 5 μm to 55 μm.

In addition, when the kerf width (cutting width) is 10 μm to 40 μm, the scribe line width is classified into “20 μm to 60 μm” and “60 μm to 120 μm” as follows:
(A) When the scribe line width is 20 μm to 60 μm From Table 1, the dimension of the protrusion length L shown in FIG. 7 is 5 μm to 25 μm. When the deviation from the center of the scribe position when scribing (cutting) the scribe line is about 4 μm, the actually obtained protrusion length L is approximately 1 μm to 29 μm.
(B) When the scribe line width is 60 μm to 120 μm From Table 1, the dimension of the protrusion length L shown in FIG. 7 is 10 μm to 55 μm. When the deviation of the scribe position from the center when scribing (cutting) the scribe line is about 4 μm, the actually obtained protrusion length L is approximately 6 μm to 59 μm.

  As described above, in the present embodiment, the interlayer insulating films 15, 17, and 19 using the low-k film having a porous structure in order to ensure low dielectric properties are stacked in multiple layers to obtain a multilayer wiring structure. When dicing is performed along scribe lines separating the respective semiconductor devices, laser dicing is first performed until the surface of the semiconductor substrate 11 is exposed. Then, after forming a sidewall protective film 22 entirely with a film that is less permeable to moisture than the Low-k film, the sidewall protective film 22 is exposed to the metal pad 20 formed on the surface by photolithography and RIE. At the same time, the side wall protective film 22 formed on the side surface of the semiconductor device is left and the side surface of the semiconductor device is protected by the side wall protective film 22.

  Further, the side wall protective film 22 covers the protruding portion that protrudes outward from the side walls of the base interlayer film 13 and the first interlayer insulating film 15 to the third interlayer insulating film 19 in the semiconductor substrate 11. . Therefore, moisture or the like entering the inside through the gap between the lower end of the sidewall protective film 22 and the protruding portion of the semiconductor substrate 11 can be prevented.

  As described above, the intrusion of moisture from the side surface of the semiconductor device can be more completely suppressed by the sidewall protective film 22. That is, according to this embodiment, it is not necessary to form a seal ring around the circuit formation region of the semiconductor device, and the semiconductor chip can be reduced in size.

  FIG. 12 is a longitudinal sectional view of a semiconductor device when the present invention is applied to a semiconductor device in which a seal ring is formed. In FIG. 12, a seal ring region 33 is disposed around the circuit forming region 32, and the side surface of the semiconductor device on the outer side is covered with the sidewall protective film 22.

  Here, according to the present embodiment, the sidewall protective film 22 prevents moisture from entering from the side surface of the semiconductor device. Therefore, the formation of a seal ring for the semiconductor device (chip) can be eliminated, and a semiconductor device without a seal ring can be formed as shown in FIG.

  The seal ring can be formed simultaneously with the formation of the metal wirings 14 and 16 in the circuit formation region and the via hole connection wiring 25 that connects the upper wiring 16 and the lower wiring 14. Therefore, it is not necessary to newly add a seal ring manufacturing procedure to the semiconductor device manufacturing procedure, and the presence or absence of the seal ring does not affect the semiconductor device manufacturing procedure. Therefore, it can be said that the presence or absence of the seal ring is determined by the design.

  As shown in FIG. 7, when the seal ring is eliminated, the semiconductor device (chip) can be reduced. As an example, when the seal ring is removed from a 5 mm square semiconductor chip, the chip area can be reduced by about 2%.

It is a longitudinal cross-sectional view which shows the structure in the semiconductor device of this invention. FIG. 2 is a longitudinal sectional view of the semiconductor device shown in FIG. 1 in the manufacturing process. FIG. 3 is a longitudinal sectional view in a different manufacturing process from FIG. 2. FIG. 4 is a longitudinal sectional view in a manufacturing process different from those in FIGS. 2 and 3. It is a longitudinal cross-sectional view in a manufacturing process different from FIGS. It is a longitudinal cross-sectional view at the time of applying the manufacturing method shown in FIGS. 2-5 to the semiconductor device in which the seal ring was formed. FIG. 2 is a longitudinal sectional view of a semiconductor device different from FIG. 1. FIG. 8 is a longitudinal sectional view in a manufacturing process of the semiconductor device shown in FIG. 7. It is a longitudinal cross-sectional view in a manufacturing process different from FIG. FIG. 10 is a longitudinal sectional view in a manufacturing process different from those in FIGS. 8 and 9. It is a longitudinal cross-sectional view in a manufacturing process different from FIGS. It is a longitudinal cross-sectional view at the time of applying the manufacturing method shown in FIGS. 8-11 to the semiconductor device in which the seal ring was formed. It is a longitudinal cross-sectional view of the conventional semiconductor device provided with the seal ring. It is a figure which shows the plane of the semiconductor device shown in FIG.

Explanation of symbols

11 ... Semiconductor substrate,
12 ... transistor element,
13: Base interlayer film,
14 ... Metal wiring,
15 ... 1st interlayer insulation film,
16 ... metal wiring,
17 ... second interlayer insulating film,
18 ... metal wiring,
19: Third interlayer insulating film,
20 ... Metal pad,
21 ... Surface protective film,
22: Side wall protective film,
23 ... contact element,
24. First wiring groove,
25, 27 ... via hole connection wiring,
25a ... via hole,
26 ... second wiring groove,
28, 31 ... opening,
29, 32 ... circuit formation region,
30, 33 ... seal ring region.

Claims (20)

A base interlayer film is formed on a semiconductor substrate on which an electronic element including a transistor element is formed,
On the base interlayer film, one or more interlayer insulating films having metal wiring are laminated and formed.
On the surface of the interlayer insulating film located in the uppermost layer among the stacked interlayer insulating films, a takeout electrode for taking out a signal from the metal wiring is formed,
A surface protective film formed so as to cover the entire region except the extraction electrode on the surface of the uppermost interlayer insulating film;
A semiconductor device comprising: the base interlayer film; and a sidewall protective film formed over the entire sidewall of the interlayer insulating film. A base interlayer film is formed on a semiconductor substrate on which an electronic element including a transistor element is formed,
On the base interlayer film, one or more interlayer insulating films having metal wiring are laminated and formed.
On the surface of the interlayer insulating film located in the uppermost layer among the stacked interlayer insulating films, a takeout electrode for taking out a signal from the metal wiring is formed,
Side edges of the semiconductor substrate protrude outward from the side walls of the base interlayer film and the interlayer insulating film,
A surface protective film formed so as to cover the entire region except the extraction electrode on the surface of the uppermost interlayer insulating film;
A side wall protective film that covers the entire side wall of the base interlayer film and the interlayer insulating film, and that covers a protruding portion that protrudes outward from the side wall of the base interlayer film and the interlayer insulating film of the semiconductor substrate; A semiconductor device comprising: In the semiconductor device according to claim 1 or 2,
The semiconductor device according to claim 1, wherein the sidewall protective film is any one of a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, an aluminum nitride film, and a titanium oxide film. In the semiconductor device according to claim 1 or 2,
The total number of interlayer insulating films is less than 10 layers,
2. The semiconductor device according to claim 1, wherein the sidewall protective film has a thickness of 20 nm to 200 nm. In the semiconductor device according to claim 1 or 2,
The total number of the interlayer insulating films is at least 10 layers and 18 layers or less,
2. The semiconductor device according to claim 1, wherein the sidewall protective film has a thickness of 200 nm to 900 nm. The semiconductor device according to claim 2,
The length of the portion of the side wall protective film covering the protruding portion of the semiconductor substrate from the side wall surface of the base interlayer film and each interlayer insulating film is not less than 5 μm and not more than 55 μm apparatus. In the semiconductor device according to claim 1 or 2,
The inside of the said side wall protective film is comprised only by the circuit formation area | region, The semiconductor device characterized by the above-mentioned. In the semiconductor device according to claim 1 or 2,
At least one of the plurality of interlayer insulating films is formed of a low dielectric constant film. The semiconductor device according to claim 8,
The semiconductor device according to claim 1, wherein the low dielectric constant film is a film having a porous structure. A step of laminating and forming one or more interlayer insulating films containing wiring on a semiconductor substrate;
Forming a wiring electrode pad for taking out a signal from the wiring on the surface of the uppermost interlayer insulating film;
Depositing a surface protective film on the surface of the uppermost interlayer insulating film;
Removing the surface protective film on the wiring electrode pad in the uppermost interlayer insulating film;
A first dicing step of removing the interlayer insulating film formed on the semiconductor substrate along the scribe line to a predetermined width;
Forming a sidewall protective film covering the entire surface including the exposed sidewall of the interlayer insulating film and the surface of the wiring electrode pad;
Removing the sidewall protective film by anisotropic etch back until the surface of the wiring electrode pad is exposed;
And a second dicing step of completely cutting the semiconductor substrate along the scribe line and dividing it into chips. A step of laminating and forming one or more interlayer insulating films containing wiring on a semiconductor substrate;
Forming a wiring electrode pad for taking out a signal from the wiring on the surface of the uppermost interlayer insulating film;
Depositing a surface protective film on the surface of the uppermost interlayer insulating film;
A first dicing step of removing the interlayer insulating film formed on the semiconductor substrate along the scribe line to a predetermined width;
Forming a sidewall protective film covering the entire surface including the exposed sidewall of the interlayer insulating film;
Forming a mask having an opening only on the wiring electrode pad on the sidewall protective film;
Removing the surface protective film and the sidewall protective film by anisotropic etch back using the mask until the surface of the wiring electrode pad is exposed;
And a second dicing step of completely cutting the semiconductor substrate along the scribe line and dividing it into chips. In the manufacturing method of the semiconductor device according to claim 10 or 11,
The semiconductor device manufacturing method, wherein the first dicing step is performed by laser dicing. In the manufacturing method of the semiconductor device according to claim 10 or 11,
The method of manufacturing a semiconductor device, wherein the second dicing step is performed by laser dicing. In the manufacturing method of the semiconductor device according to claim 10 or 11,
The method of manufacturing a semiconductor device, wherein the second dicing step is performed by blade dicing. In the manufacturing method of the semiconductor device according to claim 10 or 11,
The method of manufacturing a semiconductor device, wherein the removal of the interlayer insulating film in the first dicing step is performed up to the surface of the semiconductor substrate. In the manufacturing method of the semiconductor device according to claim 10 or 11,
The method for manufacturing a semiconductor device, wherein the removal of the interlayer insulating film in the first dicing step is performed until a part of the semiconductor substrate is removed. In the manufacturing method of the semiconductor device according to claim 10 or 11,
The method for manufacturing a semiconductor device is characterized in that the sidewall protective film is formed by a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, an aluminum nitride film, or a titanium oxide film. In the manufacturing method of the semiconductor device according to claim 10 or 11,
A method of manufacturing a semiconductor device, wherein at least one of the interlayer insulating films is formed of a low dielectric constant film. In the manufacturing method of the semiconductor device according to claim 11,
The scribe line width in the second dicing step is 20 μm or more and 60 μm or less,
The kerf width in the second dicing step is 10 μm or more and 40 μm or less,
As a result of the second dicing step, the lower end portion of the sidewall protective film covering the sidewall of the interlayer insulating film has a length of 5 μm or more and 25 μm or less from the sidewall of the interlayer insulating film. A method for manufacturing a semiconductor device, wherein the method extends in a direction to cover the surface of the semiconductor substrate. In the manufacturing method of the semiconductor device according to claim 11,
The scribe line width in the second dicing step is 60 μm or more and 120 μm or less,
The kerf width in the second dicing step is 10 μm or more and 40 μm or less,
As a result of the second dicing step, the lower end portion of the sidewall protective film covering the sidewall of the interlayer insulating film has a length of 10 μm or more and 55 μm or less from the sidewall of the interlayer insulating film. A method for manufacturing a semiconductor device, wherein the method extends in a direction to cover the surface of the semiconductor substrate.

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