CN113013098A - Method for forming scribing groove - Google Patents
Method for forming scribing groove Download PDFInfo
- Publication number
- CN113013098A CN113013098A CN202110258189.4A CN202110258189A CN113013098A CN 113013098 A CN113013098 A CN 113013098A CN 202110258189 A CN202110258189 A CN 202110258189A CN 113013098 A CN113013098 A CN 113013098A
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- chip
- mask layer
- forming
- groove
- sealing ring
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- 238000000034 method Methods 0.000 title claims abstract description 39
- 238000005520 cutting process Methods 0.000 claims abstract description 48
- 239000004065 semiconductor Substances 0.000 claims abstract description 42
- 238000007789 sealing Methods 0.000 claims abstract description 33
- 238000005530 etching Methods 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000002184 metal Substances 0.000 claims abstract description 20
- 239000000463 material Substances 0.000 claims abstract description 18
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 8
- 229910052731 fluorine Inorganic materials 0.000 claims description 8
- 239000011737 fluorine Substances 0.000 claims description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 150000004767 nitrides Chemical group 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 4
- 229910052739 hydrogen Inorganic materials 0.000 description 4
- 239000001257 hydrogen Substances 0.000 description 4
- 230000007423 decrease Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000011990 functional testing Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3178—Coating or filling in grooves made in the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Dicing (AREA)
Abstract
The invention provides a method for forming a scribing groove, which comprises the following steps: providing a semiconductor device which comprises a chip, a chip sealing ring and a cutting channel, wherein the chip, the chip sealing ring and the cutting channel are formed on a semiconductor substrate; partially etching the cutting channel and exposing the surface of the semiconductor substrate to form a deep groove, wherein both sides of the deep groove have certain distances from the edge of the cutting channel; forming a mask layer on the surface of the semiconductor device, wherein the mask layer covers the side wall and the bottom wall of the deep groove; and simultaneously etching the mask layer of the bottom wall of the deep groove and the mask layer on the chip to form a scribing groove and a bonding pad respectively. The sealing ring is not damaged by cutting the chip through the scribing groove, so that the chip can be protected. The mask layer on the side wall of the scribing groove prevents the material of the cutting channel from being exposed in air, prevents the metal of the chip from being corroded, and the formed scribing groove has no mask layer at the bottom, so that the cut scratches are smooth and have no edge curl during cutting.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for forming a scribing groove.
Background
In a semiconductor chip process, in a semiconductor chip packaging process, chips need to be cut, and the cutting process is performed in a cutting path. The mechanical force of the cutting may cause minor cracks to form at the edges, especially near the corners. The resulting cracks may push toward the central circuit region of the integrated circuit causing the circuit region therein to be destroyed. To protect the circuit area, a chip seal ring (sea r i ng) is typically disposed on the integrated circuit chip between the circuit area and its scribe line. The chip seal ring can prevent any crack from invading into the circuit area inside the integrated circuit, however, as the chip size becomes smaller, the size of the scribe line between the chips also gradually decreases, the decrease of the scribe line size brings a serious challenge to the subsequent dicing (d i e saw) process, and the micro crack in the dicing process also becomes a hidden trouble affecting the reliability of the product. In the cutting process, the chip sealing ring can be even damaged, and the crack finally enters the chip to cause fatal damage to the chip.
Disclosure of Invention
The invention aims to provide a method for forming a scribing groove, which cuts and separates a plurality of chips through the scribing groove, keeps the integrity of a chip sealing ring, reduces the damage to the chips, and ensures that the side wall and the bottom wall in the scribing groove are smooth.
In order to achieve the above object, the present invention provides a method for forming a scribe line for dividing a plurality of chips, comprising:
providing a semiconductor device, which comprises a chip, a chip sealing ring and a cutting channel, wherein the chip sealing ring is positioned on the periphery of the chip and used for protecting the chip, and the cutting channel is positioned on the periphery of the chip sealing ring;
partially etching the cutting channel and exposing the surface of the semiconductor substrate to form a deep groove, wherein two sides of the deep groove are spaced from the edge of the cutting channel;
forming a mask layer on the surface of the semiconductor device, wherein the mask layer covers the side wall and the bottom wall of the deep groove;
and simultaneously etching the mask layer on the bottom wall of the deep groove to expose the surface of the semiconductor substrate and the mask layer on the chip to expose the surface of the semiconductor device so as to respectively form a scribing groove and a bonding pad.
Optionally, in the method for forming a scribe line, the semiconductor base includes a substrate and a front-end IC.
Optionally, in the method for forming a scribe line, a material of the chip sealing ring includes a metal.
Optionally, in the method for forming a scribe line, the material of the scribe line includes a fluorine-containing oxide.
Optionally, in the method for forming a scribe line, the oxide includes silicon dioxide.
Optionally, in the method for forming a scribe line, the mask layer is made of nitride.
Optionally, in the method for forming a scribe line, the nitride includes silicon nitride.
Optionally, in the method for forming a scribe line, the chip includes a dielectric layer located on the semiconductor substrate, and a plurality of metal layers located in the dielectric layer.
Optionally, in the method for forming a scribe line, the method for simultaneously etching the mask layer of the bottom wall of the deep trench and the mask layer on the chip to form the scribe line and the pad respectively includes: and forming patterned photoresist on the surface of the mask layer, and etching the mask layer of the bottom wall of the deep groove and the mask layer of the chip simultaneously by taking the patterned photoresist as a mask.
Optionally, in the method for forming a scribe line, the deep trench has a width of 4 μm to 6 μm.
The invention provides a method for forming a scribing groove, which comprises the following steps: providing a semiconductor device, which comprises a chip, a chip sealing ring and a cutting channel, wherein the chip sealing ring is positioned on the periphery of the chip and used for protecting the chip, and the cutting channel is positioned on the periphery of the chip sealing ring; partially etching the cutting channel and exposing the surface of the semiconductor substrate to form a deep groove, wherein two sides of the deep groove are spaced from the edge of the cutting channel; forming a mask layer on the surface of the semiconductor device, wherein the mask layer covers the side wall and the bottom wall of the deep groove; and simultaneously etching the mask layer on the bottom wall of the deep groove to expose the surface of the semiconductor substrate and the mask layer on the chip to expose the surface of the semiconductor device so as to respectively form a scribing groove and a bonding pad. Because the scribing groove has a certain distance from the edge of the cutting path, which is equivalent to the scribing groove has a certain distance from the chip sealing ring, the chip can be cut by the scribing groove without damaging the sealing ring, thereby protecting the chip. The mask layer on the side wall of the scribing groove prevents the material of the cutting channel from being exposed in the air, and the material of the cutting channel is prevented from reacting with the air, so that the metal of the chip is prevented from being corroded, the mask layer is not arranged at the bottom of the formed scribing groove, and the cut scratches are smooth and free of curling during cutting.
Drawings
FIG. 1 is a flow chart of a method of forming a scribe line according to an embodiment of the present invention;
fig. 2 to 7 are schematic views illustrating a method of forming a scribe line according to an embodiment of the present invention;
in the figure: 10-deep groove area, 20-sealing ring area, 30-chip area, 110-semiconductor substrate, 120-metal layer structure, 130-dielectric layer, 140-chip sealing ring, 150-cutting channel, 160-deep groove, 170-mask layer, 180-patterned photoresist, 190-scribing groove and 200-bonding pad.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In the following, the terms "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances. Similarly, if the method described herein comprises a series of steps, the order in which these steps are presented herein is not necessarily the only order in which these steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method.
Because the chip is integrated on a wafer after the preparation, consequently, need cut a plurality of chips, general technique adopts and sets up the cutting street between chip and chip, makes the chip part through the cutting street cutting, in order to make when the cutting, the dynamics of cutting can not harm the chip, can increase the chip sealing ring around the chip. However, as the size of the chip and the size of the dicing street are reduced, the chip sealing ring may be damaged during dicing, and the chip may be damaged. Particularly, in order to save more time and resources, the slicing is selected to be carried out after the functional test, and if the chip is damaged at the moment, the consequences can not be imagined. Therefore, it is considered that a dicing groove is formed in the dicing street, and the dicing street is cut from the dicing groove to separate the chip from the chip. Then, since the scribe line is composed of oxide, if the scribe line is directly cut, the oxide of the scribe line is exposed to air, the material of the scribe line also contains fluorine, and the fluorine and hydrogen in the air form HF, which may damage the metal on the chip. Therefore, it is necessary to wrap the exposed portion of the street.
Referring to fig. 1, the present invention provides a method for forming a scribe line for dividing a plurality of chips, including:
s11: providing a semiconductor device, which comprises a chip, a chip sealing ring and a cutting channel, wherein the chip sealing ring is positioned on the periphery of the chip and used for protecting the chip, and the cutting channel is positioned on the periphery of the chip sealing ring;
s12: partially etching the cutting channel and exposing the surface of the semiconductor substrate to form a deep groove, wherein two sides of the deep groove are spaced from the edge of the cutting channel;
s13: forming a mask layer on the surface of the cutting channel, wherein the mask layer covers the side wall and the bottom wall of the deep groove;
s14: and simultaneously etching the mask layer on the bottom wall of the deep groove to expose the surface of the semiconductor substrate and the mask layer on the chip so as to form a scribing groove and a bonding pad respectively.
First, referring to fig. 2, a semiconductor substrate 110 is provided, and the semiconductor substrate 110 may be a substrate, such as a wafer, or a front-end IC. A metal layer structure 120 and a dielectric layer 130 surrounding the metal layer structure 120 are formed on the semiconductor substrate 110, and the dielectric layer 130 is typically a low dielectric constant material such as fluorine-containing silicon dioxide to ensure that the signal delay of the metal wire is smaller. The region with the metal layer structure 120 is divided into chips, a chip sealing ring 140 is formed at the periphery of the chip at the same time, the material of the chip sealing ring 140 includes a metal layer, and the chip sealing ring 140 protects the chip from being damaged by the cutting force. The periphery of the chip seal ring 140 is a scribe line 150, that is, the scribe line 150 is formed of fluorinated oxide.
Next, referring to fig. 3, the scribe line 150 is partially etched to expose the surface of the semiconductor substrate 110, so as to form a deep trench 160, wherein both sides of the deep trench 160 have a certain distance from the edge of the scribe line 150, and specifically, the width of the deep trench is 4 μm to 6 μm, for example, 5 μm. The distance between the deep groove and the scribing position (cutting point) is 20-30 μm. The distance between the deep groove and the chip sealing ring is 5-10 mu m. The etching method may be dry etching. The deep trench 160 is defined in the scribe line 150 by photolithography and then the scribe line 150 is etched, and naturally, the sidewall of the deep trench 160 is formed by the material of the scribe line 150 and the material of the scribe line 150 is exposed to air. The material of the scribe line 150 includes fluorine, which, if exposed to air, combines with hydrogen in the air to form HF, which has a corrosive effect on the metal on the chip.
Next, referring to fig. 4, a mask layer 170 is formed on the surface of the scribe line 150, the mask layer 170 covers the sidewalls and the bottom wall of the deep trench 160, and the material of the mask layer 170 is a nitride, such as silicon nitride. At this time, the mask layer 170 can block fluorine in the scribe line 150 from combining with hydrogen in the air, thereby preventing the metal from being corroded by HF. However, if the deep trench 160 is etched directly to separate the chips, the silicon nitride is brittle, which may cause the scratches not to be smooth enough, and the edge of the cut chip may curl, which may affect the appearance and even the quality.
Next, referring to fig. 5 and 6, a patterned photoresist 180 is formed on the surface of the mask layer 170, and the mask layer 170 on the bottom wall of the deep trench 160 and the mask layer 180 of the chip are etched simultaneously by using the patterned photoresist 180 as a mask to expose the surface of the semiconductor device, so as to form a scribe line 190 and a pad 200 for etching the mask layer 170 on the bottom wall of the deep trench 160 and etching the same, respectively. The mask layer 170 on the chip can be simultaneously etched, and compared with the method of forming a bonding pad only by etching, the mask layer 180 on the bottom wall of the deep trench 160 and the mask layer 170 on the chip can be simultaneously etched by only changing the model of the patterned photoresist 180 in the embodiment of the present invention without additionally increasing the mask plate or the etching step. The mask layer 170 on the sidewall of the scribe line 190 can protect the sidewall of the scribe line 190 and prevent fluorine in the material of the scribe line 150 from being combined with hydrogen in the air, so as to prevent metal on the chip from being corroded, and meanwhile, the bottom of the scribe line 190 has no mask layer, so that a brittle substance is not etched during etching, therefore, scratches formed after etching are smooth, and the edge of the etched chip does not have curling.
Referring to fig. 7, the deep trench region 10 is used to form a deep trench 160 or a scribe line 190, the seal ring region 20 is used to form a chip seal ring 140, the chip region 30 is also a pad region used to form a metal layer structure 120 and a pad 200(pad), the pad 200 exposes the metal layer structure 120, and other electronic products or other semiconductor structures can be connected to the metal layer structure 120 through the pad 200.
In summary, the method for forming a scribe line according to an embodiment of the present invention includes: providing a semiconductor device, which comprises a chip, a chip sealing ring and a cutting channel, wherein the chip sealing ring is positioned on the periphery of the chip and used for protecting the chip, and the cutting channel is positioned on the periphery of the chip sealing ring; partially etching the cutting channel and exposing the surface of the semiconductor substrate to form a deep groove, wherein two sides of the deep groove are spaced from the edge of the cutting channel; forming a mask layer on the surface of the semiconductor device, wherein the mask layer covers the side wall and the bottom wall of the deep groove; and simultaneously etching the mask layer on the bottom wall of the deep groove to expose the surface of the semiconductor substrate and the mask layer on the chip to expose the surface of the semiconductor device so as to respectively form a scribing groove and a bonding pad. Because the scribing groove has a certain distance from the edge of the cutting path, which is equivalent to the scribing groove has a certain distance from the chip sealing ring, the chip can be cut by the scribing groove without damaging the sealing ring, thereby protecting the chip. The mask layer on the side wall of the scribing groove prevents the material of the cutting channel from being exposed in the air, and the material of the cutting channel is prevented from reacting with the air, so that the metal of the chip is prevented from being corroded, the mask layer is not arranged at the bottom of the formed scribing groove, and the cut scratches are smooth and free of curling during cutting.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A method for forming a scribe line for dividing a plurality of chips, comprising:
providing a semiconductor device, which comprises a semiconductor substrate, a chip sealing ring and a cutting channel, wherein the chip sealing ring is positioned on the periphery of the chip and used for protecting the chip, and the cutting channel is positioned on the periphery of the chip sealing ring;
partially etching the cutting channel and exposing the surface of the semiconductor substrate to form a deep groove, wherein two sides of the deep groove are spaced from the edge of the cutting channel;
forming a mask layer on the surface of the semiconductor device, wherein the mask layer covers the side wall and the bottom wall of the deep groove;
and simultaneously etching the mask layer on the bottom wall of the deep groove to expose the surface of the semiconductor substrate and the mask layer on the chip to expose the surface of the semiconductor device so as to respectively form a scribing groove and a bonding pad.
2. The method of forming a scribe lane of claim 1, wherein the semiconductor base comprises a substrate and a front-end IC.
3. The method of forming a scribe lane of claim 1, wherein the material of the chip seal ring comprises a metal.
4. The method of forming a scribe lane of claim 1, wherein the material of the scribe lane comprises a fluorine-containing oxide.
5. The method of forming a scribe lane of claim 4, wherein the oxide comprises silicon dioxide.
6. The method of claim 1, wherein the material of the mask layer is nitride.
7. The method of forming a scribe lane of claim 6, wherein the nitride comprises silicon nitride.
8. The method of forming a scribe lane of claim 1, wherein said die comprises a dielectric layer located over said semiconductor base, and a plurality of metal layers located within said dielectric layer.
9. The method of claim 1, wherein the step of simultaneously etching the mask layer of the bottom wall of the deep trench and the mask layer on the chip to form the scribe line and the pad comprises:
forming patterned photoresist on the surface of the mask layer;
and simultaneously etching the mask layer of the bottom wall of the deep groove and the mask layer of the chip by taking the patterned photoresist as a mask.
10. The method of claim 1, wherein the deep trench has a width of 4 μm to 6 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110258189.4A CN113013098A (en) | 2021-03-09 | 2021-03-09 | Method for forming scribing groove |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110258189.4A CN113013098A (en) | 2021-03-09 | 2021-03-09 | Method for forming scribing groove |
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| CN113013098A true CN113013098A (en) | 2021-06-22 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202110258189.4A Pending CN113013098A (en) | 2021-03-09 | 2021-03-09 | Method for forming scribing groove |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113725106A (en) * | 2021-08-30 | 2021-11-30 | 上海华虹宏力半导体制造有限公司 | Wafer-level chip packaging technology adopting cutting channel groove process chip |
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| JP2008140829A (en) * | 2006-11-30 | 2008-06-19 | Sharp Corp | Semiconductor device and method for manufacturing the same |
| US20120241914A1 (en) * | 2009-09-04 | 2012-09-27 | X-Fab Semiconductor Foundries Ag | Reduction of fluorine contamination of bond pads of semiconductor devices |
| CN105826251A (en) * | 2015-01-09 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Cutting method |
| CN106531628A (en) * | 2016-11-09 | 2017-03-22 | 上海华力微电子有限公司 | Manufacturing method for integrating ion etching scribing groove and sealing ring |
| CN112018027A (en) * | 2019-05-31 | 2020-12-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure, forming method thereof and wafer cutting method |
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2021
- 2021-03-09 CN CN202110258189.4A patent/CN113013098A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2008140829A (en) * | 2006-11-30 | 2008-06-19 | Sharp Corp | Semiconductor device and method for manufacturing the same |
| US20120241914A1 (en) * | 2009-09-04 | 2012-09-27 | X-Fab Semiconductor Foundries Ag | Reduction of fluorine contamination of bond pads of semiconductor devices |
| CN105826251A (en) * | 2015-01-09 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Cutting method |
| CN106531628A (en) * | 2016-11-09 | 2017-03-22 | 上海华力微电子有限公司 | Manufacturing method for integrating ion etching scribing groove and sealing ring |
| CN112018027A (en) * | 2019-05-31 | 2020-12-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure, forming method thereof and wafer cutting method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113725106A (en) * | 2021-08-30 | 2021-11-30 | 上海华虹宏力半导体制造有限公司 | Wafer-level chip packaging technology adopting cutting channel groove process chip |
| CN113725106B (en) * | 2021-08-30 | 2024-02-02 | 上海华虹宏力半导体制造有限公司 | Wafer level chip packaging technology adopting dicing street groove process chip |
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