CN108346564B - Electronic component and method for manufacturing the same - Google Patents
Electronic component and method for manufacturing the same Download PDFInfo
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- CN108346564B CN108346564B CN201710075566.4A CN201710075566A CN108346564B CN 108346564 B CN108346564 B CN 108346564B CN 201710075566 A CN201710075566 A CN 201710075566A CN 108346564 B CN108346564 B CN 108346564B
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- 238000000034 method Methods 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 238000005520 cutting process Methods 0.000 claims abstract description 65
- 238000005192 partition Methods 0.000 claims abstract description 47
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 239000004065 semiconductor Substances 0.000 description 24
- 235000012431 wafers Nutrition 0.000 description 23
- 230000009471 action Effects 0.000 description 10
- 230000006378 damage Effects 0.000 description 6
- 230000008569 process Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000007769 metal material Substances 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000002313 adhesive film Substances 0.000 description 1
- 239000002390 adhesive tape Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000013585 weight reducing agent Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Electromagnetism (AREA)
- Optics & Photonics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Dicing (AREA)
Abstract
A method for manufacturing electronic element includes carrying out invisible cutting along partition portion in substrate containing multiple electronic elements and partition portion set between multiple electronic elements to form multiple invisible cutting paths with different lengths in partition portion, and separating multiple electronic elements along partition portion.
Description
Technical Field
The present invention relates to a method for manufacturing electronic devices, and more particularly, to a method for singulating electronic devices.
Background
In recent years, with the miniaturization and weight reduction of mobile devices such as mobile phones and tablets, and information storage devices that access data via memory cards, the thinning of semiconductor chips incorporated in such devices has been accelerated.
In addition, conventionally, in a semiconductor wafer singulation process, a blade is used to dice the semiconductor wafer to obtain a plurality of semiconductor chips, but since the semiconductor wafer is thin, the dicing easily generates chips and reduces the breaking strength of the semiconductor chips.
Further, from the viewpoint of increasing the operating speed of the semiconductor device, although there is a product using a dielectric film having a lower dielectric constant than silicon oxide as an insulating film between wiring layers of a semiconductor wafer, the dielectric film having a lower dielectric constant is brittle and therefore easily peels off or has a small amount of bubbles inside, so that it is difficult for the blade to cut the film during dicing work.
Therefore, Stealth Dicing (Stealth Dicing) was developed to avoid the above problems.
As shown in fig. 1A, the stealth dicing method is to irradiate a laser 7 along the separation S between the semiconductor chips 10 with the same path length from a semiconductor wafer 1 having the semiconductor chips 10 to the inside of the semiconductor wafer 1 to destroy the internal structure thereof and form a deteriorated layer, and then cut the semiconductor wafer 1 using the deteriorated layer as a dicing path to separate the semiconductor chips 10.
Generally, in the singulation process, if the sizes of the semiconductor chips 10 of the conventional semiconductor wafer 1 are the same, there is no particular problem in singulation by using the stealth dicing method.
However, as shown in fig. 1B, if the sizes of the adjacent semiconductor wafers 10 and 11 are different, the laser light 7 is scattered during the stealth dicing, and therefore, the action surface 1a of the semiconductor wafer 11 having a large size is affected by the scattering near the boundary between the semiconductor wafers 10 and 11, and the action surface 1a is damaged (dam) as shown in fig. 1B.
Therefore, how to overcome the above problems in the prior art has become a problem to be overcome in the industry.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the present invention provides an electronic device and a method for manufacturing the same, which can prevent the scattering of laser light from being affected by the invisible cutting path of the adjacent partition portion to damage the active surface of the electronic device.
The method for manufacturing the electronic element comprises the following steps: providing a substrate with a first surface and a second surface which are opposite, wherein the substrate comprises a plurality of electronic elements and a plurality of partitions arranged among the electronic elements; invisible cutting is carried out corresponding to the positions of the plurality of partitions, wherein the invisible cutting is that a plurality of invisible cutting paths are formed in a single partition, and the lengths of at least two invisible cutting paths are different; and separating each electronic element along the plurality of partitions.
In the foregoing method, before the stealth dicing, a trench is formed on the partition portion from the first surface of the substrate, wherein the trench does not penetrate through the substrate.
In the foregoing manufacturing method, at least two of the electronic components have different sizes.
In the above manufacturing method, the arrangement of the plurality of partitions is T-shaped.
In the foregoing manufacturing method, the length of the invisible cutting path corresponds to the distance from the first surface. For example, a length of the invisible cutting path near the first surface is less than a length of the invisible cutting path away from the first surface.
In the foregoing manufacturing method, the electronic component has an active surface and an inactive surface corresponding to each other, and a side surface adjacent to the active surface and the inactive surface, wherein the active surface corresponds to the first surface of the substrate, the inactive surface corresponds to the second surface of the substrate, and the side surface includes a smooth region and a rough region adjacent to each other. For example, the rough area represents traces of the plurality of invisible cutting paths, while the smooth area is not formed with traces of the invisible cutting paths.
The invention also provides an electronic element, which is provided with an active surface and an inactive surface which are opposite to each other, and at least one side surface which is adjacent to the active surface and the inactive surface, and at least one side surface is defined with a smooth area and a rough area which are adjacent to each other, wherein the rough area presents the trace of the invisible cutting path, and the smooth area does not form the trace of the invisible cutting path.
In the electronic component, the range of the rough region has a trapezoidal profile.
In the foregoing electronic component, the range of the smooth region has a triangular contour.
In the foregoing electronic component, the smooth region is adjacent to the active surface and not adjacent to the inactive surface.
In the electronic component, the rough region is adjacent to the active surface and the non-active surface.
Therefore, the electronic component and the manufacturing method thereof of the invention mainly have the advantages that the lengths of at least two invisible cutting paths formed on the partition part are different, so compared with the prior art, the manufacturing method of the invention can prevent the scattering of laser from being influenced by the invisible cutting paths of the adjacent partition part to cause the damage of the action surface of the electronic component.
Drawings
FIG. 1A is a schematic perspective view illustrating a singulation process of a semiconductor wafer according to the prior art;
FIG. 1B is a schematic partial perspective cross-sectional view illustrating a conventional semiconductor wafer undergoing an invisible dicing process;
fig. 2A to 2D are schematic cross-sectional views illustrating a method for manufacturing an electronic device according to the present invention;
FIG. 3A is a schematic top view of a portion of FIG. 2A;
FIG. 3B is a schematic partial perspective cross-sectional view of FIG. 2C; and
fig. 3C is a side view of the electronic device of the present invention.
Description of the symbols:
1 semiconductor wafer
1a surface of action
10,11 semiconductor wafer
20,21 electronic component
20a surface of action
20b non-active surface
20c,20d side
22 groove
23a-23e,24 invisible cutting path
7 laser
8 bearing part
9 base plate
9a first surface
9b second surface
A smooth area
B rough region
D, L, L1-L5 Length
H horizontal direction
k damage
S, S1, S2 partition
X, Y transverse
Z depth direction.
Detailed Description
The following description of the embodiments of the present invention is provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein.
It should be understood that the structures, ratios, sizes, and the like shown in the drawings and described in the specification are only used for understanding and reading the contents disclosed in the specification, and are not used for limiting the conditions under which the present invention can be implemented, so that the present invention has no technical significance, and any structural modifications, ratio relationship changes or size adjustments should still fall within the scope of the technical contents disclosed in the present invention without affecting the efficacy and the achievable purpose of the present invention. In addition, the terms such as "above", "first", "second", "third", "fourth", "fifth", and "a" used in the present specification are for convenience of description only, and are not intended to limit the scope of the present invention, and changes or modifications in the relative relationship may be made without substantial technical changes and modifications.
Fig. 2A to 2D are schematic cross-sectional views illustrating a method for manufacturing the electronic component 20 according to the present invention.
As shown in fig. 2A, a substrate 9 is provided, the substrate 9 includes a plurality of electronic components 20,21 and a partition S disposed between the electronic components 20, and the substrate 9 has a first surface 9a and a second surface 9b opposite to each other.
In the present embodiment, the first surface 9a corresponds to an active surface of the electronic component 20,21 having a plurality of electrode pads (not shown), and the second surface 9b corresponds to an inactive surface of the electronic component 20, 21.
In addition, the partition S is used as a scribe line, and a metal material (not shown) may be selectively provided on the first surface 9 a.
A carrier 8 can be bonded to the second surface 9b, for example, the carrier 8 is an adhesive film (such as an adhesive tape) optionally having a release profile (not shown) to facilitate the subsequent peeling of the carrier 8 and the electronic components 20 and 21.
In addition, the electronic components 20,21 may be active components such as semiconductor chips or passive components such as resistors, capacitors and inductors. Specifically, the substrate 9 is a silicon wafer, and each of the electronic components 20 and 21 is a wafer, as shown in fig. 3A, the sizes of the electronic components 20 and 21 are different (for example, the electronic component 20 is a small-sized wafer, and the electronic component 21 is a large-sized wafer), and the arrangement of the partitions S1 and S2 may be in a T shape. It should be understood that the partitions S1, S2 shown in fig. 3A are part of the partition S shown in fig. 2A.
As shown in fig. 2B, a portion of the material (including the metal material) on each of the partitions S is removed from the first surface 9a of the substrate 9 to form a trench 22 on each of the partitions S, wherein none of the trenches 22 penetrates through the substrate 9.
In the present embodiment, the groove 22 can be formed by laser ablation, diamond knife cutting or other suitable methods, and is not particularly limited.
As shown in fig. 2C, the invisible dicing is performed from the second surface 9B of the substrate 9 at the position corresponding to the groove 22 in each of the partitions S, wherein, as shown in fig. 3B, the invisible dicing is performed by respectively forming one group of a plurality of invisible dicing paths 23a-23e and another group of a plurality of invisible dicing paths 24 in one of the partitions S1, S2, and the lengths L1-L5 (i.e., the distance extending in the transverse direction or the distance extending in the horizontal direction) of at least two of the invisible dicing paths 23a-23e of at least one of the partitions S1 are different.
In the present embodiment, the stealth dicing is performed by focusing the laser 7 inside the silicon wafer and moving the laser 7 laterally to destroy the structure, so that the plurality of stealth dicing paths 23a-23e,24 are formed by focusing the laser beam on the internal destruction structure of the silicon wafer (as shown in fig. 3B, the focus destroyed state is represented by a plurality of dots).
In addition, in one of the partitions S1 shown in fig. 3A and 3B, the lengths L1-L5 of the invisible cutting paths 23A-23e are corresponding to the positions far from the first surface 9a, for example, the length L1 of the invisible cutting path 23A near the first surface 9a is smaller than the length L5 of the invisible cutting path 23e far from the first surface 9 a. Specifically, the lengths L1-L5 of the invisible cutting paths 23a-23e sequentially increase from the first surface 9a of the electronic component 20 to the second surface 9B thereof (i.e., in a downward direction along a vertical direction or in a downward direction along the depth direction Z as shown in FIG. 3B).
In addition, the plurality of invisible cutting paths 23a-23e are formed in sequence from the first surface 9a of the substrate 9 to the second surface 9b thereof, that is, based on the operation manner shown in fig. 2C, the invisible cutting path 23a farthest from the second surface 9b is formed first, and then the other invisible cutting paths 23b,23C,23d,23e are formed in sequence gradually closer to the second surface 9 b. Specifically, since the first invisible cutting path 23a is closer to the functional area of the wafer active surface (i.e., the first surface 9a), the length L1 of the first invisible cutting path 23a is, for example, 50% of the length D of the partition S1 where it is located, the length L2 of the second invisible cutting path 23b is, for example, 60% of the length D of the partition S1 where it is located, the length L3 of the third invisible cutting path 23c is, for example, 70% of the length D of the partition S1 where it is located, the length L4 of the fourth invisible cutting path 23D is, for example, 80% of the length D of the partition S1 where it is located, and the length L5 of the fifth invisible cutting path 23e is, for example, 90% of the length D of the partition S1 where it is located. In another embodiment, the length of the sixth invisible cutting path (not shown) is equal to the length D of the partition S1 where the sixth invisible cutting path is located.
In addition, in another partition S2 as shown in fig. 3A and 3B, the lengths L of the invisible cutting paths 24 may be gradually changed or maintained equal in sequence from the first surface 9a to the second surface 9B thereof according to the invisible cutting paths 23A-23e, and if the lengths L are maintained equal, the lengths L are, for example, 100% of the length of the partition S2 where the lengths L are located.
As shown in fig. 2D, the electronic components 20 and 21 are separated by performing a film expanding operation along the plurality of partitions S in a direction toward the plurality of invisible cutting paths 23A to 23e (i.e., a transverse moving direction of the laser light 7, a horizontal direction H, or transverse directions X and Y shown in fig. 3A), and the single separated electronic component 20 and 21 is formed with side surfaces 20C and 20D adjacent to the active surface 20a and the inactive surface 20b, as shown in fig. 3C.
In the present embodiment, as shown in fig. 3A and 3C, at least one side surface 20C of the small-sized electronic component 20 (for example, the side surface 20C adjacent to another small electronic component 20) defines an adjacent smooth area a and a rough area B. Specifically, the rough area B represents traces of the invisible cutting paths 23a-23e (the traces are represented by wavy lines shown in fig. 3C, but the wavy lines are not used to represent the shape of the actual traces), while the smooth area a does not form traces of the invisible cutting paths 23a-23 e.
In addition, the other side 20d of the small-sized electronic component 20 (e.g., the side 20d adjacent to the large electronic component 21) shown in fig. 3A and 3C presents the rough region B without the smooth region a if the lengths of the invisible cutting paths are maintained to be equal; on the other hand, if the length of the invisible cutting path is gradually increased from the first surface 9a to the second surface 9B, the side surface 20d is formed with a smooth area a and a rough area B adjacent to each other.
It should be understood that, after the separation of the large-sized electronic component 21 shown in fig. 3A and 3B, if the lengths of the invisible cutting paths are maintained to be equal, the rough area B is present on the side surface, but the smooth area a is absent; on the other hand, if the lengths of the invisible cutting paths are not uniform and vary, the side surfaces thereof are formed with a smooth area a and a rough area B which are adjacent to each other.
The length L1-L5 of at least two invisible cutting paths 23a-23e of at least one partition S1 is different, and the length L1 of the first invisible cutting path 23a is less than or about equal to 50% of the length D of the partition S, so compared with the prior art, the method of the invention can avoid the scattering of the laser 7 from being influenced by the invisible cutting path 24 of the adjacent partition S2 because the invisible cutting path of the partition S1 close to the action surface is shorter, thereby avoiding the damage of the action surface of the large-size electronic element 21, and the invisible cutting path of the partition S1 far away from the action surface is longer, so that the wafers (the electronic elements 20,21) can still be separated smoothly.
In addition, the length L2 of the second invisible cutting path 23b is greater than the length L1 of the first invisible cutting path 23a, so that the separating operation of the electronic components 20 and 21 can be improved without affecting the action surface of the large-sized electronic component 21.
The invention also provides an electronic component 20, which has an active surface 20a and an inactive surface 20B opposite to each other, and a plurality of side surfaces 20c adjacent to the active surface 20a and the inactive surface 20B, wherein at least one of the side surfaces 20c is defined with an adjacent smooth area a and an adjacent rough area B.
In one embodiment, the rough region B has traces of invisible scribe lines 23a-23e (i.e., laser-fired traces), and the smooth region A exhibits a lattice cross-section without traces of the invisible scribe lines 23a-23 e.
In one embodiment, the rough region B has a substantially trapezoidal profile, as shown in fig. 3C.
In one embodiment, the smooth area A has a substantially triangular profile, as shown in FIG. 3C.
In one embodiment, the smooth area A is adjacent to the active surface 20a and not adjacent to the inactive surface 20 b.
In one embodiment, the rough region B is adjacent to the active surface 20a and the inactive surface 20B.
In summary, the lengths of at least two invisible cutting paths formed on the partition are different, so compared with the prior art, the electronic component and the manufacturing method thereof can prevent the scattering of laser from being influenced by the invisible cutting paths of the adjacent partition to cause the damage of the action surface of the electronic component.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify the above-described embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.
Claims (9)
1. A method of manufacturing an electronic component, the method comprising:
providing a substrate with a first surface and a second surface which are opposite, wherein the substrate comprises a plurality of electronic elements and a plurality of partitions arranged among the electronic elements;
forming a groove which does not penetrate through the substrate on the partition part from the first surface of the substrate;
invisible cutting is carried out corresponding to the positions of the plurality of partitions, wherein the invisible cutting is to form a plurality of invisible cutting paths in a single partition, the lengths of at least two invisible cutting paths are different, the length of each invisible cutting path corresponds to the position far away from the first surface, and the length of the invisible cutting path close to the first surface is smaller than the length of the invisible cutting path far away from the first surface; and
and separating each electronic element along the plurality of partitions, wherein each electronic element is provided with a corresponding active surface and a corresponding non-active surface, and side surfaces adjacent to the active surface and the non-active surface, the active surface corresponds to the first surface of the substrate, and the non-active surface corresponds to the second surface of the substrate.
2. A method for manufacturing an electronic component according to claim 1, wherein at least two of the electronic components have different sizes.
3. A method for manufacturing an electronic component according to claim 1, wherein the arrangement of the plurality of partitions is T-shaped.
4. A method of manufacturing an electronic component according to claim 1, wherein the side surface comprises adjacent smooth and rough areas.
5. The method of claim 4, wherein the rough areas exhibit traces of the plurality of invisible cutting paths, and the smooth areas are not formed with traces of the invisible cutting paths.
6. An electronic element is provided with an active surface and an inactive surface which are opposite to each other, and at least one side surface which is adjacent to the active surface and the inactive surface, wherein at least one side surface is defined with a smooth area and a rough area which are adjacent to each other, the rough area presents the trace of an invisible cutting path, the length of the invisible cutting path corresponds to the position far away from the active surface, the length of the invisible cutting path close to the active surface is smaller than the length of the invisible cutting path far away from the active surface, the trace of the invisible cutting path is not formed in the smooth area, and the smooth area is adjacent to the active surface but not adjacent to the inactive surface.
7. An electronic component according to claim 6, wherein the roughened region has a trapezoidal profile.
8. The electrical component of claim 6, wherein the smooth region has a triangular profile.
9. An electronic component according to claim 6, characterized in that the roughened region adjoins the active side and the non-active side.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW106102896A TWI612621B (en) | 2017-01-25 | 2017-01-25 | Electronic element and the manufacture thereof |
| TW106102896 | 2017-01-25 |
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| CN108346564A CN108346564A (en) | 2018-07-31 |
| CN108346564B true CN108346564B (en) | 2021-01-08 |
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| US11054574B2 (en) | 2019-05-16 | 2021-07-06 | Corning Research & Development Corporation | Methods of singulating optical waveguide sheets to form optical waveguide substrates |
| CN111276577B (en) * | 2019-12-18 | 2021-12-10 | 北京中科优唯科技有限公司 | Manufacturing method of LED chip |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007021514A (en) * | 2005-07-13 | 2007-02-01 | Seiko Epson Corp | Scribe forming method, and substrate with division projected line |
| CN1967805A (en) * | 2005-11-16 | 2007-05-23 | 株式会社电装 | Semiconductor device and dicing method for semiconductor substrate |
| TW201210732A (en) * | 2010-07-21 | 2012-03-16 | Hamamatsu Photonics Kk | Laser processing method |
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| JP4659300B2 (en) * | 2000-09-13 | 2011-03-30 | 浜松ホトニクス株式会社 | Laser processing method and semiconductor chip manufacturing method |
| WO2015175268A1 (en) * | 2014-05-16 | 2015-11-19 | Applied Materials, Inc. | Hybrid wafer dicing approach using an ultra-short pulsed laguerre gauss beam laser scribing process and plasma etch process |
| JP6504977B2 (en) * | 2015-09-16 | 2019-04-24 | 株式会社ディスコ | Wafer processing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007021514A (en) * | 2005-07-13 | 2007-02-01 | Seiko Epson Corp | Scribe forming method, and substrate with division projected line |
| CN1967805A (en) * | 2005-11-16 | 2007-05-23 | 株式会社电装 | Semiconductor device and dicing method for semiconductor substrate |
| TW201210732A (en) * | 2010-07-21 | 2012-03-16 | Hamamatsu Photonics Kk | Laser processing method |
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| TW201828410A (en) | 2018-08-01 |
| TWI612621B (en) | 2018-01-21 |
| CN108346564A (en) | 2018-07-31 |
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