CN112599502B - Preparation method of multilayer wafer - Google Patents
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- CN112599502B CN112599502B CN202011444742.5A CN202011444742A CN112599502B CN 112599502 B CN112599502 B CN 112599502B CN 202011444742 A CN202011444742 A CN 202011444742A CN 112599502 B CN112599502 B CN 112599502B
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- 238000002360 preparation method Methods 0.000 title abstract description 8
- 235000012431 wafers Nutrition 0.000 claims abstract description 377
- 238000009966 trimming Methods 0.000 claims abstract description 176
- 238000005520 cutting process Methods 0.000 claims abstract description 68
- 238000000034 method Methods 0.000 claims abstract description 48
- 239000000758 substrate Substances 0.000 claims description 31
- 239000002184 metal Substances 0.000 claims description 11
- 230000001681 protective effect Effects 0.000 claims description 9
- 239000003292 glue Substances 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 230000003247 decreasing effect Effects 0.000 claims description 4
- 238000013467 fragmentation Methods 0.000 abstract description 2
- 238000006062 fragmentation reaction Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 120
- 238000010586 diagram Methods 0.000 description 20
- 239000012790 adhesive layer Substances 0.000 description 7
- 238000000227 grinding Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
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- 238000011161 development Methods 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 239000002390 adhesive tape Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
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- 239000000945 filler Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000011112 process operation Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/071—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next and on each other, i.e. mixed assemblies
Abstract
The application provides a preparation method of a multilayer wafer. The method includes providing M wafers bonded in sequence to form a wafer stack; trimming the edge of the wafer stack from the first surface of the wafer stack toward the second surface of the wafer stack N times to form N steps on the edge of the wafer stack; the width of the cutting edge generated by the ith cutting edge in the N times of cutting edges is smaller than that of the cutting edge generated by the jth cutting edge in the N times of cutting edges, and the depth of the cutting edge generated by the ith cutting edge is larger than that of the cutting edge generated by the jth cutting edge; the minimum trimming width generated in the N times of trimming is not smaller than a preset threshold value, and the maximum trimming depth generated in the N times of trimming is smaller than or equal to the thickness of the wafer stack; forming a filling layer at the edge of the wafer stack, wherein the filling layer at least fills N steps of the wafer stack; thinning the second surface of the wafer stack; wherein M, N is a natural number greater than 1. The method can reduce the probability of wafer stacking fragmentation in the thinning process.
Description
Technical Field
The application relates to the technical field of integrated circuit manufacturing, in particular to a preparation method of a multilayer wafer.
Background
With the development of semiconductor technology, 3D-IC (three-dimensional integrated circuit) technology is widely used, which uses wafer level packaging technology to bond different wafer stacks together to form a wafer stack structure.
Currently, a method for manufacturing a multi-layer wafer generally stacks and bonds a plurality of wafers in sequence to form a wafer stack; in a specific implementation process, in order to further reduce the thickness of the product, before packaging the wafer stack, thinning the substrate of the wafer stack is generally performed; however, since the step formed by trimming is present at the edge of the wafer stack, during the thinning process, the wafer stack is prone to breaking due to uneven stress, and in order to avoid this problem, a filling layer is generally disposed on the step and on a surface of a side of the wafer stack facing away from the substrate before the thinning process is performed on the wafer stack; and then thinning the substrate of the wafer stack and removing the filling layer.
However, as the number of wafer layers on the wafer stack increases, the depth of the step at the edge of the wafer stack also becomes deeper, making it difficult for the filler layer to cover the step well, and further, the problem of chipping may still occur due to uneven stress of the wafer stack at the step.
Disclosure of Invention
The preparation method of the multilayer wafer can solve the problem that the depth of the steps at the edge of the wafer stack is deeper and deeper along with the increase of the number of layers of the wafer on the wafer stack, so that the filling layer is difficult to cover the steps well, and the problem of fragmentation possibly caused by uneven stress of the wafer stack at the steps still occurs.
In order to solve the technical problems, the application adopts a technical scheme that: a method for preparing a multi-layer wafer is provided. The method includes providing M wafers bonded in sequence to form a wafer stack having first and second surfaces opposite each other; trimming the edge of the wafer stack from the first surface of the wafer stack toward the second surface of the wafer stack N times to form N steps on the edge of the wafer stack; the width of the cutting edge generated by the ith cutting edge in the N times of cutting edges is smaller than that of the cutting edge generated by the jth cutting edge in the N times of cutting edges, and the depth of the cutting edge generated by the ith cutting edge is larger than that of the cutting edge generated by the jth cutting edge; the minimum trimming width generated in the N times of trimming is not smaller than a preset threshold value, and the maximum trimming depth generated in the N times of trimming is smaller than or equal to the thickness of the wafer stack; forming a filling layer at the edge of the wafer stack, wherein the filling layer at least fills N steps of the wafer stack; thinning the second surface of the wafer stack; wherein M, N is a natural number greater than 1, i+.j.
The m-th wafer in the wafer stack comprises a substrate, a dielectric layer positioned on one side surface of the substrate and a metal layer embedded in the dielectric layer; bonding the mth wafer with the (m-1) th wafer through the dielectric layer of the mth wafer; wherein, M is more than or equal to 2 and less than or equal to M, and the value of M is gradually decreased from the first surface of the wafer stack to the second surface of the wafer stack.
Trimming the edge of the wafer stack from the first surface of the wafer stack toward the second surface of the wafer stack N times to form N steps on the edge of the wafer stack specifically includes: the width of the cutting edge generated by the ith cutting edge is smaller than that of the cutting edge generated by the ith-1 cutting edge, and the depth of the cutting edge generated by the ith cutting edge is larger than that of the cutting edge generated by the ith-1 cutting edge, wherein i is more than or equal to 2 and less than or equal to N.
The trimming depth generated by the last trimming is between the thickness of the wafer stack and the thickness of the remaining wafer stack after the first wafer is removed.
Wherein, N=M, the horizontal step surface formed by the i-1 th trimming is positioned in the dielectric layer between the M-th wafer and the M-1 th wafer; wherein, (i-1) + (M-1) =m; when i=n, the horizontal step surface formed by the ith trim is located in the first wafer.
Trimming the edge of the wafer stack from the first surface of the wafer stack toward the second surface of the wafer stack N times to form N steps on the edge of the wafer stack specifically includes: the width of the cutting edge generated by the ith cutting edge is larger than that of the cutting edge generated by the ith-1 cutting edge, and the depth of the cutting edge generated by the ith cutting edge is smaller than that of the cutting edge generated by the ith-1 cutting edge, wherein i is more than or equal to 2 and less than or equal to N.
When i=2, the i-1 th trimming is performed to generate a trimming depth between the thickness of the wafer stack and the thickness of the remaining wafer stack after the first wafer is removed.
Wherein n=m, the horizontal step surface formed by the ith trimming is located in the dielectric layer between the mth wafer and the M-1 th wafer, where i=m;
when i=2, the horizontal step surface formed by the i-1 st trimming is located in the first wafer.
Wherein, forming a filling layer at the edge of the wafer stack, the step of filling the filling layer with at least N steps of the wafer stack specifically includes:
and coating an adhesive layer on the edge of the wafer stack, wherein the adhesive layer at least fills N steps of the wafer stack.
Wherein, after the step of forming a filling layer at the edge of the wafer stack, the filling layer fills at least N steps of the wafer stack, before the step of thinning the second surface of the wafer stack, the method further comprises: and arranging a protective film on the surface of one side of the filling layer, which is far away from the wafer stack.
The preparation method of the multilayer wafer comprises the steps of forming a wafer stack by providing M wafers which are bonded in sequence, and trimming the edge of the wafer stack from the first surface of the wafer stack towards the second surface of the wafer stack for N times so as to form N steps on the edge of the wafer stack; then forming a filling layer at the edge of the wafer stack, wherein the filling layer at least fills N steps of the wafer stack; finally, thinning the second surface of the wafer stack; the width of the trimming edge generated by the ith trimming edge in the N trimming edges is smaller than that of the trimming edge generated by the jth trimming edge in the N trimming edges, and the depth of the trimming edge generated by the ith trimming edge is larger than that of the trimming edge generated by the jth trimming edge, so that the formed N steps are distributed in a step shape, the surface tension of the edge of the wafer stack is greatly increased, the covering capacity of the filling layer on the steps of the wafer stack is effectively improved, the filling layer can better cover the N steps, and the probability of breakage of the wafer stack at the steps due to uneven stress in the thinning process is greatly reduced; in addition, by enabling the minimum trimming width generated by N times of trimming to be larger than a preset threshold value, the positions where the edges of the wafer stack have defects can be effectively cut off.
Drawings
FIG. 1 is a flowchart of a method for manufacturing a multi-layered wafer according to a first embodiment of the present application;
FIG. 2 is a schematic diagram of a wafer stack according to an embodiment of the present application;
FIG. 3 is a schematic diagram of the product structure of FIG. 1 after the processing of step S12 according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a product structure after first trimming the edges of a wafer stack according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a product structure after performing a second trimming on an edge of a wafer stack according to an embodiment of the present application;
FIG. 6 is a schematic diagram of a product structure after performing a third trimming on an edge of a wafer stack according to an embodiment of the present application;
fig. 7 is a schematic view of a product structure after first trimming an edge of a wafer stack according to another embodiment of the present application;
fig. 8 is a schematic diagram of a product structure after performing a second trimming on an edge of a wafer stack according to another embodiment of the present application;
fig. 9 is a schematic diagram of a product structure after performing a third trimming on an edge of a wafer stack according to another embodiment of the present application;
fig. 10 is a schematic view of a product structure after performing a second trimming on an edge of a wafer stack according to another embodiment of the present application;
FIG. 11 is a schematic view of a product structure after a third trimming of an edge of a wafer stack according to another embodiment of the present application;
FIG. 12 is a schematic diagram of the product structure of FIG. 1 after the treatment of step S13 according to an embodiment of the present application;
FIG. 13 is a schematic diagram of the product structure of FIG. 1 after the treatment in step S14 according to an embodiment of the present application;
fig. 14 is a schematic structural view of a filling layer with a protective film disposed on a surface of the filling layer far from a wafer stack according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The terms "first," "second," "third," and the like in this disclosure are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", and "a third" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise. All directional indications (such as up, down, left, right, front, back … …) in embodiments of the present application are merely used to explain the relative positional relationship, movement, etc. between the components in a particular gesture (as shown in the drawings), and if the particular gesture changes, the directional indication changes accordingly. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
The present application will be described in detail with reference to the accompanying drawings and examples.
Referring to fig. 1 and 2, fig. 1 is a flowchart of a method for preparing a multi-layer wafer according to a first embodiment of the present application; FIG. 2 is a schematic diagram of a wafer stack according to an embodiment of the present application; in this embodiment, a method for manufacturing a multi-layer wafer is provided, which can reduce the probability of breakage of a wafer stack at a step due to uneven stress during a subsequent thinning process.
Specifically, referring to fig. 1, the preparation method of the multilayer wafer specifically includes:
step S11: m wafers bonded in sequence are provided to form a wafer stack.
Wherein, M is a natural number greater than 1, the minimum value of M is 2, and in particular, M may be 4, and the specific structure of the wafer stack may be referred to fig. 2, and fig. 2 is a schematic structural diagram of the wafer stack according to an embodiment of the present application; the wafer stack is provided with a first surface A and a second surface B which are opposite; the mth wafer in the wafer stack at least comprises a substrate, a dielectric layer positioned on one side surface of the substrate and a metal layer embedded in the dielectric layer; bonding the mth wafer with the (m-1) th wafer through the dielectric layer of the mth wafer; wherein, M is more than or equal to 2 and less than or equal to M, and the value of M is gradually decreased from the first surface A of the wafer stack to the second surface B of the wafer stack. In one embodiment, when m is greater than or equal to 2, the mth wafer in the wafer stack includes an mth wafer substrate, a second dielectric layer of the mth wafer and a third dielectric layer of the mth wafer on opposite surfaces of the mth wafer substrate, and a second metal layer of the mth wafer embedded in the second dielectric layer of the mth wafer, and a third metal layer of the mth wafer embedded in the third dielectric layer of the mth wafer. Specifically, referring to fig. 2, in a direction from the first surface a toward the second surface B of the wafer stack, the values of m are 4, 3, 2, and 1 in order; when m=2, the m=2 th wafer 2 in the wafer stack includes the m=2 th wafer substrate 21, the second dielectric layer 22 of the m=2 th wafer 2 and the third dielectric layer 23 of the m=2 th wafer 2 on opposite surfaces of the m=2 th wafer substrate 21, and the second metal layer 24 of the m=2 th wafer 2 embedded in the second dielectric layer 22 of the m=2 th wafer 2, the third metal layer 25 of the m=2 th wafer 2 embedded in the third dielectric layer 23 of the m=2 th wafer 2; the second dielectric layer 22 of the m=2nd wafer 2 is bonded to the m-1=1st wafer 1; the second dielectric layer 32 of the m=3 th wafer 3 is bonded to the third dielectric layer 23 of the m-1=2 th wafer 2; the second dielectric layer 42 of the m=4 th wafer 4 is bonded to the third dielectric layer 33 of the m-1=3 rd wafer 3; and so on, the second dielectric layer of the mth wafer is bonded with the third dielectric layer of the m-1 th wafer.
When m=2, the m-1 th wafer, that is, the first wafer 1 may include a first substrate 11, a first dielectric layer 12 located on one side surface of the first substrate 11, and a first metal layer 13 embedded in the first dielectric layer 12; of course, in other embodiments, the first wafer 1 may be a substrate, i.e., the first wafer 1 does not include the first dielectric layer 12, and the second dielectric layer 22 of the 2 nd wafer is directly bonded to the substrate wafer.
In a specific embodiment, when m=m, a groove is formed on a surface of one side of the mth wafer away from the M-1 th wafer, a connection pad 15 is placed in the groove, and the connection pad 15 can be connected with the second metal layer of the mth wafer for subsequent needle insertion test; specifically, the grooves penetrate through the third dielectric layer and the substrate of the mth wafer, and the height of the upper surface of the connection pad 15 is lower than the surface of the mth wafer far away from the mth-1 wafer, so that the thickness of the planarization layer for planarizing the stacked surface of the wafer is reduced as much as possible after the subsequent needle insertion test, which is beneficial for the development of products in the direction of thinning and thinning. In another embodiment, the connection pad 15 may be electrically connected to the second metal layer of the mth wafer. Specifically, in this embodiment, when m=4, the connection pad 15 may be specifically connected to the second metal layer 44 of the 4 th wafer 4.
Specifically, the mth wafer is a device wafer, that is, electronic devices such as a semiconductor device, a chip circuit, a through hole, or a conductive pad may be formed on the substrate of the mth wafer, and the device structure of the device wafer may include one or more of a well-known capacitor, resistor, inductor, MOS transistor, amplifier, or logic circuit.
Step S12: the edge of the wafer stack is trimmed N times from the first surface of the wafer stack toward the second surface of the wafer stack to form N steps at the edge of the wafer stack.
The step in the application specifically refers to a combination of a side wall and a horizontal step surface formed at the wafer stacking edge after trimming the wafer stacking edge; in the specific implementation process, an edge cutting machine table can be used for cutting edges; referring to fig. 3, fig. 3 is a schematic diagram of the product structure after the step S12 in fig. 1 according to an embodiment of the present application; in one embodiment, to increase the surface tension of the steps of the wafer stack while minimizing the process, N.ltoreq.M; of course, in the implementation process, the value of N can be selected according to the thickness of the actual wafer stack, so that N is more than or equal to M, and the surface tension of the steps of the wafer stack is ensured; in one embodiment, n=m, i.e., the number of trimming steps is the same as the number of wafers in the wafer stack, which is exemplified in the following embodiments.
The width Wi generated by the ith trimming in the N trimming is specifically defined as the horizontal distance between the position of the ith trimming and the outermost edge of the wafer stack, and the width Wj generated by the jth trimming in the N trimming is specifically defined as the horizontal distance between the position of the jth trimming and the outermost edge of the wafer stack; the depth Hi generated by the ith trimming in the N trimming specifically refers to the vertical distance between the first surface a of the wafer stack and the horizontal step surface formed by the ith trimming, and the depth Hj generated by the jth trimming in the N trimming specifically refers to the vertical distance between the first surface a of the wafer stack and the horizontal step surface formed by the jth trimming; wherein, the values of i and j are different, i.e. i is not equal to j; the width Wi generated by the ith trimming in the N trimming is smaller than the width Wj generated by the jth trimming in the N trimming, and the depth Hi generated by the ith trimming in the N trimming is larger than the depth Hj generated by the jth trimming in the N trimming. The minimum trimming width generated in the N times of trimming is not smaller than a preset threshold W0, and the maximum trimming depth generated in the N times of trimming is smaller than or equal to the thickness of the wafer stack, wherein the preset threshold is the horizontal distance between the trimming position for removing the edge defect of each layer of wafer stack and the outermost edge of the wafer stack.
In one embodiment, the trimming process may sequentially perform trimming from shallow to deep from a position away from the wafer stack edge to a position close to the wafer stack edge, i.e., the trimming width is changed from large to small and the depth generated by the trimming is changed from small to large.
Specifically, in this embodiment, the width of the cut produced by the ith cut is smaller than the width of the cut produced by the ith-1 st cut, and the depth of the cut produced by the ith cut is greater than the depth of the cut produced by the ith-1 st cut, wherein 2.ltoreq.i.ltoreq.N.
Specifically, in this embodiment, when i=n, that is, the trimming depth generated by the last trimming is between the thickness of the wafer stack and the thickness of the remaining wafer stack after the first wafer 1 is removed.
Specifically, in one embodiment, n=m, and the horizontal step surface formed by the i-1 th trimming is located in the dielectric layer between the M-1 th wafer and the M-1 th wafer; wherein, (i-1) + (M-1) =m; and when i=n, the horizontal step surface formed by the ith trimming is located in the first wafer 1; for example, when n=3, the horizontal step surface formed by the first trimming is located in the dielectric layer between the third wafer 3 and the second wafer 2, and it is understood that the dielectric layer may be the third dielectric layer 23 of the second wafer 2; the horizontal step surface formed by the second trimming is located in the dielectric layer between the second wafer 2 and the first wafer 1, it is understood that the dielectric layer may be the first dielectric layer 12 of the first wafer 1, and the horizontal step surface formed by the third trimming is located on the first substrate 11 of the first wafer 1.
The following describes in detail one embodiment.
Specifically, referring to fig. 4 to 6, fig. 4 is a schematic diagram of a product structure after first trimming an edge of a wafer stack according to an embodiment of the present application; FIG. 5 is a schematic diagram of a product structure after performing a second trimming on an edge of a wafer stack according to an embodiment of the present application; FIG. 6 is a schematic diagram of a product structure after performing a third trimming on an edge of a wafer stack according to an embodiment of the present application; specifically, when n=m=4, the value of i is 2, the value of i-1 is 1, the edge of the wafer stack is subjected to the i-1=1 trimming, that is, the first trimming, and is cut onto the third dielectric layer 33 of the third wafer 3, so as to form a first step 404a on the third dielectric layer 33 of the third wafer 3, that is, the horizontal step surface formed by the i-1=1 trimming is located in the dielectric layer between the m=4th wafer 4 and the M-1=3rd wafer 3, the product structure after the first trimming can be specifically seen in fig. 4, the width generated by the first trimming is W01a, and the depth generated by the first trimming is H01a; then, the value of i is 3, the value of i-1 is 2, the edge of the wafer stack is subjected to i-1=2 times of trimming, namely second trimming, and is cut onto the third dielectric layer 23 of the second wafer 2, so that a second step 304a is formed on the third dielectric layer 23 of the second wafer 2, namely the horizontal step surface formed by the i-1=2 times of trimming is positioned in the dielectric layer between the m=3rd wafer 3 and the m-1=2nd wafer 2, the product structure after the second trimming can be seen in fig. 5, the width generated by the second trimming is W02a, the depth generated by the second trimming is H02a, wherein W02a is less than W01a, and H02a is greater than H01a; then, the value of i is 4, the value of i-1 is 3, the edge of the wafer stack is subjected to i-1=3 times of trimming, namely third trimming, and is cut onto the first dielectric layer 12 of the first wafer 1, so that a third step 204a is formed on the first dielectric layer 12 of the first wafer 1, namely, the horizontal step surface formed by the i-1=3 times of trimming is positioned in the dielectric layer between the m=2nd wafer 2 and the m-1=1st wafer 1, the product structure after the third trimming can be specifically seen in fig. 6, the width generated by the third trimming is W03a, the depth generated by the third trimming is H03a, wherein W03a is less than W02a and less than W01a, and H03a is more than H02a and more than H01a; after that, i takes a value of n=4, and the edge of the wafer stack is subjected to an i=n=4 trimming, that is, a fourth trimming, and cut onto the first substrate 11 of the first wafer 1, so as to form a fourth step 104a on the first substrate 11 of the first wafer 1, that is, a horizontal step surface formed by the i=n=4 trimming is located in the first wafer, the product structure after the fourth trimming can be specifically seen in fig. 3, the width generated by the fourth trimming is W04a, and the depth generated by the fourth trimming is H04a, where W04a < W03a < W02a < W01a, and H04a > H03a > H02a > H01a. It will be appreciated that the first to fourth trim will produce a progressively smaller trim width and a progressively larger trim depth. The minimum trimming width W04a generated in N times of trimming is not smaller than a preset threshold W0, and the maximum trimming depth H04a generated in N times of trimming is smaller than or equal to the thickness of the wafer stack; in this embodiment, w04 a=w0.
In another embodiment, the trimming process may sequentially trim from deep to shallow from the position of the wafer stack edge to a direction away from the position of the wafer stack edge, i.e., the trim width is changed from small to large and the trim depth is changed from large to small.
Specifically, in this embodiment, the width of the cut produced by the ith cut is greater than the width of the cut produced by the ith-1 st cut, and the depth of the cut produced by the ith cut is less than the depth of the cut produced by the ith-1 st cut, wherein 2.ltoreq.i.ltoreq.N.
Specifically, in this embodiment, when i=2, the i-1=1-th trimming produces a trimming depth between the thickness of the wafer stack and the thickness of the wafer stack remaining after the removal of the first wafer 1. That is, the first trimming produces a trimming depth between the thickness of the wafer stack and the thickness of the remaining wafer stack after the removal of the first wafer 1.
Specifically, in one embodiment, the horizontal step surface formed by the ith trimming is located in the dielectric layer between the mth wafer and the m-1 th wafer, where i=m; and when i=2, the horizontal step surface formed by the i-1 th trimming is located on the first substrate 11 of the first wafer 1, i.e., the horizontal step surface formed by the first trimming is located on the first substrate 11 of the first wafer 1. For example, when n=3, the horizontal step surface formed by the first trimming is located on the first substrate 11 of the first wafer 1, and the horizontal step surface formed by the second trimming is located in the dielectric layer between the second wafer 2 and the first wafer 1, specifically, on the first dielectric layer 12 of the first wafer 1; the horizontal step surface formed by the third trimming is located in the dielectric layer between the third wafer 3 and the second wafer 2, specifically, on the third dielectric layer 23 of the second wafer 2.
The following describes in detail one embodiment.
Referring to fig. 7 to fig. 9, fig. 7 is a schematic view of a product structure after first trimming an edge of a wafer stack according to another embodiment of the present application; fig. 8 is a schematic diagram of a product structure after performing a second trimming on an edge of a wafer stack according to another embodiment of the present application; fig. 9 is a schematic diagram of a product structure after performing a third trimming on an edge of a wafer stack according to another embodiment of the present application; specifically, when n=m=4, the value of i is 2, the value of i-1 is 1, the edge of the wafer stack is subjected to the i-1=1-time trimming, that is, the first trimming, and cut onto the first wafer 1, specifically, the first substrate 11 of the first wafer 1 may be cut onto the first substrate 11 of the first wafer 1 to form the first step 104b on the first substrate 11 of the first wafer 1, that is, the horizontal step surface formed by the i-1=1-time trimming is located in the m=1-th wafer, and the product structure after the first trimming can be specifically seen in fig. 7; the width generated by the first trimming is W01b, and the depth generated by the first trimming is H01b; then, i takes a value of 2, and based on the product shown in fig. 7, performing an i=2nd trimming, that is, a second trimming, in a direction from the first surface a toward the second surface B of the wafer stack, and cutting the product onto the first dielectric layer 12 of the first wafer 1 to form a second step 204B on the first dielectric layer 12 of the first wafer 1, that is, a horizontal step surface formed by the i=2nd trimming is located in the dielectric layer between the m=2nd wafer 2 and the m-1 st wafer 1, the product structure after the second trimming can be specifically seen in fig. 8, the width generated by the second trimming is W02B, and the depth generated by the second trimming is H02B, where W02B is greater than W01B, and H02B is less than H01B; then, i takes a value of 3, and based on the product shown in fig. 8, the product is continuously trimmed i=3 times, namely, a third trimming is performed in the direction from the first surface a to the second surface B of the wafer stack, and is cut onto the third dielectric layer 23 of the second wafer 2, so that a third step 304B is formed on the third dielectric layer 23 of the second wafer 2, namely, the surface of the horizontal step formed by the i=3 th trimming is located in the dielectric layer between the m=3 th wafer 3 and the m-1=2 th wafer 2, and the structure of the product after the third trimming can be seen in fig. 9 specifically; the third trimming has a width W03b and a depth H03b, wherein W03b is greater than W02b and greater than W01b, and H03b is less than H02b and less than H01b. After the third trimming, i has a value of 4, and based on the product shown in fig. 9, continuing to perform the i=4 th trimming, that is, the fourth trimming, in the direction from the first surface a toward the second surface B of the wafer stack, and cutting onto the third dielectric layer 33 of the third wafer 3, so as to form a fourth step 404B on the third dielectric layer 33 of the third wafer 3, that is, the horizontal step surface formed by the i=4 th trimming is located in the dielectric layer between the m=4 th wafer and the m-1=3 th wafer, and the structure of the product after the fourth trimming can be seen in fig. 3; the fourth trimming has a width W04b and a depth H04b, wherein W04b is greater than W03b and W02b is greater than W01b, and H04b is less than H03b and H02b is less than H01b; it will be appreciated that the first to fourth trim will produce progressively larger widths and progressively smaller depths of the trim. The minimum trimming width W01b generated in the N times of trimming is not smaller than a preset threshold W0, and the maximum trimming depth H01b generated in the N times of trimming is smaller than or equal to the thickness of the wafer stack; in this embodiment, w01b=w0.
Of course, in other embodiments, a random cut may also be made; see in particular fig. 10 and 11; fig. 10 is a schematic diagram of a product structure after performing a second trimming on an edge of a wafer stack according to another embodiment of the present application; FIG. 11 is a schematic view of a product structure after a third trimming of an edge of a wafer stack according to another embodiment of the present application; when n=m=4, the edge of the wafer stack is trimmed for the first time and cut onto the first wafer 1, specifically, onto the first substrate 11 of the first wafer 1, so as to form a first step on the first substrate 11 of the first wafer 1, and the product structure after trimming can be seen in fig. 7; then, a second trimming is performed from the first surface a toward the second surface B of the wafer stack based on the product shown in fig. 7, and the product is cut onto the third dielectric layer 33 of the third wafer 3 to form a second step 404c on the third dielectric layer 33 of the third wafer 3, and the structure of the product after the second trimming is specifically shown in fig. 10; then, continuing to trim the product in the direction from the first surface a to the second surface B of the wafer stack for the third time based on the product shown in fig. 10, and cutting the product onto the first dielectric layer 12 of the first wafer 1 to form a third step 204c on the first dielectric layer 12 of the first wafer 1, wherein the product structure after the third trimming can be seen in fig. 11; after the third trimming, a fourth trimming is performed based on the product shown in fig. 11, which is continued from the first surface a toward the second surface B of the wafer stack, and is cut onto the third dielectric layer 23 of the second wafer 2, so as to form a fourth step on the third dielectric layer 23 of the second wafer 2, and the structure of the product after the fourth trimming is specifically shown in fig. 3.
Step S13: and forming a filling layer at the edge of the wafer stack, wherein the filling layer at least fills N steps of the wafer stack.
Specifically, referring to fig. 12, fig. 12 is a schematic diagram of the product structure after the processing in step S13 in fig. 1 according to an embodiment of the present application; specifically, a glue layer is coated on the edge of the wafer stack, and the glue layer fills at least N steps of the wafer stack to form a filling layer 16 covering the N steps; the edge of the wafer stack is provided with a plurality of steps, so that the surface tension of the steps of the wafer stack is greatly increased, the covering capability of the adhesive layer on the steps of the wafer stack is effectively improved, the adhesive layer can better cover a plurality of steps of the wafer stack, the top surface of the filling layer 16 is not lower than the first surface A of the wafer stack, and the problem that part of the steps are not filled with the adhesive layer is avoided. Meanwhile, the concave-convex points on the first surface A of the wafer stack are covered and protected by the adhesive layer, so that the surface of one side of the adhesive layer, which is far away from the wafer stack, is parallel to the second surface B of the wafer stack, and the problem of breakage in the thinning process is further avoided.
Specifically, the specific embodiment of coating the glue layer on the edge of the wafer stack may take part in the specific embodiment of coating the glue layer on the step in the prior art, and the same or similar technical effects may be achieved, which will not be described herein.
Step S14: the second surface of the wafer stack is thinned.
Specifically, referring to fig. 13, fig. 13 is a schematic diagram of the product structure after the treatment in step S14 in fig. 1 according to an embodiment of the present application; specifically, the second surface B of the wafer stack is thinned, that is, the substrate 11 of the first wafer 1 is thinned, and specifically, the thinned thickness is not greater than the thickness between the step closest to the second surface B of the wafer stack and the second surface B of the wafer stack.
In the specific implementation process, the thinning process can adopt coarse grinding and then fine grinding; specifically, the coarse grinding can be performed quickly by using a coarse grinding machine, and the fine grinding can be performed by using a chemical mechanical grinding process.
In the specific implementation process, the filling layer 16 is removed after the treatment in the step S14, and then steps such as packaging, cutting and the like are performed to form a multi-layer wafer; specifically, the specific process flow after step S14 is the same as or similar to the related process flow in the prior art, and the same or similar technical effects can be achieved, and specific reference may be made to the prior art, and details are not repeated herein.
In another embodiment, referring to fig. 14, fig. 14 is a schematic structural view of a filling layer with a protective film disposed on a surface of the filling layer far from a wafer stack according to an embodiment of the present application; in order to protect the circuit on the first surface a of the wafer stack during the thinning process, a protective film 17 may be further provided on a side surface of the filling layer 16 remote from the wafer stack before thinning, and then the thinning process is performed; this enables protection of the circuit on the surface of the side of the mth wafer away from the M-1 th wafer during the thinning process, where m=m; wherein, the protective film 17 can cover the whole filling layer 16 and is far away from the surface of one side of the m-th wafer; and in one embodiment, the protective film 17 may be an adhesive tape; then sequentially removing the protective film 17 and the filling layer 16, and performing subsequent process operations; the specific implementation process of removing the filling layer 16 and the protective film 17 may refer to the specific implementation process of removing the filling layer 16 on the step of the wafer stack in the prior art, and may achieve the same or similar technical effects, and may refer to the prior art specifically, and will not be described herein.
According to the preparation method of the multilayer wafer, M wafers bonded in sequence are provided to form a wafer stack, and then the edge of the wafer stack is trimmed N times from the first surface A of the wafer stack to the second surface B of the wafer stack, so that N steps are formed on the edge of the wafer stack; then, forming a filling layer 16 at the edge of the wafer stack, wherein the filling layer 16 at least fills N steps of the wafer stack; finally, thinning the second surface B of the wafer stack; the method comprises the steps that the width of the trimming edges generated by N times of trimming is gradually decreased and the depth of the trimming edges generated by N times of trimming is gradually increased from the first surface A of the wafer stack to the second surface B of the wafer stack, so that N steps are formed to be distributed in a step shape, the surface tension of the edge of the wafer stack is greatly increased, the covering capacity of a filling layer on the steps of the wafer stack is effectively improved, the filling layer can better cover the N steps, and the probability of breakage of the wafer stack at the steps due to uneven stress in the thinning process is greatly reduced; in addition, by enabling the minimum trimming width generated by N times of trimming to be not smaller than a preset threshold value, the positions where defects exist on the edges of the wafer stack can be effectively cut off.
The foregoing is only the embodiments of the present application, and therefore, the patent scope of the application is not limited thereto, and all equivalent structures or equivalent processes using the descriptions of the present application and the accompanying drawings, or direct or indirect application in other related technical fields, are included in the scope of the application.
Claims (9)
1. A method of preparing a multi-layer wafer, comprising:
providing M wafers bonded in sequence to form a wafer stack, the wafer stack having first and second surfaces opposite;
trimming the edge of the wafer stack from the first surface of the wafer stack toward the second surface of the wafer stack N times to form N steps on the edge of the wafer stack; the width of the cutting edge generated by the ith cutting edge in the N times of cutting edges is smaller than that of the cutting edge generated by the jth cutting edge in the N times of cutting edges, and the depth of the cutting edge generated by the ith cutting edge is larger than that of the cutting edge generated by the jth cutting edge; the minimum trimming width generated in the N times of trimming is not smaller than a preset threshold value, and the maximum trimming depth generated in the N times of trimming is smaller than or equal to the thickness of the wafer stack;
forming a filling layer at the edge of the wafer stack, wherein the filling layer at least fills N steps of the wafer stack;
thinning the second surface of the wafer stack; wherein M, N is a natural number greater than 1, i+.j;
the m-th wafer in the wafer stack comprises a substrate, a dielectric layer positioned on one side surface of the substrate and a metal layer embedded in the dielectric layer;
bonding the mth wafer with the (m-1) th wafer through the dielectric layer of the mth wafer; and M is more than or equal to 2 and less than or equal to M, and the value of M is gradually decreased from the first surface of the wafer stack to the second surface of the wafer stack.
2. The method of claim 1, wherein trimming the edge of the wafer stack N times from the first surface of the wafer stack toward the second surface of the wafer stack to form N steps on the edge of the wafer stack specifically comprises:
the width of the cutting edge generated by the ith cutting edge is smaller than that of the cutting edge generated by the ith-1 cutting edge, and the depth of the cutting edge generated by the ith cutting edge is larger than that of the cutting edge generated by the ith-1 cutting edge, wherein i is more than or equal to 2 and less than or equal to N.
3. The method of claim 2, wherein the last trimming produces a trim depth between the thickness of the wafer stack and the thickness of the wafer stack remaining after the first wafer is removed.
4. A method of preparing a multi-layered wafer according to claim 3 wherein n=m, the horizontal step surface formed by the i-1 th trimming is located in the dielectric layer between the M-th wafer and the M-1 th wafer; wherein, (i-1) + (M-1) =m;
when i=n, the horizontal step surface formed by the ith trim is located in the first wafer.
5. The method of claim 1, wherein trimming the edge of the wafer stack N times from the first surface of the wafer stack toward the second surface of the wafer stack to form N steps on the edge of the wafer stack specifically comprises:
the width of the cutting edge generated by the ith cutting edge is larger than that of the cutting edge generated by the ith-1 cutting edge, and the depth of the cutting edge generated by the ith cutting edge is smaller than that of the cutting edge generated by the ith-1 cutting edge, wherein i is more than or equal to 2 and less than or equal to N.
6. The method of claim 5, wherein the i-1 st trimming step produces a trim depth between the thickness of the wafer stack and the thickness of the wafer stack remaining after the first wafer is removed when i = 2.
7. The method of claim 6, wherein n=m, the horizontal step surface formed by the ith trim is located in the dielectric layer between the mth wafer and the M-1 th wafer, where i=m;
when i=2, the horizontal step surface formed by the i-1 st trimming is located in the first wafer.
8. The method of claim 1, wherein the step of forming a filling layer at an edge of the wafer stack, the filling layer filling at least N steps of the wafer stack specifically comprises:
and coating a glue layer on the edge of the wafer stack, wherein the glue layer at least fills N steps of the wafer stack.
9. The method of claim 8, wherein the step of forming a filling layer at an edge of the wafer stack, the filling layer filling at least N steps of the wafer stack, before the step of thinning the second surface of the wafer stack, further comprises:
and arranging a protective film on the surface of one side of the filling layer, which is far away from the wafer stack.
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