CN106531638B

CN106531638B - Semiconductor device including stacked semiconductor bare chip and method of manufacturing the same

Info

Publication number: CN106531638B
Application number: CN201510578162.8A
Authority: CN
Inventors: 邱进添; S.K.厄帕德海尤拉; 俞志明
Original assignee: Shengdai Semiconductor (shanghai) Co Ltd; Shengdai Information Technology (shanghai) Co Ltd
Current assignee: Shengdai Semiconductor (shanghai) Co Ltd; Shengdai Information Technology (shanghai) Co Ltd
Priority date: 2015-09-11
Filing date: 2015-09-11
Publication date: 2020-02-07
Anticipated expiration: 2035-09-11
Also published as: CN106531638A

Abstract

A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor includes a plurality of semiconductor die stacked as a one-dimensional block of semiconductor die, and conductive patterns formed along edges of the one-dimensional block to electrically couple the semiconductor die in the one-dimensional block to each other and to an external electrical connector. In a further example, the one-dimensional blocks may be mounted to each other to form a two-dimensional semiconductor block and a three-dimensional semiconductor block.

Description

Semiconductor device including stacked semiconductor bare chip and method of manufacturing the same

Technical Field

The present invention relates to a semiconductor device including stacked semiconductor bare chips and a method of manufacturing the same.

Background

The strong growth in demand for portable consumer electronics has driven the demand for high capacity storage devices. Non-volatile semiconductor memory devices, such as flash memory cards, are being widely used to meet the ever-increasing demand for digital information storage and exchange. Their portability, versatility and rugged design, along with their high reliability and large capacity, make such storage devices ideal for use in a wide variety of electronic devices, including, for example, digital cameras, digital music players, video game consoles, PDAs and mobile telephones.

Although a wide variety of packaging configurations are known, flash memory cards can typically be fabricated as system-in-package (SIP) or multi-die modules (MCM) in which multiple die are mounted and interconnected on a small footprint (footprint) substrate. The substrate may typically comprise a rigid, dielectric base, which is etched on one or both sides with a conductive layer. An electrical connection is formed between the die and the conductive layer, and the conductive layer provides an electrical connection structure to connect the die to a host device. Once the electrical connections between the die and the substrate are established, the assembly is typically encapsulated in a molding compound to provide a protective package.

Fig. 1 shows a cross-sectional side view of a conventional semiconductor package 20. A typical package includes a plurality of semiconductor die, such as a flash die 22 and a controller die 24, supported on a substrate 26. The substrate 26 includes vias 30, electrical traces 32, and contact pads 34 to transmit signals between the semiconductor die 22, 24 and a host device in which the package is located. Die bond pads (not shown) may be formed on the surfaces of the die 22, 24 to electrically couple the semiconductor die to the substrate by securing wire bonds between corresponding die bond pads and the contact pads 34. Once all electrical connections are made, the die and wire bonds may be encapsulated in a molding compound 36 to encapsulate the package and protect the die and wire bonds.

There is an increasing demand to increase storage capacity while maintaining or reducing the device form factor of semiconductor packages. This need can be partially met by fabricating elements such as smaller and thinner semiconductor die. However, if significant progress is to be made in terms of greater storage capacity with the same or smaller form factor, a thorough redesign of conventional semiconductor packages is required.

Disclosure of Invention

In general, examples of the present technology relate to a method of forming a semiconductor device, including: (a) forming a plurality of semiconductor die on one or more semiconductor wafers; (b) dicing the plurality of semiconductor die from the one or more semiconductor wafers at least in part by an invisible laser technique that forms a hole at a depth in the middle of the one or more semiconductor wafers, the wafer being diced such that dicing edges of the plurality of semiconductor die have electrical contacts; (c) stacking the plurality of semiconductor die on top of each other using a die attach film between corresponding semiconductor die in the stack to form a block, edges of the plurality of semiconductor die being aligned to a common edge of the block; (d) applying pressure to the surface of the block to remove air bubbles; and (e) forming a conductive pattern on a common edge of the block to electrically couple the plurality of semiconductor die in the block to each other and to an external electrical connector.

In other examples, the present technology relates to a method of forming a semiconductor device, comprising: (a) forming a plurality of semiconductor die on one or more semiconductor wafers, including forming a plurality of die bond pads in the plurality of semiconductor die; (b) dicing the plurality of semiconductor die from the one or more semiconductor wafers at least in part by an invisible laser technique that forms a hole at a depth intermediate the one or more semiconductor wafers, the dicing step comprising the step of dicing the plurality of contact pads in the plurality of semiconductor die such that the plurality of contact pads are exposed at edges of the plurality of semiconductor die; (c) stacking a plurality of first semiconductor die in a first direction down to form a one-dimensional block using die attach films between corresponding ones of the plurality of first semiconductor die in the stack, edges of the plurality of first semiconductor die aligned to a common edge of the one-dimensional block; (d) forming a conductive pattern on the common edge that connects to a plurality of contact pads at an edge of the plurality of first semiconductor die at the common edge; and (e) separating the one-dimensional blocks into a plurality of smaller semiconductor blocks.

In another example, the present technology relates to a method of forming a semiconductor device, comprising: (a) forming a plurality of semiconductor die on one or more semiconductor wafers, including forming a plurality of electrical contacts on the plurality of semiconductor die; (b) dicing the plurality of semiconductor die from the one or more semiconductor wafers at least in part by an invisible laser technique, the invisible laser forming a hole at a depth intermediate the one or more wafers, the dicing of the plurality of semiconductor die exposing the plurality of electrical contacts to edges of the plurality of semiconductor die; (c) arranging the plurality of semiconductor die side by side along a second direction which is overlapped in a first direction and is orthogonal to the first direction to form a two-dimensional block, wherein the edges of the plurality of semiconductor die in the two-dimensional block are aligned with the common edge of the two-dimensional block; (d) applying isostatic pressure to the surface of the two-dimensional block to remove air bubbles; (e) forming a conductive pattern on a common edge of the two-dimensional block to electrically couple at least some electrical contacts of the plurality of semiconductor die in the two-dimensional block to each other; and (f) separating the two-dimensional module into smaller units, each unit including two or more semiconductor die.

Drawings

Fig. 1 is a prior art side view of a conventional semiconductor device including a semiconductor die mounted on a substrate.

Fig. 2 is a prior art top view of a conventional semiconductor device including a semiconductor die mounted on a substrate.

Fig. 3 is a flow chart of forming a semiconductor die according to an embodiment of the invention.

Fig. 4 is a front view of a semiconductor wafer showing a first major surface of the wafer.

Fig. 5 is a rear view of the semiconductor wafer showing the second major surface of the wafer. .

Fig. 6 is a perspective view of a single semiconductor die 256 from a wafer.

FIG. 7 is an enlarged perspective view of a portion of a wafer 250 undergoing a stealth laser process

Fig. 8 and 9 are perspective views of a single semiconductor die 256 from a wafer undergoing an invisible laser process.

Fig. 10 is a perspective view of a single semiconductor die 256 from a wafer during a back side grinding process.

Fig. 11 is a top view of a portion of a wafer separated after dicing.

Fig. 12 is a perspective view of a stacked block of semiconductor die in accordance with embodiments of the present technology.

FIG. 13 is a flowchart showing further details of step 220 of the flowchart of FIG. 3.

Fig. 14-16 illustrate a semiconductor device in various steps of forming stacked semiconductor tiles in accordance with embodiments of the present technique.

Fig. 17 is a flow chart of forming an array of stacked semiconductor tiles in accordance with further embodiments of the present technique.

Fig. 18-22 illustrate a semiconductor device in various steps of forming an array of stacked semiconductor tiles in accordance with embodiments of the present technique.

FIGS. 23-25 illustrate a semiconductor device in various steps of forming an array of stacked semiconductor tiles in accordance with further embodiments of the present technique

Detailed Description

The present technology will now be described with reference to the accompanying drawings, in which embodiments relate to a semiconductor device including a semiconductor bare chip block formed in a precision manufacturing process. The semiconductor die are formed with precise edges and in a bubble-removing manner so that the die can be closely and uniformly stacked on top of and/or beside each other.

It is understood that the present invention may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the invention to those skilled in the art. Indeed, the invention is intended to cover alternatives, modifications and equivalents of these embodiments, which are included within the scope and spirit of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without these specific details.

The terms "top" and "bottom", "upper" and "lower", and "vertical" and "horizontal" may be used herein for convenience and illustrative purposes only, and are not intended to limit the description of the invention since the articles referred to may be interchanged in position and orientation. Also, the terms "substantially" and/or "about" as used herein mean that a particular dimension or parameter may vary within acceptable manufacturing tolerances for a given application. In one embodiment, the acceptable manufacturing tolerance is ± 0.25%.

Embodiments of the present invention will now be explained with reference to the flow diagrams of fig. 3, 13 and 17, and the views of fig. 4-12, 14-16 and 18-25. First, referring to the flowchart of fig. 3 and the views of fig. 4-11, a semiconductor wafer 250 may initially be a wafer sheet ingot that may be formed in step 200. In one example, the ingot from which the wafer 250 is formed may be formed of single crystal silicon grown according to a Czochralski (CZ) method or a Float Zone (FZ) method process. However, other materials and processes may be used to form wafer 250 in other embodiments.

In step 204, a semiconductor wafer 250 may be cut from the ingot and polished to provide a smooth surface, both a first major surface 252 (fig. 4) and a second major surface 254 (fig. 5) opposite surface 252. In step 206, the first major surface 252 can be subjected to various process steps to singulate the wafer 250 into individual semiconductor die 256 (one of which is shown in fig. 4) and form integrated circuits of the individual semiconductor die 256 on and in the first major surface 252. These various processes may include a metallization step that deposits a metal layer in the integrated circuit, the metal layer including a plurality of metal contacts that transmit signals to and from the integrated circuit. The electrical contacts may include die bond pads 258 (one of which is numbered in fig. 4 and 6, respectively) exposed at the first major surface 252. In an embodiment, die bond pads 258 may be formed of aluminum or alloys thereof, although pads 258 may be formed of other materials in other embodiments. In an embodiment, the integrated circuit may store the semiconductor die as a NAND flash memory, but other types of integrated circuits are also contemplated.

In accordance with some aspects of the present technique, after dicing as explained below, a plurality of stacked semiconductor die 256 may be stacked and electrically connected to each other along at least one edge of the semiconductor die 256 (fig. 6). Accordingly, in one embodiment, die bond pads 258 may extend to and terminate at an edge 260 of each semiconductor die in wafer 250. In the embodiment shown in fig. 6, the electrical connection may further include a low profile tie bar, generally referred to herein as lead 262. Wire 262 may be bonded to each die bond pad 258 and bent to extend to edge 260. Fig. 6 shows the die 256 after dicing as explained below. The leads 262 may be formed of gold, for example, but may be formed of other materials in other examples. In further embodiments, redistribution pads (not shown) may be formed at edge 260 and electrically connected to die bond pads 258 in a known manner. Fig. 6 shows die bond pads 258 and leads 262 formed on a single edge 260 of semiconductor die 256. It should be understood, however, that die bond pads 258 and/or leads 262 may be formed around two, three, or four edges of semiconductor die 256.

In accordance with aspects of the present technique, tie bar leads 262 (as indicated by the dashed lines around step 208 in fig. 3) may be omitted and the wafer diced by a stealth laser process such that die bond pads 258 are exposed to edge 260. In step 212, an invisible laser process can be used in conjunction with back grinding of the wafer 250 and/or tape stretching as explained below to very cleanly and accurately slice the wafer 250 into individual semiconductor die 256 and expose a portion of the die bond pads to the edges of the corresponding semiconductor die.

Referring now to fig. 7, a wafer 250 may be supported by a jig or other support surface (not shown) with the integrated circuits on the first major surface 252 facing the support surface and the second major surface 254 facing away from the support surface. The laser 264 may then emit a pulsed laser beam 266 of a wavelength (e.g., infrared or near infrared wavelength) that is transmitted through the second major surface of the wafer 250. The pulsed laser beam may be focused at a point below the surface 254 of the wafer by an optical system, for example, including one or more collimating lenses 268. When the laser beam reaches a peak power density at the focal point, the wafer absorbs energy and creates a fine aperture 270.

The laser can be moved along rows and columns in the horizontal plane of the wafer and activated at multiple points such that a plurality of closely spaced fine apertures 270 are formed at an intermediate depth of the wafer (between the first surface 252 and the second surface 254 of the wafer). The rows and columns of apertures 270 define the final shape of each semiconductor die 256 cut from the wafer 250. The laser may form a single layer of fine holes 270 (at a single depth) as shown in fig. 8. Alternatively, the laser may form multiple (two or more) layers of fine holes 270 at multiple depths, as represented in FIG. 9. Although fig. 8 and 9 appear to show the diced semiconductor die 256, the die 256 may still be part of the wafer 250 when performing the stealth laser process.

This method of wafer dicing provides advantages over conventional blade dicing and laser surface ablation dicing. The latter two dicing techniques can cause chipping, flaking and wafer contamination along the dicing lines, resulting in semiconductor die with rough edges. As explained below, semiconductor die in accordance with the present technology can have their edges 260 aligned with each other in a stack of semiconductor die 256, while any such rough edges can interfere with a smooth, clean, and tight interface between adjacent semiconductor die. The wafer dicing method described above allows the multiple die 256 to be stacked such that the edges 260 together form a very smooth surface of the stacked semiconductor tiles without cracks or chip defects. Additionally, the blades and laser surface ablation dicing can crush the wafer material along the dicing lines, resulting in relatively large kerf widths. The stealth laser shown in fig. 7-11 has a very narrow kerf, providing more space on the wafer for the semiconductor die 256, and higher production yield.

After the stealth laser step 212, the wafer 250 may still be a single sheet. The wafer may then be thinned in step 214, applied to second major surface 254 using a grinding wheel (not shown) to back grind the wafer from, for example, 780 μm to 280 μm, although these thicknesses are for exemplary purposes only and may vary in different embodiments.

Referring to fig. 10, in addition to thinning the wafer 250, vibrations from the back grinding step may cause cracks 272 that propagate from the fine holes 270 toward the first and second

major surfaces

252, 254 of the wafer 250 to complete the dicing of the wafer 250. In other embodiments, the wafer 250 may remain as a single piece after the backgrinding step 214. This is probably because the backgrinding process does not cause cracks propagating from the fine holes. This may also be due to the fact that, in an embodiment, the backgrinding step 214 may be performed before the stealth laser step 212.

After the stealth laser and backgrind steps, the wafer may be flipped over and the second major surface secured to a tape 274 (fig. 11 shows a portion of the tape 274) with the wafer remaining as a single piece. The ribbon may then be stretched along a vertical axis in step 216. This creates stress in the wafer that causes cracks to propagate from the fine holes 270 toward the first and second

major surfaces

252, 254 of the wafer 250 to complete the dicing of the wafer 250. The stretching also separates the diced semiconductor die 256 on the tape as shown in fig. 11. In embodiments where the wafer is diced after the backgrinding step, the pick-and-place robot may transfer the diced semiconductor die 256 to a support surface, such as tape 274 shown in fig. 8, to continue further processing as explained below.

In accordance with one aspect of the present technique, the stealth laser and subsequent propagation of crack 272 may cause dicing of the wafer along a line through die bond pad 258. As crack 272 propagates, die bond pad 258 is severed. Thus, as shown in the partial top view of fig. 11, active portion 258a of die bond pad 258 is exposed at edge 260 of corresponding semiconductor die 256. The remaining portion 258b of die bond pad 258 remains in edge 276 of the next adjacent semiconductor die 256 (the next adjacent semiconductor die 256 also has an active portion 258a in edge 260 opposite edge 276). Electrical connections to die bond pads 258 in die 256 are established to active portion 258 a. The remaining portion 258b in each semiconductor die 256 remains electrically isolated.

A plurality of semiconductor wafers 250 may be fabricated according to steps 200-216 as explained above. Thereafter, in step 218, as shown in fig. 12, the pick-and-place robot may pick up the semiconductor die 256 from the same or different wafer and stack it into a stack block 280 of semiconductor die 256. The stacked block 280 may be referred to herein as a semiconductor device 280. Edges 260 of active portion 258a including die bond pads 258 may be aligned along a common side to form edge 282 of stacked block 280.

The semiconductor die 256 may be stacked and secured to each other in the stacked semiconductor 280 using a Die Attach Film (DAF) layer between corresponding semiconductor die 256. The number of semiconductor die in a single stacked block 280 can vary in embodiments from 2 to 32 (or more) semiconductor die 256, including, for example, 4, 8, or 16 semiconductor die.

In step 220, conductive patterns of electrical traces may be formed on the edges 282 of the stacked semiconductor tiles 280. The flowchart of fig. 13 and the views of fig. 14-16 show further details of step 220. The view of FIG. 15 shows a conductive pattern 288 formed on a single edge 282 of stacked block 280. It should be understood, then, that conductive patterns 288 may be formed around two, three, four, five, or six sides of stacked block 280.

As described above, one of die bond pads 258, one of which is numbered in fig. 14, is exposed at edge 282. In step 350, the edge 282 can receive an electrically insulating layer to prevent shorting between the conductive pattern formed thereon and the semiconductor die 256 in the block 280. For example, in step 350, an electrically insulating layer 284, such as silicon oxide or silicon nitride, may be sputtered over the edge 282. In other embodiments, the insulating layer 284 can be formed of other electrical insulators and can be applied by other thin film deposition techniques. The insulating layer 284 may be less than 1 μm, but may be thicker in other embodiments.

In step 354, electrically insulating layer 284 may be processed to expose the ends of die bond pads 258 to edge 282, as shown in fig. 14. In embodiments where tie bar leads 262 are formed, the ends of leads 262 may be exposed at edge 282. Layer 284 may be treated to expose the ends of pads 258 (or leads 262), for example, by laser or chemical etching.

In step 358, a conductive layer may be applied over the insulating layer 284. The conductive layer may be formed, for example, of titanium, nickel, copper, or stainless steel sputtered over the insulating layer 284. In other embodiments, the conductive layer may be formed of other electrical conductors and may be applied by other thin film deposition techniques. The conductive layer may have a thickness of 2-5 μm, but may be thicker or thinner than this in other embodiments. Annealing heat is optionally performed to remove the metallic grain states in the conductive layer.

In step 360, the conductive layer may be processed to remove a portion of the layer and leave a conductive pattern 288 (fig. 15). The conductive patterns may connect the ends of selected pads of different semiconductor die 256 to each other and to external electrical connectors, such as solder balls as explained below. For example, a known photolithography process may be performed to apply a photoresist layer on the conductive layer, expose and develop the photoresist through a mask having a pattern of the final metal traces, etch away the unexposed portions to leave the metal traces with the conductive pattern 288, and then remove the photoresist on the metal traces. In other embodiments, the conductive pattern 288 may be formed by other photolithographic or non-photolithographic processes. One additional technique is screen printing of conductive traces in the shape of conductive patterns 288.

The particular conductive pattern shown in fig. 15 is for exemplary purposes only and varies in further embodiments. As noted, in other embodiments, conductive patterns such as pattern 288 may be formed around two or more sides (whether or not these sides have pads 258). Additionally, electrical traces 290 may be formed on the upper and/or lower surfaces of semiconductor device 280, for example, in connection with conductive patterns on the sides, or in connection with integrated circuit 292. The traces 290 may be formed by photolithography, screen printing, or other processes. As described above, the very smooth and highly aligned edges of the die 256 on the edge surface 282 allow the traces 290 to be formed without any breaks or other problems with the traces.

Referring again to the flowchart of fig. 3, in step 226, external electrical connectors 296 (one of which is numbered in the bottom view of fig. 16) are defined to form the complete stacked semiconductor block 280. For example, where semiconductor device 280 is soldered to a motherboard of a host device as a BGA package, the external electrical connectors may be solder balls that secure redistribution pads (or other contact pads) on the bottom surface of semiconductor device 280. The external electrical connectors may alternatively be contact fingers on the bottom surface of the semiconductor device 280. For fine pitch (e.g., pitches less than 350 μm) connectors, the electrical connectors 296 may be bumps formed by, for example, wet chemical plating.

The flow diagram of fig. 17 and the views of fig. 18-25 illustrate additional embodiments of the present technology that form a 2D array of semiconductor tiles 380 or a 3D array of semiconductor tiles 480 as explained below. The 2D and 3D semiconductor tiles are collectively referred to herein as multi-dimensional tiles. In step 200-. Semiconductor die are formed from a wafer and stacked. For example, steps 300-316 may be the same steps as steps 200-216 described above.

In step 330, the semiconductor die may be stacked in a 2D or 3D array. For example, as shown in fig. 18, individual semiconductor die 256 can be stacked vertically (y-direction) and/or horizontally (x-direction) on support plate 278 to form a 2D array of semiconductor die 380. The 2D array of semiconductor die 256 may also be referred to herein as a semiconductor device 380. Instead of individual semiconductor die, semiconductor device 380 can be formed from stacked semiconductor tiles 280 (e.g., formed and shown in fig. 12, prior to formation of traces 288) stacked vertically and/or horizontally on support plate 278, as shown in fig. 19.

When semiconductor die are stacked in two dimensions (on top of each other and side-by-side), it should be understood that support plate 278 can support semiconductor die in multiple directions. Support plate 278 can support an array of semiconductor die 380 from a bottom surface (as shown in fig. 18). Support plate 278 may instead be a horizontal plate that supports the array of semiconductor die from a surface lying in the x-y plane of fig. 18 (i.e., a back surface not visible from the view of fig. 18 that is opposite the surface that includes pads 258). The support plate 278 may instead be a horizontal plate that extends from a surface perpendicular to the x-direction of fig. 18 (i.e., into and out of the page, the surface on the right side of the view of fig. 18). In addition to support plate 278, a second guide plate (not shown) may be provided that extends vertically upward over support plate 287 to aid in further alignment of semiconductor die 256 as they are stacked in array 302.

In positioning semiconductor die 256 one above the other in the y-direction and side-by-side with each other in the x-direction, DAF may be used between adjacent semiconductor die 256. As explained below, once the electrical traces are formed on one or more edge surfaces of the 2D array of semiconductor die, the array can be separated into separate stacked semiconductor tiles 280 (e.g., as shown in fig. 15). Accordingly, two different DAF layers may be used. The first DAF layer 302 (some of which are numbered in fig. 18 and 19) may be used between the semiconductor die 256, with the semiconductor die 256 still remaining bonded to each other in the respective stacked semiconductor tiles 280 after the tiles 280 are separated from the 2D tiles 380. The second DAF layer 304 (some of which are numbered in fig. 18 and 19) may be used between semiconductor die that will be separated from each other after the separation of block 280 from the 2D block 380. The differences between the first DAF layer 302 and the second DAF layer 304 will be explained below.

The particular configuration in fig. 18 and 19 is for example purposes only, and the 2D semiconductor tile 380 may have fewer or more semiconductor die or stacked tiles 280 in the x-direction and/or y-direction. In the case of forming a stacked block 280 as shown in fig. 19, the stacked block 280 may have fewer or more semiconductor die 256 than shown in fig. 19.

In order to stack the semiconductor die 256 side-by-side with each other in the x-direction (whether individual or in blocks) it is important to have the edge surfaces of the corresponding semiconductor die 256 fit closely and cleanly to each other. The present technology accomplishes this in a number of ways. First, as explained above, using the stealth laser process to dice individual semiconductor die ensures smooth, precise edges of the semiconductor die 256 and allows corresponding semiconductor die 256 in a single stacked semiconductor tile 280 to be precisely aligned with each other. Similarly, the aligned edges allow for the stacked semiconductor tiles in the 2D semiconductor tile 380 to be closely and precisely aligned with each other.

Alternatively, the corresponding semiconductor tiles 280 may be precisely aligned to ensure that there are no bubbles in the DAF layer between the x-direction and y-direction corresponding dies 256 in the 2D semiconductor tiles 380. These bubbles may otherwise cause separation of the semiconductor die 256 in the 2D semiconductor tile 380. In accordance with aspects of the present technique, the bubbles may be removed, for example by applying isostatic pressure to the 2D semiconductor block 380 in step 334. For example, the 2D semiconductor tile 380 may be immersed in an isostatic pressing liquid (not shown) while the DAF layer between the dies is in the b-stage. This process simultaneously applies pressure (as indicated by the arrows on the corresponding surfaces in fig. 20) to all surfaces of the 2D semiconductor tiles to squeeze out bubbles to ensure that the corresponding stacked semiconductor tiles 280 are tightly bonded together. Pressure may be applied to the stacked semiconductor tiles 280 in the same manner as shown in fig. 9 after the tape 274 is removed.

In an example, the pressure applied by isostatic pressing may be between 2Mpa and 10Mpa, the temperature may be between 80 ℃ and 180 ℃, and the time is from a few seconds to about 1 minute. It should be understood that these parameters are for exemplary purposes only, and that in other embodiments each parameter may vary above or below these ranges. The working fluid of isostatic pressure may be water, but it may be other fluids in other embodiments. The DAF layer 302 (not 304) may be cured to a c-stage in an isostatic pressing process or a subsequent reflow process.

In an embodiment, the semiconductor die 256 in the 2D block 380 may be aligned in the same orientation in the 2D semiconductor block 380. Thus, for example, where die bond pads 258 terminate at a single edge of stacked semiconductor tile 280, pads 258 may all be exposed to the same edge 382 of 2D semiconductor tile 380, as shown in fig. 20. It is contemplated that in other embodiments, some pads 258 face one side and other pads 258 face the other side.

As shown in fig. 21, a conductive pattern 288 may then be formed in step 340 on the edge 382. Details of forming the conductive pattern 288 may be as described in the step of fig. 13 above. The particular conductive pattern 288 shown in fig. 21 is for exemplary purposes only and may vary in other embodiments. The conductive pattern 288 may be repeated on each stacked semiconductor tile 280. However, a given trace of the semiconductor pattern 288 may span and electrically connect die bond pads 258 from two or more stacked semiconductor tiles 280 in the semiconductor device 380.

In other embodiments, conductive patterns such as pattern 288 may be formed around two or more sides (whether or not those sides have die bond pads 258 exposed thereon). Additionally, electrical traces 290 may be formed on the top and/or bottom surfaces of the semiconductor device 380, such as to connect conductive patterns on the sides, or to connect the integrated circuit 292. The traces 290 may be formed by photolithography, screen printing, or other processes.

In step 344, the semiconductor devices 380 may be separated into stacked semiconductor tiles, such as stacked semiconductor tiles 280 shown in fig. 15. At some point prior to step 344, the DAF layer 302 may be hardened to a c-stage so that the die in a given stacked semiconductor tile 280 may fit closely together. In one embodiment, the DAF layer 304 remains a b-staged adhesive after the DAF layer is hardened. Thus, in step 344, the DAF layer 304 may be processed to remove the DAF layer 304, reduce the adhesive properties of the DAF layer 304, or overcome the force of the DAF layer holding the semiconductor tiles 280 together so that the tiles 280 may be separated by the 2D tiles 380.

The properties of the DAF layers 302 and 304 may be selected in a known manner such that the DAF layer 302 may be hardened while the DAF layer 304 does not. Additionally, the DAF layers 302 and 304 may be selected in a known manner such that the DAF layer 302 remains unaffected when the DAF layer 304 is processed to separate the corresponding blocks 280 from each other in step 344. The DAF layers 302 and 304 may be a variety of materials including, for example, polyester resins (polyester resins), vinyl ester resins (vinyl esters), or other resins, epoxy resins, phenolic compounds, or polyurethane compounds. The DAF layers 302 and 304 may further be bismaleimides (bismaleimides), PEAM-based adhesives, and mixtures of these chemistries. Other materials are also contemplated. In one embodiment, the DAF layer 304 may be a double-sided tape, wherein the adhesive decomposes under uv irradiation and/or application of heat. DAF layers 302 and 304 may be from Henkel, which has a business establishment at the domingous farm, California, USA.

It should be understood that other methods of separating the corresponding stacked semiconductor tiles 280 from the 2D tiles 380 may be used in addition to using two different DAF layers having different adhesion properties. For example, a single type of DAF may be used, but the DAF layer between the die to be separated from each other when the block 280 is separated may be selectively processed to decompose or reduce the adhesive properties of this portion of the DAF. In other embodiments, a single type of DAF may be used, and the corresponding stacked semiconductor tiles may be separated by cutting, such as with a saw blade.

In step 346, external electrical connectors 296 (one of which is numbered in the view of fig. 22) may be secured to corresponding surfaces of the stacked semiconductor tiles 280 as described above to complete the stacked semiconductor tiles 280.

The steps of the flow chart of fig. 17 may also be used to form the 3D semiconductor tile 480 shown in fig. 23-25. The 3D semiconductor tile 480 is also referred to herein as a semiconductor device 480. To form the 3D semiconductor tile 480, a plurality of the formed stacked semiconductor tiles 280 may be vertically stacked in the y-direction, horizontally aligned in the x-direction, and further aligned in the z-direction orthogonal to the y-direction and the x-direction. In the particular configuration shown, the semiconductor device 480 has a height of three stacked blocks 280 in the y-direction, a width of three stacked blocks in the x-direction, and a depth of two stacked blocks in the z-direction. However, it should be understood that more or fewer stacked blocks may be stacked/aligned in at least one of the x-direction, y-direction, and z-direction. 3D semiconductor tile 480 may be formed by stacking individual semiconductor die 256 in the x-direction, y-direction, and z-direction.

Fig. 23 can be a front view of a 3D semiconductor block 480 showing the edge 382 described above. The opposite edge 384 is not visible in the front view of fig. 23. Fig. 24 is a rear view of a 3D semiconductor block 480 with edge 384 visible and opposite edge 382 not visible. In some embodiments, an interface 388 may exist between corresponding stacked blocks 280 along the y-direction. The stacked blocks 280 along this interface 388 may be secured to each other using DAF layers as explained above, while any bubbles may be squeezed out of the interface 388, such as in the isostatic pressing process explained above. In some embodiments, the edge of the stacked semiconductor tiles 280 may be free of conductive patterns at the interface 388. However, in other embodiments, there may be a conductive pattern on one or more edges at interface 388 that may be embedded in the DAF layer between adjacent stacked blocks at interface 388.

The particular semiconductor pattern 288 on the

edges

382 and 384 shown in fig. 23 and 24 is for exemplary purposes only and may vary in other embodiments. In other embodiments, conductive patterns such as pattern 288 may be formed on one edge or around three or more sides (whether or not those sides have die bond pads 258 thereon). Additionally, electrical traces 290 may be formed on the top and/or bottom surface of the semiconductor device 480, such as to connect side conductive patterns, or to connect the integrated circuit 292. The traces 290 may be formed by photolithography, screen printing, or other processes.

After traces are formed on one or more edge surfaces of 3D semiconductor tiles 480, tiles 480 may be separated into individual stacked semiconductor tiles 280 and electrical connectors 296 may be secured to corresponding surfaces of stacked semiconductor tiles 280, as shown in fig. 25.

The semiconductor device according to any of the above described embodiments, wherein the semiconductor device comprises almost entirely a semiconductor die, provides an efficient space utilization. According to the present technology, a substrate and wire bonding, which occupy space in a conventional semiconductor device, are omitted. Additionally, the precise edges and contours of the semiconductor die in the semiconductor device allow for precise fitting of the semiconductor die in the device.

The foregoing detailed description of the invention has been presented for purposes of illustration and example. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. The scope of the invention is defined by the appended claims.

Claims

1. A method of forming a semiconductor device, comprising:

(a) forming a plurality of semiconductor die on one or more semiconductor wafers, including forming a plurality of die bond pads in the plurality of semiconductor die;

(b) dicing the plurality of semiconductor die from the one or more semiconductor wafers at least in part by an invisible laser technique that forms a hole at a depth intermediate the one or more semiconductor wafers, the dicing step comprising the step of dicing the plurality of contact pads in the plurality of semiconductor die such that the plurality of contact pads are exposed at edges of the plurality of semiconductor die;

(c) stacking a plurality of first semiconductor die in a first direction down to form a one-dimensional block using die attach films between corresponding ones of the plurality of first semiconductor die in the stack, edges of the plurality of first semiconductor die aligned to a common edge of the one-dimensional block;

(d) forming a conductive pattern on the common edge that connects to a plurality of contact pads at an edge of the plurality of first semiconductor die at the common edge; and

(e) the one-dimensional blocks are separated into a plurality of smaller semiconductor blocks.

2. The method of claim 1, further comprising the step of applying pressure on the surface of the one-dimensional block to remove air bubbles.

3. The method of claim 1, further comprising the step of placing a plurality of second semiconductor die alongside one another in a second direction orthogonal to the first direction using die attach films of corresponding ones of the plurality of second semiconductor die to form a two-dimensional block, edges of the plurality of semiconductor die being aligned to the common edge.

4. The method of claim 3, further comprising the step of applying pressure to the surface of the two-dimensional block to remove air bubbles.

5. The method of claim 1, said step (d) comprising mounting the plurality of one-dimensional blocks in a second direction orthogonal to the first direction and mounting the plurality of one-dimensional blocks in a third direction orthogonal to the first and second directions to form a multi-dimensional block comprising a three-dimensional block.

6. The method of claim 1, further comprising the steps of mounting a wafer of the one or more wafers on a tape, and stretching the tape so that holes formed by the stealth laser technology propagate toward the first and second major surfaces of the wafer to complete dicing of the semiconductor die from the wafer.

7. The method of claim 1, further comprising the step of back grinding the second major surface of one of the one or more wafers to thin the wafer, the wafer being back ground such that the holes formed by the stealth laser technique propagate toward the first and second major surfaces of the wafer to complete dicing of the semiconductor die from the wafer.

8. The method of claim 5, the conductive pattern on the common edge comprising at least a first conductive pattern, the method further comprising the step of forming at least a second conductive pattern on at least a second surface of the multi-dimensional block different from the common edge.

9. The method of claim 1, further comprising the step of securing a plurality of solder balls on the surface of the block as external electrical connectors.

10. The method of claim 1, further comprising the step of forming a plurality of contact fingers on a surface of the block as external electrical connectors.

11. A method of forming a semiconductor device, comprising:

(a) forming a plurality of semiconductor die on one or more semiconductor wafers, including forming a plurality of electrical contacts on the plurality of semiconductor die;

(b) dicing the plurality of semiconductor die from the one or more semiconductor wafers at least in part by an invisible laser technique, the invisible laser forming a hole at a depth intermediate the one or more wafers, the dicing of the plurality of semiconductor die exposing the plurality of electrical contacts to edges of the plurality of semiconductor die;

(c) arranging the plurality of semiconductor die side by side along a second direction which is overlapped in a first direction and is orthogonal to the first direction to form a two-dimensional block, wherein the edges of the plurality of semiconductor die in the two-dimensional block are aligned with the common edge of the two-dimensional block;

(d) applying isostatic pressure to the surface of the two-dimensional block to remove air bubbles;

(e) forming a conductive pattern on a common edge of the two-dimensional block to electrically couple at least some electrical contacts of the plurality of semiconductor die in the two-dimensional block to each other; and

(f) the two-dimensional block is separated into smaller units, each unit including two or more semiconductor die.

12. The method of claim 11, wherein step (c) comprises using die attach film between corresponding semiconductor die in the first and second directions.

13. The method of claim 11, said step (d) comprising immersing the two-dimensional block in isostatic pressure.

14. The method of claim 11, the conductive pattern on the common edge comprising at least a first conductive pattern, the method further comprising the step of forming at least a second conductive pattern on at least a second surface of the two-dimensional block different from the common edge.

15. The method of claim 11, further comprising the step of attaching a plurality of solder balls on the surface of the block as external electrical connectors.

16. The method of claim 11, further comprising the step of forming a plurality of contact fingers on a surface of the block as external electrical connectors.