CN106531638A - Semiconductor device comprising stacked semiconductor bare core blocks and manufacturing method of semiconductor device - Google Patents
Semiconductor device comprising stacked semiconductor bare core blocks and manufacturing method of semiconductor device Download PDFInfo
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- CN106531638A CN106531638A CN201510578162.8A CN201510578162A CN106531638A CN 106531638 A CN106531638 A CN 106531638A CN 201510578162 A CN201510578162 A CN 201510578162A CN 106531638 A CN106531638 A CN 106531638A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
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- Microelectronics & Electronic Packaging (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a semiconductor device and a manufacturing method thereof. A semiconductor comprises a plurality of semiconductor bare cores, wherein the semiconductor bare cores are stacked into one-dimensional blocks of the semiconductor bare cores, and conductive patterns are formed along the edges of the one-dimensional blocks, so that the semiconductor bare cores in the one-dimensional blocks are electrically coupled with one another and electrically coupled with an external electric connector. In a further example, the one-dimensional blocks can be arranged into one another to form two-dimensional semiconductor blocks and three dimensional semiconductor blocks.
Description
Technical field
The present invention relates to the semiconductor device and its manufacture method of a kind of semiconductor bare chip block including stacking.
Background technology
Strong growth in portable consumer electronics product demand advances the demand of high capacity storage device.
Nonvolatile semiconductor memory device, such as flash card, be used widely for meeting digital information storage and
Growing demand in exchange.Their portability, multi-functional and robust design, and they
High reliability and Large Copacity cause such storage device to be ideally used to broad category of electronic installation,
Including such as digital camera, digital music player, video game console, PDA and mobile phone.
Although known package arrangements miscellaneous, flash card can generally be made as system in package
(SIP) or many bare die modules (MCM), wherein install on little footmark (footprint) substrate and
Interconnect multiple naked cores.Substrate can generally include firm, base of dielectric, and its one or both sides etches
There is conductive layer.Electrical connection is formed between naked core and conductive layer, and conductive layer is provided and line structure is electrically connected with even
Naked core is connect to host apparatus.Once establishing the electrical connection between naked core and substrate, then component is by typically
Encapsulated with providing protectiveness in being encapsulated in moulding compound.
Fig. 1 shows the cross-sectional side view of conventional semiconductor packages 20.Typical encapsulation includes multiple
Semiconductor bare chip, such as flash memory naked core 22 and controller naked core 24, which is supported on substrate 26.Base
Plate 26 includes via 30, electric trace 32 and engagement pad 34 with semiconductor bare chip 22,24 and the encapsulation
Transmission signal between the host apparatus is located at by body.Naked core joint sheet (not shown) can be formed in naked core
22nd, on 24 surface, with by the anchor leg between corresponding naked core joint sheet and engagement pad 34
Semiconductor bare chip is coupled by bonding with electrical property of substrate.Once complete all of electrical connection, naked core and lead
Bonding can be sealed in moulding compound 36 to seal the packaging body and protect naked core and wire bonding.
Increase memory capacity and while the need of the device form factor of holding or reduction semiconductor package body
Ask and constantly increasing.Can be by manufacturing the element of for example less and thinner semiconductor bare chip etc come portion
Ground is divided to meet the demand.If however, will depositing more greatly in the case of same or less form factor
The aspect of storage capacity obtains significant progress, then need to carry out thoroughly again conventional semiconductor packages body
Design.
The content of the invention
Generally speaking, the example of this technology is related to a kind of method for forming semiconductor device, including：A () exists
Multiple semiconductor bare chips are formed on one or more semiconductor wafers；B () is swashed at least partially through stealthy
Light technology is from one or more the plurality of semiconductor bare chips of semiconductor wafers section, the invisible laser technology
Hole is formed in the intermediate depth of one or more semiconductor wafers, the chip is sliced and causes the plurality of
The slicing edge of semiconductor bare chip has electrical contact；C () is using the corresponding semiconductor bare chip in stacking
Between naked core attach film by the plurality of semiconductor bare chip stacked on top forming block, the plurality of quasiconductor
Common edge of the edge of naked core in alignment with the block；D () applies pressure to remove bubble to the surface of the block；
And (e) forms conductive pattern so that the plurality of semiconductor bare chip in the block in the common edge of the block
Electrical couplings each other, and with External electrical connectors electrical couplings.
In other examples, this technology is related to a kind of method for forming semiconductor device, including：A () exists
Multiple semiconductor bare chips are formed on one or more semiconductor wafers, is included in the plurality of semiconductor bare chip
Form multiple naked core bond pads；(b) at least partially through invisible laser technology from this one or more half
The plurality of semiconductor bare chip of conductor wafer slice, the invisible laser technology is in one or more semiconductor dies
The intermediate depth of piece forms hole, and what the slicing step included cutting in the plurality of semiconductor bare chip multiple connects
Touch pad is so that the step of the plurality of engagement pad is exposed to the edge of the plurality of semiconductor bare chip；C () makes
Attached with the naked core between the corresponding semiconductor bare chip in multiple first semiconductor bare chips in stacking
Multiple first semiconductor bare chips are stacked to form one-dimensional piece by film in a first direction up and down, and the plurality of first
The edge of semiconductor bare chip is in alignment with one-dimensional piece of the common edge；D () forms in the common edge and leads
Electrical pattern, its multiple of edge for being connected to the plurality of first semiconductor bare chip at the common edge connect
Touch pad；And (e) separates this one-dimensional piece for multiple less semiconductor pieces.
In another example, this technology is related to a kind of method for forming semiconductor device, including：A () exists
Multiple semiconductor bare chips are formed on one or more semiconductor wafers, is included in the plurality of semiconductor bare chip
Form multiple electrical contacts；B () is at least partially through invisible laser technology from one or more quasiconductors
The plurality of semiconductor bare chip of wafer slice, intermediate depth shape of the invisible laser in one or more chips
Pore-forming, causes the plurality of electrical contact to be exposed to the plurality of quasiconductor naked to the section of the plurality of semiconductor bare chip
The edge of core；C () second direction that is upper stacked and being orthogonal to the first direction is arranged side by side in the first direction
To form two-dimensional block, the edge of the multiple semiconductor bare chips in the two-dimensional block is aligned the plurality of semiconductor bare chip
In the common edge of the two-dimensional block；D () applies isostatic pressed in the surface of the two-dimensional block to remove bubble；(e)
Conductive pattern is formed in the common edge of the two-dimensional block so that multiple semiconductor bare chips in the two-dimensional block
In at least some electrical contact electrical couplings each other；And (f) to separate the two-dimentional module be less unit,
Each unit includes two or more semiconductor bare chips.
Description of the drawings
Fig. 1 is the prior art of the Conventional semiconductor devices for including the semiconductor bare chip on substrate
Edge view.
Fig. 2 is the prior art of the Conventional semiconductor devices for including the semiconductor bare chip on substrate
Top view.
Fig. 3 is the flow chart of formation semiconductor bare chip according to embodiments of the present invention.
Fig. 4 is the front view of semiconductor wafer, it illustrates the first first type surface of chip.
Fig. 5 is the rearview of semiconductor wafer, it illustrates the second first type surface of chip..
Perspective views of the Fig. 6 from the single semiconductor bare chip 256 of chip.
Fig. 7 is the enlarged perspective of a part for the chip 250 for undergoing invisible laser technique
Fig. 8 and Fig. 9 are the saturating of the single semiconductor bare chip 256 from the chip for undergoing invisible laser technique
View.
Figure 10 is the perspective view of the single semiconductor bare chip 256 of the chip during the backgrinding process.
Figure 11 is the top view of a part of chip separated after cutting.
Figure 12 is the perspective view of the stacked blocks of the semiconductor bare chip of the embodiment according to this technology.
The flow chart of the further detail below of the step of Figure 13 shows the flow chart of Fig. 3 220.
During Figure 14-16 shows the different step of formation Stacket semiconductor block of the embodiment according to this technology
Semiconductor device.
Figure 17 is the flow process of the formation Stacket semiconductor block array of the further embodiment according to this technology
Figure.
Figure 18-22 shows the asynchronous of the formation Stacket semiconductor block array of the embodiment according to this technology
Semiconductor device in rapid.
Figure 23-25 shows the formation Stacket semiconductor block array of the further embodiment according to this technology
Different step in semiconductor device
Specific embodiment
This technology is described referring now to accompanying drawing, embodiment therein is related to a kind of semiconductor device, its
The semiconductor bare chip block formed in being included in accurate manufacturing process.The semiconductor bare chip block is formed with accurately
Edge, and formed in the way of removing bubble removing so that naked core closely and equably can be stacked on each other
Top and/or side.
It should be understood that the present invention can be implemented by many multi-forms, and should not be construed as limited to
Embodiments described herein.Conversely, these embodiments are provided so that the disclosure is comprehensively complete, and
The present invention is passed on fully to those skilled in the art.In fact, it is contemplated that covering these embodiments
Substitute, change and equivalent, which is included in the scope of the present invention and essence limited such as the claim
Within god.Additionally, with regard to the present invention it is described in detail below in, elaborate numerous details so as to
Thorough understanding of the present invention is provided.However, those of ordinary skill in the art are noted that with this
Invention can be implemented without the need for these details.
The term " top " that may be used herein and " bottom ", "up" and "down" and " hang down
Directly " and " level " merely for convenience and the purpose that illustrates, it is not intended to limit retouching for the present invention
State, because the article for being referred to may occur the exchange on position and direction.Equally, as used herein
Term " basic " and/or " about " mean that for given application specific dimensions or parameter can be with
Change in acceptable manufacture tolerance limit.In one embodiment, acceptable manufacturing tolerance for ±
0.25%.
Referring now to the flow chart of Fig. 3, Figure 13 and Figure 17, and Fig. 4-12, Figure 14-16 and figure
The view of 18-15 is explaining embodiments of the invention.First, with reference to the flow chart and Fig. 4-11 of Fig. 3
View, semiconductor wafer 250 can be the wafer material ingot that can be formed in step 200 in beginning.
In one example, chip 250 can be by according to vertical pulling (CZ) method or floating region (FZ) by its ingot for being formed
The monocrystal silicon of method technique growth is forming.However, other materials can also be used in other embodiments
Expect with technique to form chip 250.
In step 204, can be from ingot cutting lower semiconductor chip 250 and by its first first type surface 252
(Fig. 4) all polish with the second first type surface 254 (Fig. 5) relative with surface 252, it is smooth to provide
Surface.In step 206, the first first type surface 252 can undergo kinds of processes step with by chip 250
Each semiconductor bare chip 256 (one of them figure 4 illustrates) is divided into, and in the first first type surface 252
Integrated circuit that is upper and wherein forming each semiconductor bare chip 256.These multiple techniques can be included in collection
The metallization step of deposited metal layer in circuit, metal level include the contact of multiple metals, its to from collection
Into circuit transmissioning signal.Electrical contact can include naked core bond pad 258 (one of them respectively in Fig. 4 and
It is numbered in Fig. 6), which is exposed to the first first type surface 252.In embodiment, naked core bond pad 258
Can be formed by aluminum or its alloy, but pad 258 can also be formed by other materials in other embodiments.
In embodiment, integrated circuit can as nand flash memory storing semiconductor naked core, but can also
It is envisioned for other types of integrated circuit.
According to this technology some in terms of, after cutting into slices as explained below, the quasiconductor of multiple stackings
Naked core 256 can be stacked, and electric each other along at least one edge (Fig. 6) of semiconductor bare chip 256
Connection.Correspondingly, in one embodiment, naked core bond pad 258 can be extended in chip 250
The edge 260 of each semiconductor bare chip here termination.In the embodiment show in figure 6, it is electrically connected with
The tie-rod of low profile is may further include, lead 262 is generally referred herein to.Lead 262 can be with key
Each naked core bond pad 258 is bonded to, and bends to extend to edge 260.Fig. 6 shows following article institute
Naked core 256 after the section of explanation.Lead 262 for example can be formed by gold, but in other examples
Can also be formed by other materials.In a further embodiment, pad redistribution (not shown) can be formed
Naked core bond pad 258 is electrically connected at edge 260 and in known manner.Fig. 6 shows and is formed in
Naked core bond pad 258 and lead 262 on the single edge 260 of semiconductor bare chip 256.However, should
When being understood by, naked core bond pad 258 and/or lead 262 can be formed in the two of semiconductor bare chip 256
Individual, three or four perimeters.
According to this technology some in terms of, it is convenient to omit tie-rod lead 262 is (as in Fig. 3, step 208 is all
Represented by the dotted line for enclosing), and pass through invisible laser technology mode cut crystal so that naked core bond pad
258 are exposed to edge 260.In the step 212, invisible laser technique can be with the back side of chip 250
Grinding and/or as explained below band stretching are used in combination, with very clean and accurate by chip 250
Cut into slices as independent semiconductor bare chip 256, and a part for naked core bond pad is exposed to and corresponding is partly led
The edge of body naked core.
With reference now to Fig. 7, chip 250 can be propped up by fixture or other stayed surface (not shown)
Support, and the integrated circuit on the first first type surface 252 is made in the face of stayed surface, and the second first type surface 254 is carried on the back
From stayed surface.Subsequently laser instrument 264 can launch certain wavelength (e.g. infrared or near-infrared wavelength)
Pulse laser beam 266, the beam transmission is by the second first type surface of chip 250.The pulse laser
Beam can pass through optics into focus in the surface 254 of chip under a bit, optical system is for example including one
Individual or multiple collimating lens 268.When the laser beam reaches peak power density in focus, chip is inhaled
Energy is received, and produces Small Holes 270.
Laser can be moved along the row and column in the horizontal plane of chip, and is activated so that on multiple points
The Small Holes 270 of multiple tight settings are formed in the intermediate depth of chip (in the first surface 252 of chip
And second surface 254 between).The row and column of Small Holes 270 limits each cut by chip 250
The net shape of semiconductor bare chip 256.Laser can form the Small Holes 270 of simple layer (single
Depth), as represented by Fig. 8.Alternately, laser can form multiple (two or more) layers
Small Holes 270 in multiple depth, as represented by Fig. 9.Although Fig. 8 and Fig. 9 is as showing cutting
Semiconductor bare chip 256 afterwards, but when invisible laser technique is performed, naked core 256 can remain chip
250 part.
It is excellent with laser surface ablation section that the method for this wafer slice provides more traditional blade section
Point.Both microtomy can cause fragment along line of cut, peel off and wafer contamination, so as to cause afterwards
Semiconductor bare chip with Roughen Edges.As explained below, can according to the semiconductor bare chip of this technology
To make its edge 260 aligned with each other in the stacked body of semiconductor bare chip 256, and it is any this kind of coarse
Edge can hinder smooth, the clean and close interface between adjacent semiconductor bare chip.Mentioned above
Wafer slice method allows multiple naked cores 256 to stack so that edge 260 forms partly leading for stacking together
The surface of the unusual light of body block, without crackle or chip defect.Additionally, blade and laser surface
Ablation section can crush wafer material along line of cut, cause relatively large kerf width.As illustrated in figures 7-11
Invisible laser have very narrow otch, provide more spaces for semiconductor bare chip 256 on chip,
And higher production yield.
After invisible laser step 212, chip 250 can remain as single piece.Chip subsequently can exist
Thinning in step 214, is applied on the second first type surface 254 using abrasive wheel (not shown) and is ground with back
Mill chip is from such as 780 μm to 280 μm, but the merely illustrative purpose of those thickness, and can be different
Change in embodiment.
With reference to Figure 10, except chip thinning 250, the vibration from backgrind step is likely to result in crackle
272, which is passed to first first type surface 252 and the second first type surface 254 of chip 250 from Small Holes 270
Broadcast, to complete the section of chip 250.In a further embodiment, chip 250 can be in backgrind
Single piece is remained after step 214.This is likely due to backgrind technique and does not result in from Small Holes
The crackle of propagation.This may also be due to, in embodiment, backgrind step 214 can be in stealth
Perform before laser step 212.
After invisible laser and backgrind step, in the case where chip remains single piece, chip
Can be turned over, and the second first type surface is fixed on (Figure 11 is shown with 274 on 274
A part).The band subsequently can be stretched along vertical axises in the step 216.This produces stress in the wafer,
Which causes to propagate to first first type surface 252 and the second first type surface 254 of chip 250 from Small Holes 270
Crackle completing the section of chip 250.Semiconductor bare chip after the section that the stretching also separately takes
256, as shown in Figure 11.In embodiment after chip is sliced after backgrind step, take
Put robot the semiconductor bare chip 256 after section can be transmitted to stayed surface, such as band shown in Fig. 8
274, to continue with the further technique explained by text.
According to the one side of this technology, the propagation of invisible laser and follow-up crackle 272 can cause crystalline substance
Piece is along the section by the line of naked core bond pad 258.When crackle 272 is propagated, naked core bond pad 258
It is cut off.Therefore, as shown in the top partial view diagram in Figure 11, the active part of naked core bond pad 258
258a is exposed to the edge 260 of corresponding semiconductor bare chip 256.The remainder of naked core bond pad 258
258b is divided to be maintained at (next neighbouring in the edge 276 of next neighbouring semiconductor bare chip 256
Semiconductor bare chip 256 is also with the active part 258a in the edge 260 relative with edge 276).It is naked
Electrical connection in core 256 to naked core bond pad 258 is set up to active part 258a.Each semiconductor bare chip
Remainder 258b in 256 keeps electrically isolating.
Multiple semiconductor wafers 250 can be manufactured according to step 200-216 as explained above.At this
Afterwards, in step 218, as shown in figure 12, pick and place robot to take from identical or different
The semiconductor bare chip 256 of chip, and it is stacked as the stacked blocks 280 of semiconductor bare chip 256.At this
In text, stacked blocks 280 are properly termed as semiconductor device 280.Including the active part of naked core bond pad 258
The edge 260 of 258a can be aligned to form the edge 282 of stacked blocks 280 along common side.
Semiconductor bare chip 256 can be stacked, and using between corresponding semiconductor bare chip 256
Naked core attaches film (DAF) layer makes which interfix in Stacket semiconductor 280.Single stacked blocks 280
In the quantity of semiconductor bare chip can change in embodiment, partly lead from 2 to 32 (or more) are individual
Body naked core 256, including such as 4,8 or 16 semiconductor bare chips.
In a step 220, the conductive pattern of electric trace can be formed at the edge of Stacket semiconductor block 280
On 282.The view of the flow chart and Figure 14-16 of Figure 13 shows the further details of step 220.
The view of Figure 15 shows the conductive pattern 288 being formed on the single edge 282 of stacked blocks 280.So
Afterwards, it should be appreciated that can be formed conductive pattern 288 in two of stacked blocks 280, three, four
Individual, five, or six side peripheries.
As described above, naked core bond pad 258, one of them is numbered in fig. 14, is exposed to edge
282.In step 350, edge 282 can accommodate electric insulation layer to prevent the conduction being formed thereon
Short circuit between semiconductor bare chip 256 in pattern and block 280.For example, in step 350, electricity
Insulating barrier 284, e.g. Si oxide or silicon nitride, can be with splash on edge 282.At other
Embodiment in, insulating barrier 284 can also be made up of other electrical insulators, it is also possible to sunk by other thin film
Product technology is applying.Insulating barrier 284 can be less than 1 μm, but in other embodiments can also be thicker.
In step 354, electric insulation layer 284 can be treated to make the end of naked core bond pad 258 sudden and violent
Edge 282 is exposed to, as shown in Figure 14.In the embodiment of tie-rod lead 262 is formed with, lead
262 end can be exposed to edge 282.Layer 284 for example can be processed by laser or chemical etching
To expose the end of pad 258 (or lead 262).
In step 358, conductive layer can be applied on insulating barrier 284.The conductive layer may, for example, be
Titanium, nickel, copper or rustless steel by splash on insulating barrier 284 is formed.In other embodiments, lead
Electric layer can also be made up of other electric conductors, it is also possible to applied by other film deposition techniques.The conduction
Layer can have 2-5 μm of thickness, but in other embodiments can also be thicker or thinner than this.
Annealing heating is selectively performed to remove the metal grain state in conductive layer.
In step 360, conductive layer can be treated to remove the part of this layer and leave conductive pattern
288 (Figure 15).Conductive pattern can make the end of the pad of the selection of different semiconductor bare chips 256 each other
Connection, and be, for example, that soldered ball as explained below is connected with External electrical connectors.For example, it is known that
Lithography process can be performed to apply photoresist layer on conductive layer, by with final metal trace
Pattern mask, the exposed and developed photoresist etches away unexposed part to stay with conduction
The metal trace of pattern 288, subsequently removes the photoresist in metal trace.In other embodiments,
Conductive pattern 288 can be formed by other photoetching processes or non-lithographic method technique.One other technology is tool
There is the screen printing of the conductive trace of 288 shape of conductive pattern.
The merely illustrative purpose of particular conductivity pattern illustrated in Figure 15, and change in a further embodiment.
As mentioned, in other embodiments, the conductive pattern such as pattern 288 can be formed in two or many
Individual lateral periphery (no matter whether these sides have pad 258).Additionally, electric trace 290 can be with shape
Into on the upper surface and/or lower surface of semiconductor device 280, for example, connect with the conductive pattern on side
Connect, or be connected with integrated circuit 292.Trace 290 can by photoetching process, screen printing or
Other techniques are formed.As described above, the unusual light and height of the naked core 256 on edge surface 282
The edge of alignment allows to form trace 290 without making trace have any interruption or other problems.
The flow chart for referring again to Fig. 3, in step 226, limits External electrical connectors 296 (wherein
One of be numbered in the upward view of Figure 16) to form complete Stacket semiconductor block 280.For example,
It is soldered on the mainboard of host apparatus as BGA package in semiconductor device 280, external electrical connections
Device can be the pad redistribution (or other engagement pads) in the lower surface for fix semiconductor device 280
Solder ball.External electrical connectors can also be alternatively connecing in the lower surface of semiconductor device 280
Fingertip.For thin space (for example, the spacing less than 350 μm) adapter, electric connector 296 can
Being by the projection that for example wet-chemical plating method is formed.
The view of the flow chart and Figure 18-25 of Figure 17 shows the further embodiment of this technology, its shape
Into the 3D arrays of the 2D arrays or semiconductor piece 480 of semiconductor piece as explained below 380.
Herein, the semiconductor piece of 2D and 3D is collectively known as multidimensional block.In step 200-316, such as
Have been explained above.Formed semiconductor bare chip and stacked by chip.For example, step 300-
Step 316 can be the same steps corresponding with step 200-216 mentioned above.
In a step 330, semiconductor bare chip can be stacked as 2D or 3D arrays.For example, as schemed
Shown in 18, single semiconductor bare chip 256 can vertically (y- directions) and/or flatly (x-
Direction) it is stacked in gripper shoe 278 to form the 2D arrays of semiconductor bare chip 380.Herein,
The 2D arrays of semiconductor bare chip 256 can also be referred to as semiconductor device 380.Replacement is individually partly led
Body naked core, semiconductor device 380 can be by (such as institute's shapes in Figure 12 of semiconductor piece 280 for stacking
Into with illustrate, before trace 288 is formed) be vertically and/or horizontally stacked on gripper shoe 278
On being formed, as shown in figure 19.
When in two dimensions (in top of each other and side by side) Stacket semiconductor naked core, it should be understood that
It is that gripper shoe 278 can support semiconductor bare chip in multiple directions.Gripper shoe 278 can be from bottom table
Face supports the array (as shown in figure 18) of semiconductor bare chip 380.What gripper shoe 278 can be substituted is
Horizontal plate, which is from the surface of the x-y plane positioned at Figure 18 (that is, by the sightless back of the body of view of Figure 18
Portion surface, which is relative with the surface including pad 258) support semiconductor bare chip array.Gripper shoe 278 can
With substitute as horizontal plate, its from perpendicular to the x- directions of Figure 18 surface (that is, enter page-out,
Surface on the right side of the view of Figure 18).Except gripper shoe 278, can be provided in vertical in gripper shoe 287
Upwardly extending second guide plate (not shown), with when semiconductor bare chip 256 is stacked as array 302
Help its further alignment.
It is stacked up and down and in x- directions semiconductor bare chip 256 side by side each other y- directions are positioned, can be with
DAF is used between adjacent semiconductor bare chip 256.As explained below, once electric trace is formed
On one or more edge surfaces of the 2D arrays of semiconductor bare chip, the array can be separated into point
Other Stacket semiconductor block 280 (such as shown in Figure 15).Correspondingly, it is possible to use two different
DAF layers.First DAF layers 302 (some of them are numbered in Figure 18 and Figure 19) can be used for
Between semiconductor bare chip 256, after block 280 is separated from 2D blocks 380, these semiconductor bare chips 256
Still keep being bonded to each other in each Stacket semiconductor block 280.2nd DAF layers, 304 (some of them
Be numbered in Figure 18 and Figure 19) can be used between semiconductor bare chip, in block 280 from 2D blocks
After separating in 380, these naked cores will be separated from one another.First DAF layers 302 and the 2nd DAF layers 304
Between difference will be described below.
The merely illustrative purpose of particular configuration in Figure 18 and Figure 19, and 2D semiconductor pieces 380 can be
There is on x- directions and/or y- directions the block 280 of less or more semiconductor bare chips or stacking.Formed
In the case of stacked blocks 280 as shown in figure 19, stacked blocks 280 can with than shown in Figure 19 more
Less or more semiconductor bare chip 256.
In order to along x- directions semiconductor bare chip stacked side by side 256 (either individually or in bulk) each other
It is essential that the edge surface of corresponding semiconductor bare chip 256 closely neatly coordinates each other.This
Technology is accomplished in several ways this point.First, as explained above, using invisible laser technique
Ensure that semiconductor bare chip 256 is smooth, accurate edge come single semiconductor bare chip of cutting into slices, and allow
Corresponding semiconductor bare chip 256 in single Stacket semiconductor block 280 is accurate aligned with each other.It is similar
Ground, the edge of alignment allow the Stacket semiconductor block in 2D semiconductor pieces 380 each other closely and accurate
Alignment.
Another way, corresponding semiconductor piece 280 can accurately be aligned to ensure that 2D semiconductor pieces 380
In x- directions and the corresponding naked core 256 in y- directions between DAF layers in no bubble.Otherwise
These bubbles may result in the separation of the semiconductor bare chip 256 in 2D semiconductor pieces 380.According to this
In terms of some of technology, bubble can be removed, such as 2D semiconductor pieces 380 be applied in step 334
Plus isostatic pressed.For example, when the DAF layers between naked core are in b-stage, 2D can partly be led
Body block 380 is immersed in (not shown) in the liquid of isostatic pressed.This technique is simultaneously to 2D semiconductor pieces
All surface applies pressure (as represented by the arrow on the corresponding surface in Figure 20) to extrude gas
Steep to ensure that corresponding Stacket semiconductor block 280 is closely bonded together.Band 274 can removed
Same mode as shown in Figure 9 applies pressure to Stacket semiconductor block 280 afterwards.
In this example, the pressure for being applied by isostatic pressed can be between 2Mpa and 10Mpa, temperature
Can be between 80 DEG C and 180 DEG C, the time is several seconds to about 1 minute.It should be appreciated that this
A little parameters be only for example purpose, and in other embodiments each parameter can become turn to be higher than or
Less than these scopes.The working fluid of isostatic pressed can be water, but which can also in other embodiments
It is other fluids.DAF layers 302 (not being 304) can be in isostatic pressing process or subsequent reflux technique
In be cured as the c- stages.
In embodiment, the semiconductor bare chip 256 in 2D blocks 380 can be in 2D semiconductor pieces 380
In in same orientation be aligned.Thus, for example, in naked core bond pad 258 in Stacket semiconductor block
In the case of 280 single edge termination, pad 258 can all be exposed to the same of 2D semiconductor pieces 380
One edge 382, as shown in figure 20.It is contemplated that in other embodiments, some pads 258
Towards one side, and other pads 258 are towards another side.
As shown in figure 21, conductive pattern 288 can be subsequently formed in step 340 on edge 382.
The details for forming conductive pattern 288 can be as described in the step of fig. 13 above.In Figure 21
The 288 merely illustrative purpose of particular conductivity pattern for illustrating, and can change in other embodiments.Can be with
The repeat conduction pattern 288 on each Stacket semiconductor block 280.However, semiconductor pattern 288 is given
Determine trace to cross over and electrically connect the two or more Stacket semiconductor blocks in semiconductor device 380
280 naked core bond pad 258.
In other embodiments, the conductive pattern such as pattern 288 can be formed in two or more sides
Surrounding (no matter whether these sides have exposure naked core bond pad 258 thereon).Additionally, electricity
Trace 290 can be formed in the upper surface and/or lower surface of semiconductor device 380, for example, connect side
Conductive pattern, or connection integrated circuit 292.Trace 290 can by photoetching process, screen printing,
Or other techniques are formed.
In step 344, semiconductor device 380 can be separated into Stacket semiconductor block, such as Figure 15
Shown in Stacket semiconductor block 280.Before step 344 sometimes, DAF layers 302 can be with
The c- stages are hardened to, so that the naked core in given Stacket semiconductor block 280 can be closely installed at one
Rise.In one embodiment, after DAF layers are hardened, DAF layers 304 remain b- stage adhesives.
Therefore, in step 344, DAF layers 304 can be treated to remove DAF layers 304, reduce DAF
The bond propertiess of layer 304, or overcome the power that semiconductor piece 280 keeps together by DAF layers, with
Block 280 is separated by 2D blocks 380.
The performance of DAF layers 302 and 304 can be selected as known mode, so that DAF layers 302
While can hardening, DAF layers 304 will not.Additionally, DAF layers 302 and 304 can be with known
Mode is chosen so that ought in step 344 DAF layers 304 it is processed with by corresponding block 280
When separated from one another, DAF layers 302 are remained unaffected.DAF layers 302 and 304 can be various materials
Material, including such as polyester resin (polyester resin), vinyl ester resin (vinyl ester resin),
Or other resins, epoxy resin, phenolic compound or urethanes.DAF layers 302
With 304 can be further BMI (bismaleimides), PEAM based adhesives,
And the mixture of these chemical compositions.It is also contemplated that other materials.In one embodiment, DAF
Layer 304 can be two-sided tape, and wherein binding agent decomposes in ultra-vioket radiation and/or in the case of applying heat.
DAF layers 302 and 304 can come from Henkel, and which is on the how bright Goss farm of California, USA
(Rancho Dominguez, California, USA) is with business office.
It should be appreciated that in addition to using two kinds of difference DAF layers with different bond properties,
Corresponding Stacket semiconductor block 280 can also be made to separate from 2D blocks 380 using other methods.
For example, it is possible to use the DAF of single type, it is but to be separated from each other when block 280 is separated
DAF layers between naked core selectively can be processed, to decompose or reduce the viscous of the DAF of this part
Close property.In other embodiments, it is possible to use the DAF of single type, corresponding stacking half
Conductor block can be separated by cutting, e.g. using saw blade.
In step 346, External electrical connectors 296 (one of them is numbered in the view of Figure 22)
The surface of corresponding Stacket semiconductor block 280 as described above can be fixed on, to complete stacking half
Conductor block 280.
The step of flow chart of Figure 17, can be used for forming the 3D semiconductor pieces 480 shown in Figure 23-25.
Herein, 3D semiconductor pieces 480 are also referred to as semiconductor device 480.To form 3D semiconductor pieces
480, the Stacket semiconductor block 280 of multiple formation can be vertically stacked in y- directions, in x- directions water
Level land is aligned, and is further aligned in the z- directions for being orthogonal to y- directions and x- directions.It is specific what is illustrated
In configuration, height of the semiconductor device 480 in y- directions is three stacked blocks 280, in the width in x- directions
Spend for three stacked blocks, and the depth in z- directions is two stacked blocks.It is to be understood, however, that
Can be at least one of x- directions, y- directions and z- directions stacking/more or less of stacking of alignment
Block.3D semiconductor pieces 480 independent can be partly led by stacking in x- directions, y- directions and z- directions
Body naked core 256 is forming.
Figure 23 can be the front view of 3D semiconductor pieces 480, it illustrates edge 382 mentioned above.
Relative edge 384 is invisible in the front view of Figure 23.After Figure 24 3D semiconductor pieces 480
View, wherein edge 384 are visible, and relative edge 382 is invisible.In certain embodiments, edge
There may be interface 388 between the corresponding stacked blocks 280 in y- directions.Along the stacking at the interface 388
Block 280 can be fixed to one another using DAF layers as explained above, and any bubble can be by interface
It is extruded in 388, such as in the isostatic pressing process having been explained above.In certain embodiments, stack
The edge of semiconductor piece 280 can no conductive pattern at interface 388.However, in other enforcements
In example, there can be conductive pattern on one or more edges at interface 388, the conductive pattern can be with
It is embedded in the DAF layers between the adjacent stacked blocks at interface 388.
The particular semiconductor pattern 288 on edge 382 and 384 illustrated in Figure 23 and Figure 24 be only for
Example purpose, and can change in other embodiments.In other embodiments, such as pattern 288
Conductive pattern can be formed on one edge or around the side of three or more (no matter these
Whether side has naked core bond pad 258 thereon).Additionally, electric trace 290 can be formed in half
On the top of conductor device 480 and/or lower surface, for example, connect the conductive pattern of side, or connection
Integrated circuit 292.Trace 290 can be formed by photoetching process, screen printing or other techniques.
After trace is formed on one or more edge surfaces of 3D semiconductor pieces 480, block 480 can
To be separated into independent Stacket semiconductor block 280, and electric connector 296 can be fixed on it is corresponding
On the surface of Stacket semiconductor block 280, as shown in Figure 25.
Efficient space utilization is provided according to the semiconductor device in any embodiments thereof described above, wherein should
Semiconductor device almost includes semiconductor bare chip completely.According to this technology, eliminate and fill in conventional semiconductor
The substrate taken up space in putting and wire bonding.Additionally, semiconductor bare chip in the semiconductor device
Precise edge and profile allow the semiconductor bare chip precise match in the device.
In order to illustrate the purpose with example, the aforementioned specific descriptions of the present invention are presented.This is not intended to exhaustion
Or limit the invention to disclosed precise forms.According to teaching many modifications and variations above being can
Can.Described embodiment is selected best to explain principle of the invention and its practical application, therefore
Those skilled in the art best using the present invention, and can be carried out suitable for set in different embodiments
The various modifications of the special-purpose thought.The scope of the present invention is defined by the appended claims.
Claims (29)
1. it is a kind of formed semiconductor device method, including：
A () forms multiple semiconductor bare chips on one or more semiconductor wafers；
B () is cut into slices from one or more semiconductor wafers at least partially through invisible laser technology this is more
Individual semiconductor bare chip, the invisible laser technology are formed in the intermediate depth of one or more semiconductor wafers
Hole, the chip are sliced and cause the slicing edge of the plurality of semiconductor bare chip to have electrical contact；
(c) using stacking in corresponding semiconductor bare chip between naked core attach film come by the plurality of half
Conductor naked core stacked on top to form block, the common edge of the edge of the plurality of semiconductor bare chip in alignment with the block
Edge；
D () applies pressure to remove bubble to the surface of the block；And
E () forms conductive pattern so that the plurality of semiconductor bare chip in the block in the common edge of the block
Electrical couplings each other, and with External electrical connectors electrical couplings.
2. the method for claim 1, the naked core of cutting into slices cause the section of the plurality of semiconductor bare chip
There is the step (b) of electrical contact to be included in formation naked core bond pad in the plurality of semiconductor bare chip at edge
At the slicing edge of the plurality of semiconductor bare chip.
3. the method for claim 1, the naked core of cutting into slices cause the section of the plurality of semiconductor bare chip
The step (b) that edge has electrical contact is included in shape in the naked core bond pad of the plurality of semiconductor bare chip
Into electrical lead, and bend the electrical lead to extend to the slicing edge of the plurality of semiconductor bare chip.
4. the method for claim 1, the naked core of cutting into slices cause the section of the plurality of semiconductor bare chip
The step (b) of the edge with electrical contact is included at the slicing edge of the plurality of semiconductor bare chip and is formed
Pad redistribution, and electrically connect bond pad of the pad redistribution to the plurality of semiconductor bare chip.
5. the method for claim 1, also includes pacifying the chip in one or more chips
The step of being mounted in and take, and stretch the band.
6. method as claimed in claim 5, is stretched the band and causes what is formed by the invisible laser technology
Hole is propagated to the first and second first type surfaces of the chip, to complete from the wafer slice semiconductor bare chip.
7. the method for claim 1, also including in backgrind one or more chips
The step of second first type surface of chip is with the thinning chip.
8. method as claimed in claim 7, the backgrind chip are caused by the invisible laser technology
Propagate to complete from the wafer slice quasiconductor to the first and second first type surfaces of the chip in the hole of formation
Naked core.
9. the method for claim 1, the conductive pattern include the first conductive pattern, and the method is also
It is included on the block at least second surface different from common edge and forms the step of at least the second conductive pattern
Suddenly.
10. the method for claim 1, the plurality of electrical contact include multiple first electrical contacts, and
The slicing edge of the plurality of semiconductor bare chip includes the first slicing edge of the plurality of semiconductor bare chip, the party
Method also includes forming the plurality of semiconductor bare chip so that at least multiple second electrical contacts extend to the plurality of half
At least second slicing edge of conductor naked core, second common edge of at least the second slicing edge in the block
Edge is mutually aligned with each other.
11. methods as claimed in claim 10, the conductive pattern include the first conductive pattern, the method
Be additionally included in the step of at least the second conductive pattern being formed at least second common edge of the block.
12. the method for claim 1, are additionally included on the surface of the block and fix multiple solder balls
The step of using as External electrical connectors.
13. the method for claim 1, be additionally included on the surface of the block formed it is multiple contact refer to
The step of using as External electrical connectors.
A kind of 14. methods for forming semiconductor device, including：
A () forms multiple semiconductor bare chips on one or more semiconductor wafers, be included in the plurality of half
Multiple naked core bond pads are formed in conductor naked core；
B () is cut into slices from one or more semiconductor wafers at least partially through invisible laser technology this is more
Individual semiconductor bare chip, the invisible laser technology are formed in the intermediate depth of one or more semiconductor wafers
Hole, the slicing step include cutting multiple engagement pads in the plurality of semiconductor bare chip so that the plurality of
The step of engagement pad is exposed to the edge of the plurality of semiconductor bare chip；
C () is using between the corresponding semiconductor bare chip in multiple first semiconductor bare chips in stacking
Naked core attaches film and stacks up and down in a first direction to form one-dimensional piece by multiple first semiconductor bare chips, should
The edge of multiple first semiconductor bare chips is in alignment with one-dimensional piece of the common edge；
D () forms conductive pattern in the common edge, which is connected at the common edge the plurality of
Multiple engagement pads of the edge of semiconductor naked core；And
E () separates this one-dimensional piece for multiple less semiconductor pieces.
15. methods as claimed in claim 14, be additionally included on one-dimensional piece of the surface apply pressure with
The step of removing bubble.
16. methods as claimed in claim 14, are also included using the phase in multiple second semiconductor bare chips
It is this is more along the second direction for being orthogonal to the first direction that the naked core of corresponding semiconductor bare chip attaches film
The step of individual second semiconductor bare chip is arranged side by side each other to form two-dimensional block, the plurality of semiconductor bare chip
Edge is in alignment with the common edge.
17. methods as claimed in claim 16, the surface for being additionally included in the two-dimensional block apply pressure to move
The step of bubble removing.
18. methods as claimed in claim 14, the step (d) include being orthogonal to the first party
To second direction install the plurality of one-dimensional piece, and to be orthogonal to the third direction in first and second direction
The plurality of one-dimensional piece is installed so that the multidimensional block includes three-dimensional bits.
19. methods as claimed in claim 14, are also included the chip in one or more chips
The step of installing on tape, and stretch the band, is stretched the band and causes what is formed by the invisible laser technology
Propagate to complete from the wafer slice semiconductor bare chip to the first and second first type surfaces of the chip in hole.
20. methods as claimed in claim 14, also including in backgrind one or more chips
The step of second first type surface of one chip is with the thinning chip, the backgrind chip are caused by the stealth
Propagate to complete from the wafer slice to the first and second first type surfaces of the chip in the hole that laser technology is formed
The semiconductor bare chip.
21. methods as claimed in claim 14, the conductive pattern in the common edge include that at least first leads
Electrical pattern, the method are additionally included in shape at least second surface different from the common edge of the multidimensional block
The step of at least the second conductive pattern.
22. methods as claimed in claim 14, are additionally included on the surface of the block and fix multiple solder balls
The step of using as External electrical connectors.
23. methods as claimed in claim 14, be additionally included on the surface of the block formed it is multiple contact refer to
The step of using as External electrical connectors.
A kind of 24. methods for forming semiconductor device, including：
A () forms multiple semiconductor bare chips on one or more semiconductor wafers, be included in the plurality of half
Multiple electrical contacts are formed on conductor naked core；
B () is cut into slices from one or more semiconductor wafers at least partially through invisible laser technology this is more
Individual semiconductor bare chip, the invisible laser form hole in the intermediate depth of one or more chips, many to this
The section of individual semiconductor bare chip causes the plurality of edge for making electrical contact with and being exposed to the plurality of semiconductor bare chip；
(c) it is upper stacked in the first direction and be orthogonal to the second direction of the first direction be arranged side by side it is the plurality of
Semiconductor bare chip to form two-dimensional block, the edge of the multiple semiconductor bare chips in the two-dimensional block in alignment with this two
The common edge of dimension block；
D () applies isostatic pressed in the surface of the two-dimensional block to remove bubble；
E () in the common edge of the two-dimensional block forms conductive pattern so that multiple in the two-dimensional block partly lead
At least some in body naked core makes electrical contact with electrical couplings each other；And
F it is less unit that () separates the two-dimentional module, and each unit includes two or more quasiconductors
Naked core.
25. methods as claimed in claim 24, the step (c) include using the first direction and are somebody's turn to do
Naked core between corresponding semiconductor bare chip in second direction attaches film.
26. methods as claimed in claim 24, the step (f) include the two-dimensional block such as being immersed in quiet
In pressure.
27. methods as claimed in claim 24, the conductive pattern in the common edge include at least first
Conductive pattern, the method are additionally included on the multidimensional block at least second surface different from common edge and are formed
The step of at least the second conductive pattern.
28. methods as claimed in claim 24, are additionally included on the surface of the block and adhere to multiple solder balls
The step of using as External electrical connectors.
29. methods as claimed in claim 24, be additionally included on the surface of the block formed it is multiple contact refer to
The step of using as External electrical connectors.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109909623A (en) * | 2017-12-12 | 2019-06-21 | 中芯国际集成电路制造(北京)有限公司 | Cutting method for wafer |
| CN110660805A (en) * | 2018-06-28 | 2020-01-07 | 西部数据技术公司 | Stacked semiconductor device including bifurcated memory die module |
| CN111291494A (en) * | 2020-02-21 | 2020-06-16 | 西安交通大学 | Multi-scale multi-physical field coupling simulation method for TRISO fuel particles of nuclear reactor |
| CN111696968A (en) * | 2019-03-14 | 2020-09-22 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110221073A1 (en) * | 2009-02-06 | 2011-09-15 | Headway Technologies, Inc. | Layered chip package with wiring on the side surfaces |
| CN102206469A (en) * | 2010-03-31 | 2011-10-05 | 古河电气工业株式会社 | Adhesive tape for wafer processing |
| US20120119385A1 (en) * | 2008-05-20 | 2012-05-17 | Vertical Circuits, Inc. | Electrical Connector Between Die Pad and Z-Interconnect for Stacked Die Assemblies |
| CN103258773A (en) * | 2013-05-21 | 2013-08-21 | 合肥彩虹蓝光科技有限公司 | Semiconductor component coating film processing method |
| CN103413785A (en) * | 2013-08-02 | 2013-11-27 | 南通富士通微电子股份有限公司 | Chip cutting method and chip packaging method |
-
2015
- 2015-09-11 CN CN201510578162.8A patent/CN106531638B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120119385A1 (en) * | 2008-05-20 | 2012-05-17 | Vertical Circuits, Inc. | Electrical Connector Between Die Pad and Z-Interconnect for Stacked Die Assemblies |
| US20110221073A1 (en) * | 2009-02-06 | 2011-09-15 | Headway Technologies, Inc. | Layered chip package with wiring on the side surfaces |
| CN102206469A (en) * | 2010-03-31 | 2011-10-05 | 古河电气工业株式会社 | Adhesive tape for wafer processing |
| CN103258773A (en) * | 2013-05-21 | 2013-08-21 | 合肥彩虹蓝光科技有限公司 | Semiconductor component coating film processing method |
| CN103413785A (en) * | 2013-08-02 | 2013-11-27 | 南通富士通微电子股份有限公司 | Chip cutting method and chip packaging method |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109909623A (en) * | 2017-12-12 | 2019-06-21 | 中芯国际集成电路制造(北京)有限公司 | Cutting method for wafer |
| CN110660805A (en) * | 2018-06-28 | 2020-01-07 | 西部数据技术公司 | Stacked semiconductor device including bifurcated memory die module |
| CN110660805B (en) * | 2018-06-28 | 2023-06-20 | 西部数据技术公司 | Stacked semiconductor device including branched memory die modules |
| CN111696968A (en) * | 2019-03-14 | 2020-09-22 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure |
| CN111696968B (en) * | 2019-03-14 | 2022-06-24 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure |
| CN111291494A (en) * | 2020-02-21 | 2020-06-16 | 西安交通大学 | Multi-scale multi-physical field coupling simulation method for TRISO fuel particles of nuclear reactor |
| CN111291494B (en) * | 2020-02-21 | 2021-10-19 | 西安交通大学 | Multi-scale multi-physical field coupling simulation method for TRISO fuel particles of nuclear reactor |
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| CN106531638B (en) | 2020-02-07 |
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