JP2006108254A - Manufacturing methods of semiconductor chip and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor chip capable of reducing chipping and lack of any chip corner that are problems of a manufacturing method of a semiconductor chip formed by a conventional dicing method, and of improving the yield. <P>SOLUTION: As illustrated in (1), (2) of Fig. (b), cutouts 3, 4 having inclination side faces 3a, 4a are formed along a dicing line or a chip division line on the side of a circuit formation surface 2 of a wafer 1. A protective tape 7 is stuck on the side of the circuit formation surface 2 as illustrated in (3) of Fig. (b), and the rear surface 12 of the wafer 1 is polished as illustrated in (4) of Fig. (b). As illustrated in (5) of Fig. (b), the wafer 1 is polished to a predetermined thickness, and is separated into a plurality of semiconductor chips 13. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention provides a shape and method for manufacturing a semiconductor chip that are particularly effective for improving the yield of semiconductor chip formation. For example, various IC cards, one-chip chip size package (CSP), and two chips are provided. The present invention relates to a technique effective for a stacked chip size package (S-CSP) in which the above-described stacked body is mounted, and a multichip size package (M-CSP) in which two or more chips are mounted side by side.

  In general, in a semiconductor chip manufacturing process, after circuit elements are formed on the surface of a semiconductor wafer, the opposite side of the circuit formation surface is polished to a predetermined thickness and then divided into individual semiconductor chips by dicing. The divided semiconductor chips are mounted on a wiring board or the like, connected with gold wires or bumps, sealed with resin, and various semiconductors represented by IC cards and CSPs (Chip Size Packages). Form as a package. However, due to recent demands for miniaturization and thickness reduction, a process of reducing the thickness of the semiconductor chip to 100 μm or less is performed.

  However, in the conventional method of manufacturing a semiconductor chip, chipping occurs on the back surface of the semiconductor chip in the dicing process, or many damages are formed on the side surface due to scratches (crushed layers) by the dicing blade. In particular, for semiconductor chips that require a thickness of 100 μm or less, the difference in thermal expansion characteristics between the semiconductor chip and the sealing material or die bond material due to impact during handling during package manufacturing or thermal stress after completion of the package Due to the stress caused by the above, the chipping on the back surface or the damage on the side surface is the starting point, and the semiconductor chip is easily cracked.

Therefore, a tip dicing method has been proposed as a semiconductor chip manufacturing method for reducing chipping (for example, Patent Document 1). In this technique, a notch deeper than a predetermined chip thickness is formed along a dicing line or a chip dividing line on a circuit element forming surface of a semiconductor wafer, and a protective tape is attached to the circuit element forming surface of the semiconductor wafer. In this method, the semiconductor chip is formed by polishing from the opposite side of the circuit element forming surface of the wafer, thereby greatly reducing chipping generated at the back edge of the semiconductor chip and improving the chip strength. In some cases, after polishing the back surface, the polished surface may be mirror-finished by dry polishing or CMP (Chemical Mechanical Polish). Alternatively, not only the polished surface is mirror-finished by plasma etching, but also damage on the side surface of the chip that occurs when a cut is formed by dicing or the like is reduced, and the chip strength is further improved.
Japanese Patent Laid-Open No. 61-112345 (published May 30, 1986) Japanese Patent Laying-Open No. 2003-229384 (published on August 15, 2003)

  In the prior dicing method of Patent Document 1, the chipping of the back surface of the semiconductor chip is greatly reduced compared to the conventional method in which dicing is performed from the circuit element forming surface of the semiconductor wafer after the back surface polishing. However, in the backside polishing process, depending on the type of protective tape and the backside polishing conditions, the chip thickness reaches the pre-formed cutting depth, the moment when the chip is divided, or the predetermined chip thickness after reaching the cutting depth. Until the polishing is completed, new chipping and chip corner chipping may occur at the chip edge due to contact between adjacent divided chips and mechanical stress and impact during polishing, which may reduce the yield.

  The present invention has been made in view of the above-described conventional problems, and its object is to reduce chipping and chip corner chipping, which are problems in the conventional method of manufacturing a semiconductor chip formed by the prior dicing method, and to improve the yield. An object of the present invention is to provide a semiconductor chip manufacturing method and a semiconductor device manufacturing method that can be improved.

  In order to solve the above-described problem, the semiconductor chip manufacturing method of the present invention provides a dicing line or chip from a predetermined dicing line or chip dividing line to an inner region on the surface side where a semiconductor element or circuit is formed on the wafer. Thickness of the wafer along the dividing line and deeper than the finished thickness of the wafer from the surface of the wafer and stopped in the middle of the thickness of the wafer so as to move away from each other in the thickness direction. Forming a notch having two side surfaces inclined opposite to each other in a direction, attaching a protective tape to the front surface of the wafer, polishing the back surface of the wafer, and thickness of the wafer And a step of separating a plurality of semiconductor chips of the wafer by reducing the thickness to the finished thickness. To have.

  According to the above invention, the width of the cut formed in the wafer increases as it becomes deeper from the circuit formation surface (this spread is set to ΔD), and therefore reaches the moment when the semiconductor chip is separated or the cut depth. The gap (clearance) between the back surface edges of adjacent separated chips increases by ΔD after polishing to a predetermined thickness. Accordingly, contact between adjacent semiconductor chips is reduced against expansion and contraction of the protective tape and mechanical stress / impact during polishing. Furthermore, since the side surface of the semiconductor chip forms an obtuse angle with respect to the polished surface of the wafer, that is, the back surface of the semiconductor chip, the stress on the edge of the back surface of the semiconductor chip is dispersed, and even if there is mechanical stress / impact during polishing, the semiconductor chip The occurrence of new chipping and chip corner chipping at the edge of the back surface can be greatly reduced.

  As described above, it is possible to provide a method of manufacturing a semiconductor chip that can reduce chipping and chip corner chipping, which are problems of a method of manufacturing a semiconductor chip formed by a conventional tip dicing method, and can improve yield. Play.

  In order to solve the above-described problems, the semiconductor chip manufacturing method of the present invention applies a protective tape to the surface of the wafer in which dicing lines or chip dividing lines are formed in the internal region on the surface side where the semiconductor elements or circuits are formed. A process of pasting, a process of polishing the back surface of the wafer to reduce the thickness of the wafer to a finished thickness, and polishing of the wafer after the polishing along a predetermined dicing line or chip dividing line of the wafer By dicing from the surface, by forming a notch having two side surfaces that are inclined to the opposite sides with respect to the thickness direction of the wafer so as to approach each other and the dicing line or the chip dividing line as proceeding in the thickness direction And a step of separating a plurality of semiconductor chips of the wafer. .

  According to the above invention, since the back surface of the wafer is polished and then the semiconductor chip is separated by forming a cut by dicing from the polished surface, chipping and chip corner chipping do not occur during polishing.

  In addition, the width of the cut formed in the wafer increases with increasing depth from the circuit formation surface. Therefore, if plasma etching is performed from the back surface after the cut is formed, the back surface of the semiconductor chip can be efficiently etched even if the direction of movement of reactive ions is perpendicular to the back surface of the semiconductor chip (anisotropic etching). Compared to the above, the arrival efficiency of the reactive ions on the side surface of the semiconductor chip is improved, the damage to the side surface of the chip caused when forming the notch can be efficiently removed, and the chip strength can be improved. .

  As described above, it is possible to provide a method of manufacturing a semiconductor chip that can reduce chipping and chip corner chipping, which are problems of a method of manufacturing a semiconductor chip formed by a conventional tip dicing method, and can improve yield. Play.

  In addition, since dicing is performed from the back surface of the wafer, it is possible to easily incline the side surface of the semiconductor chip by one dicing by using a dicing blade having an angle at the tip of the blade edge.

  In order to solve the above problems, the semiconductor chip manufacturing method of the present invention is characterized in that after the semiconductor chips are separated from each other, plasma etching is performed from the back side of the semiconductor chip.

  After polishing the back surface of the semiconductor wafer by the conventional tip dicing method, the reactive ion movement direction is perpendicular to the back surface of the semiconductor chip, particularly when anisotropic plasma etching is performed on the back surface of the divided semiconductor chip. On the other hand, while the back surface of the semiconductor chip can be etched efficiently, only a few reactive ions reach the side surface of the semiconductor chip, and the etching efficiency is poor.

  According to the above invention, even if the direction of movement of reactive ions in plasma etching is perpendicular to the back surface of the semiconductor chip, not only the back surface of the semiconductor chip can be etched efficiently, but also the side surface of the semiconductor chip is inclined. Therefore, the arrival efficiency of the reactive ions is also improved on the side surface of the semiconductor chip. Therefore, when the cut is formed, the damage to the side surface of the semiconductor chip caused by the diamond grains of the dicing blade can be removed.

  In order to solve the above problems, the semiconductor chip manufacturing method of the present invention has an angle of 45 ° between the surface of the semiconductor chip after separation and the side surface of the semiconductor chip formed by the side surface of the cut. The above-mentioned cut is formed so as to be at least 89 °.

  According to the above invention, since the angle is 45 ° or more, a sufficient edge strength on the surface of the semiconductor chip can be secured, and since the angle is 89 ° or less, the semiconductor of reactive ion of plasma Since the arrival efficiency to the side surface of the chip is improved, the damage to the side surface of the semiconductor chip can be removed.

  In order to solve the above problems, a method for manufacturing a semiconductor device according to the present invention manufactures a semiconductor chip by the method for manufacturing a semiconductor chip, mounts one or more stacked bodies of the semiconductor chips on a wiring board, A semiconductor device is manufactured by electrically connecting an external terminal on a semiconductor chip and a terminal on the wiring substrate and sealing with a sealing material.

  Conventionally, a first semiconductor chip is mounted using a paste or a film to fix the semiconductor chip on the wiring board, or a second or second is further used using the paste or film on the first semiconductor chip. When mounting multiple semiconductor chips, depending on the amount of paste or film applied and the material characteristics, the semiconductor chip surface and wiring board terminals may be contaminated by protruding from the semiconductor chip. There has been a problem that the yield is lowered by inducing a situation in which paste or film residue adheres to the collet or inducing a bonding error in the next wire bonding process.

  According to the above invention, since the side surface of the semiconductor chip has an inclination and the back surface of the semiconductor chip is hidden under the front surface, the amount of paste or film protruding is reduced, and the semiconductor chip is stably formed. There is an effect that it can be implemented.

  In order to solve the above-described problems, a method for manufacturing a semiconductor device according to the present invention is characterized in that the thickness of the semiconductor chip is 100 μm or less.

  According to the above invention, a semiconductor chip having a thickness that has been particularly problematic in the past due to chipping, chipping of chip corners, and protrusion of paste or film can be separated from the wafer and mounted on the apparatus without any problem. There is an effect.

  As described above, the semiconductor chip manufacturing method according to the present invention changes from a predetermined dicing line or chip dividing line to a dicing line or chip dividing line in an internal region on the surface side where a semiconductor element or circuit is formed on the wafer. Along the thickness direction of the wafer so that the distance from the surface of the wafer is greater than the finished thickness of the wafer and stops at the middle of the thickness of the wafer, and away from each other as it proceeds in the thickness direction. Forming a notch having two side surfaces that are inclined opposite to each other, attaching a protective tape to the front surface of the wafer, polishing the back surface of the wafer, and finishing the thickness of the wafer. A step of separating the plurality of semiconductor chips of the wafer by thinning them to a thickness.

  In addition, as described above, the method for manufacturing a semiconductor chip according to the present invention attaches a protective tape to the surface of the wafer in which dicing lines or chip dividing lines are formed in the internal region on the surface side where the semiconductor elements or circuits are formed. Attaching the wafer, polishing the back surface of the wafer to reduce the thickness of the wafer to a final thickness, and polishing the polished surface of the wafer along a predetermined dicing line or chip dividing line of the wafer. From the above, by dicing, the notch having two side surfaces that are inclined to the opposite sides with respect to the thickness direction of the wafer so as to approach each other and the dicing line or the chip dividing line as it proceeds in the thickness direction. And a step of separating a plurality of semiconductor chips on the wafer.

  Therefore, it is possible to provide a method of manufacturing a semiconductor chip that can reduce chipping and chip corner chipping, which are problems of a method of manufacturing a semiconductor chip formed by a conventional tip dicing method, and can improve yield. Play.

Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.
(First embodiment)
An embodiment of the present invention will be described with reference to FIGS. 1 and 2 as follows.

  1 (a) to 1 (7) show a process flow of the method of manufacturing a semiconductor chip of this embodiment, and FIGS. 1 (b) to 1 (7) show ( Process cross sections corresponding to 1) to (7) are shown.

  As shown in (1) of FIG. 1 (b), the dicing line or chip dicing line from each dicing line or each chip dividing line is formed in the internal region of the circuit forming surface 2 on which the semiconductor element or circuit is formed on the wafer 1. A notch 3 is formed along the chip dividing line with a depth deeper than the finished thickness of the wafer from the surface of the wafer and stopped in the middle of the thickness of the wafer, and the side surface of the notch 3 is inclined. The step of forming the cut 3 is a step of inclined dicing A ((1) in FIG. 1A).

  Next, as shown in (2) of FIG. 1B, the center of the dicing line or chip dividing line is formed in the internal region where the circuit is formed on the original wafer, compared to the formation of the notch 3 of the inclined dicing A. On the other hand, the incision 4 of the inclined dicing B is formed so as to be mirror-reversed ((2) in FIG. 1A).

  By the steps of the inclined dicing A and B, a cut formed by combining the cut 3 and the cut 4 is formed between adjacent semiconductor chips 13 (described later) to be separated from each other. The combination of the two cuts includes two side surfaces 3a and 4a that are inclined opposite to each other with respect to the thickness direction of the wafer 1 so as to move away from each dicing line or each chip dividing line in the thickness direction. It has a notch. The side surfaces 3a and 4a are two side surfaces outside the notches 3 and 4, and are used for separation of the semiconductor chip 13 later. The two side surfaces 3b and 4b inside the notches 3 and 4 may be omitted. Therefore, the notch combining the notch 3 and the notch 4 may be formed at a time so as to have the side surfaces 3a and 4a.

  Next, as shown in (3) of FIG. 1B, a protective tape 7 composed of an adhesive material 5 and a base material 6 is applied so as to cover the circuit forming surface 2 of the wafer 1 (FIG. 1 ( a) (3)). Next, as shown in (4) of FIG. 1 (b), the back surface 12 of the wafer 1 is subjected to back surface polishing by the rotating grindstone 8 ((4) of FIG. 1 (a)), and FIG. When the plurality of semiconductor chips 13 are separated from each other to form a predetermined thickness as shown in (5) of FIG. 1), the back surface polishing is completed ((5) of FIG. 1A).

  Next, as shown in (6) of FIG. 1B, wafer mounting is performed in which the back surface 13a of the semiconductor chip 13 serving as the back surface of the wafer 1 is attached to the dicing tape 11 stretched on the metal carrier frame 10 ( (6) in FIG. Next, as shown to (7) of FIG.1 (b), the surface protection tape 7 is peeled and it transfers to the following process ((7) of FIG.1 (a)).

  FIG. 2A shows an enlarged view of the Z portion in (5) of FIG. 1B, which is a cross section of the semiconductor chip 13 formed by the method shown in this embodiment. In addition, FIG. 2B shows a cross section of a conventional semiconductor chip 13 ′. If the gap between the adjacent semiconductor chips 13 and the semiconductor chip 13 'is a distance D1 on the circuit forming surface 2 side of the chip and a distance D2 on the back surface side of the chip, it is conventionally processed in a shape of D1 = D2. This embodiment is characterized by being processed so as to have a shape of D1 <D2. The incisions 3 and 4 shown in (2) of FIG. 1B may be formed in all directions to be separated from the chip. However, at least the following effects can be obtained even if formed only in a specific direction. can get. By setting D1 <D2, the angle θ formed by the surface on the circuit forming surface 2 side of the semiconductor chip 13 and the inclined surface formed by the side surfaces 3a and 4a of the cuts 3 and 4 becomes smaller than 90 °. As a result, the semiconductor chip 13 has at least a pair of inclined side surfaces with the circuit forming surface 2 side of the semiconductor chip 13 as the front surface, and has a mesa shape in which the back surface 13a is hidden directly under the surface.

  The effect of processing into the shape shown in the present embodiment is such that D1 <D2 with respect to expansion / contraction of the protective tape 7 caused by tension when the protective tape 7 is applied, heat generation of the rotating grindstone 8, and mechanical stress / impact during polishing. This makes it difficult for the back surfaces of adjacent chips 13 to come into contact with each other, thereby reducing the occurrence of back surface chipping and chip corner chipping.

  Further, since the inclined side surface of the semiconductor chip 13 is inclined so as to form an obtuse angle with the back surface 13a of the semiconductor chip 13, the back surface of the wafer 1 being separated into each semiconductor chip 13 while rotating the rotating grindstone 8 during back surface polishing. 12 (parallel to the back surface 13a), the stress at the back surface edge of the semiconductor chip 13 is dispersed and becomes strong against mechanical stress and impact. Therefore, the occurrence of chipping on the back surface of the semiconductor chip 13 and chipping of chip corners can be greatly reduced.

As described above, it is possible to provide a method of manufacturing a semiconductor chip that can reduce chipping and chip corner chipping, which are problems of a method of manufacturing a semiconductor chip formed by the conventional tip dicing method, and can improve the yield.
(Second Embodiment)
The following will describe another embodiment of the present invention with reference to FIG.

  (1) to (6) in FIG. 3 (a) show the process flow of the semiconductor chip manufacturing method of the present embodiment, and (1) to (6) in FIG. Process cross sections corresponding to 1) to (6) are shown.

  As shown in (1) of FIG. 3B, a protective tape 7 composed of an adhesive material 5 and a base material 6 is applied so as to cover the circuit forming surface 2 of the wafer 1 (in FIG. 3A). (1)). Next, as shown in (2) of FIG. 3B, the back surface 12 of the wafer 1 is subjected to back surface polishing by the rotating grindstone 8 ((2) of FIG. 3A), and FIG. When the wafer 1 reaches a specified thickness as in (3)), the back surface polishing is completed ((3) in FIG. 3A). Let the back surface of the wafer 1 after completion be the back surface 22.

  Next, as shown in (4) of FIG. 3B, the pattern of the circuit forming surface 2 of the wafer 1 is transmitted by infrared rays from the back surface 22 side of the wafer 1 along the dicing line or chip dividing line of the wafer 1. Recognizing and dicing from the back surface 22 of the wafer 1 to form a notch 23 between adjacent semiconductor chips 13 to separate them into a plurality of semiconductor chips 13 ((4) in FIG. 3A). At this time, an acute angle is provided at the tip of the cutting edge of the dicing blade, so that the side surface of the separated semiconductor chip 13 is inclined. In this state, the back surface 22 of the wafer 1 remains as the back surface 13 a of the semiconductor chip 13.

  The notch 23 has two side surfaces 23a and 23b that are inclined to the opposite sides with respect to the thickness direction of the wafer 1 so as to approach each other and the dicing line or chip dividing line as the thickness advances from the polishing surface of the wafer 1. Have

  Next, as shown in FIG. 3B (5), the back surface 13a of the semiconductor chip 13 is attached to the dicing tape 11 stretched on the metal carrier frame 10 (FIG. 3A (5)). . Next, as shown to (6) of FIG.3 (b), the surface protection tape 7 is peeled and it transfers to the following process ((6) of Fig.3 (a)).

  In this embodiment, after the back surface of the wafer 1 is polished, the semiconductor chip 13 is separated from the polished surface by forming the cuts 23 by dicing, so that chipping and chipping of chip corners do not occur during polishing.

  In addition, if plasma etching is performed after forming the notch 23 according to (4) of FIG. 3B, the reactive ion motion direction 9 (solid arrow in the figure) is perpendicular to the back surface 13a of the semiconductor chip 13 ( Even in the case of anisotropic etching, the back surface 13a of the semiconductor chip 13 can be efficiently etched, while the arrival efficiency of reactive ions on the side surface of the semiconductor chip 13 is improved compared to the conventional case, and the dicing blade is formed when the cut 23 is formed. The damage to the side surface of the chip caused by the diamond grains can be efficiently removed, and the chip strength can be improved.

  As described above, it is possible to provide a method of manufacturing a semiconductor chip that can reduce chipping and chip corner chipping, which are problems of a method of manufacturing a semiconductor chip formed by the conventional tip dicing method, and can improve the yield.

Further, since the dicing is performed from the back surface of the wafer 1, it is easy to incline the side surface of the semiconductor chip 13 by one dicing by using a dicing blade having an angle at the tip of the blade edge.
(Third embodiment)
The following will describe another embodiment of the present invention with reference to FIGS.

  In this embodiment, a plasma etching step is added to the next step of FIG. 1A (5) of the first embodiment and (4) of FIG. 3A of the second embodiment. Since the description of other steps is the same, the description thereof is omitted. According to the present embodiment, as shown in FIG. 2A, the semiconductor chip 13 has a mesa shape of D1 <D2, and the inclined side surface of the circuit forming surface 2 is formed from the edge adjacent to the inclined side surface of the back surface 13a. Adjacent edges are outside as viewed from the center of the semiconductor chip 13 in the direction perpendicular to the thickness direction. Therefore, even when the direction 9 of movement of reactive ions in plasma etching (solid arrow in the figure) is perpendicular to the back surface 13a of the semiconductor chip 13 (anisotropic etching), the back surface 13a of the semiconductor chip 13 is efficiently etched. On the other hand, the arrival efficiency of the reactive ions on the side surface of the semiconductor chip 13 can be improved compared to the conventional case, and the damage to the side surface of the chip caused by the diamond grains of the dicing blade can be efficiently removed when the cut is formed. And the chip strength can be improved. Here, when the intensity of the reactive ion in the moving direction 9 is S and the intensity of the reactive ion reaching the side surface of the semiconductor chip 13 is S ′ (dotted arrow in the figure), S′≈S · cos θ is almost equal. Follow.

Further, in the second embodiment using the normal dicing method, the chipping amount of the edge of the back surface 13a of the semiconductor chip 13 may be increased as compared with the first embodiment using the previous dicing method, but an additional plasma etching process is added. By doing so, it is possible to remove chipping.
(Fourth embodiment)
The following will describe another embodiment of the present invention with reference to FIG.

  FIG. 4A is a cross-sectional view of the semiconductor device of this embodiment. The semiconductor device in the present embodiment is an example of a two-chip stacked CSP in which the semiconductor chips 13 manufactured using any one of the semiconductor chip manufacturing methods described in the first to third embodiments are stacked in two stages. In the figure, the semiconductor chip 113 is disposed at the lower stage of the two semiconductor chips 13 and the semiconductor chip 213 is disposed at the upper stage. The semiconductor chip 113 has a larger surface area in the direction perpendicular to the thickness direction because the semiconductor chip 213 is stacked thereabove. In general, a semiconductor device in which a stacked body of one or a plurality of semiconductor chips 13 is mounted is considered.

  The thickness of one semiconductor chip 13 can be variously changed depending on the number of stacked chips and the thickness of the sealing resin. For example, when the thickness of the sealing resin 14 is 800 μm, the thickness of two chips is generally stacked. In this case, it is necessary to set the thickness to 200 μm, three chips stacked to 150 μm, four chips stacked to 100 μm, five chips stacked to 70 μm, and six chips stacked to about 50 μm.

  In particular, when the chip thickness is 100 μm or less, the chip strength is remarkably reduced. Therefore, according to the semiconductor chip 13 described in the first to third embodiments, a chip without chipping or chip corner chipping can be used. The semiconductor chip 13 having a thickness of 100 μm or less can be stably mounted.

  Further, conventionally, as shown in FIG. 4B, in order to fix the semiconductor chip 113 ′ on the surface of the wiring board 17 opposite to the surface on which the solder balls 18 are formed, an epoxy resin or a polyimide resin is used. A first semiconductor chip 113 ′ is mounted using a resin, epoxy / polyimide mixed resin paste or film 16 or the like, or a second semiconductor using paste or film 16 on the first semiconductor chip 113 ′. Chips 213 ′ (similarly, third, fourth,... Semiconductor chips are also conceivable) are sequentially mounted. At this time, depending on the application amount and material characteristics of the paste or film 16, as shown in the figure, the protruding distance X of the paste or film 16 from the semiconductor chip 113 ′ or 213 ′ increases, and the semiconductor chips 113 ′ and 213 increase. When the electrical terminals of the semiconductor chips 113 ′, 213 ′,... And the terminals on the wiring substrate 17 are electrically connected due to contamination of the surface of the circuit board terminals and the wiring board terminals. The yield is lowered by inducing a situation in which the paste or debris of the film 16 adheres to the die bonding collet or inducing a bonding error of the gold wire 15 in the next wire bonding process. The protruding distance X in FIG. 4B is about 0.5 mm to 0.8 mm when a general die bond paste is taken as an example.

  On the other hand, as shown in FIG. 4A, when the semiconductor chip is fixed on the surface of the wiring board 17 opposite to the surface on which the solder balls 18 are formed, the semiconductor chip of the first to third embodiments. 13 is used for the semiconductor chips 113 and 213. Then, the external terminals on the semiconductor chips 113 and 213 and the terminals on the wiring substrate 17 are electrically connected by die bonding or wire bonding, and sealed with a sealing resin 14 as a sealing material to manufacture a semiconductor device. To do. Each semiconductor chip 13 has a mesa shape having an inclined side surface, and the edge adjacent to the inclined side surface of the circuit forming surface 2 is closer to the thickness direction from the center of the semiconductor chip 13 than the edge adjacent to the inclined side surface of the back surface 13a. Since the shape is the outer side when viewed in the vertical direction (the back surface 13a is hidden directly under the front surface), the protrusion distance X of the paste or film 16 is reduced as the angle θ in FIG. Semiconductor chips 113 and 213 having a thickness of 100 μm or less can be mounted. From the viewpoint of realizing such a small protruding distance X, the semiconductor chip 13 is preferably formed with inclined side surfaces in all directions in which it is desired to reduce the protruding distance X of the paste or film 16.

  When the angle θ of the semiconductor chip 13 is reduced, the effect is increased to reduce the protrusion distance X. However, when the angle θ is less than 45 °, the angle θ becomes too sharp, and the circuit formation surface of the semiconductor chip 13 due to stress concentration or the like. Since edge chipping of the surface on the two sides may increase, it is desirable to ensure at least 45 ° or more. On the other hand, the effect of reducing the protrusion distance X decreases as the angle θ increases. However, when the angle θ exceeds 70 °, the protrusion distance X is substantially the same as when the side surface of the semiconductor chip 13 is not inclined (θ = 90 °). Therefore, in order to reduce the protrusion distance X while sufficiently securing the edge strength of the surface of the semiconductor chip 13 on the circuit forming surface 2 side, it is desirable that the angle θ is 45 ° or more and 70 ° or less.

However, if the purpose is to remove the damaged layer on the side surface of the semiconductor chip 13 by dicing by plasma etching, the range of the preferable angle θ is widened. Specifically, as the plasma reactive ions reach the side surface of the semiconductor chip 13 as the angle decreases from 89 ° or less, the above object is achieved when the angle θ is 45 ° or more and 89 ° or less. In addition, sufficient edge strength on the surface of the semiconductor chip can be ensured. When S = 1 in FIG. 2 (a),
When θ = 90 ° S′≈S · cos θ≈0
When θ = 89 ° S′≈S · cos θ≈0.0175 (1.75%)
This is because the efficiency of reaching plasma energy increases as θ decreases below 89 °. Even at θ = 90 °, the plasma energy actually reaches a little due to gas scattering, but the change efficiency of plasma energy is improved by the change of cos θ, so the change is large between 90 ° and 89 °, and at 89 ° As shown in the above numerical value, the arrival efficiency of plasma energy increases. Therefore, the damage layer can be further removed at an angle of 89 ° or less.

  As is clear from the above, according to the semiconductor chip manufacturing method and the semiconductor device manufacturing method according to each embodiment, even when the chip thickness is as thin as 100 μm or less, chipping of the back surface of the semiconductor chip is possible. And chip corners can be prevented and the damage layer on the side surface of the semiconductor chip can be removed, so that the yield of various semiconductor devices such as IC cards, CSPs, stacked CSPs, and multi-CSPs can be improved and stably produced. be able to.

  The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.

  The present invention can be suitably used for a semiconductor chip and its assembly for various semiconductor devices such as an IC card, a CSP, a stacked CSP, and a multi-CSP.

(A) is a flowchart which shows the process by the manufacturing method of the semiconductor chip of embodiment of this invention, (b) is process sectional drawing corresponding to the figure (a). (A) is sectional drawing which shows the processing shape of the semiconductor chip of embodiment of this invention, (b) is sectional drawing which shows the processing shape of the conventional chip | tip. (A) is a flowchart which shows the other process by the manufacturing method of the semiconductor chip of embodiment of this invention, (b) is process sectional drawing corresponding to the figure (a). (A) is sectional drawing of the semiconductor device using the semiconductor chip of the processing shape by embodiment of this invention, (b) is sectional drawing of the semiconductor device using the semiconductor chip of the conventional processing shape.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Wafer 2 Circuit formation surface 3 Notch 3a Side surface 4 Notch 4a Side surface 5 Adhesive material 6 Base material 7 Protective tape 8 Rotary grindstone 9 Direction of movement of reactive ion of anisotropic plasma etching 10 Metal carrier 11 Dicing tape 12 Back surface 13 Semiconductor Chip 13a Back surface 14 Sealing material 15 Gold wire 16 Paste or film 17 Wiring board 18 Solder ball 22 Back surface 23a Side surface 23b Side surface

Claims (6)

Finishing thickness of the wafer from a predetermined dicing line or chip dividing line along the dicing line or chip dividing line and from the surface of the wafer to an inner region on the surface side where semiconductor elements or circuits are formed on the wafer A notch having two side surfaces that are inclined to the opposite sides with respect to the thickness direction of the wafer so as to move away from each other in the thickness direction at a depth that is deeper and stops in the middle of the thickness of the wafer, Forming, and
Attaching a protective tape to the surface of the wafer;
And a step of separating the plurality of semiconductor chips of the wafer by polishing the back surface of the wafer and reducing the thickness of the wafer to the finished thickness. A step of attaching a protective tape to the surface of the wafer on which a dicing line or a chip dividing line is formed in the inner region on the surface side where the semiconductor element or circuit is formed;
Polishing the backside of the wafer and reducing the thickness of the wafer to a finished thickness;
Dicing along the predetermined dicing line or chip dividing line of the wafer from the polished surface of the wafer after polishing so that the wafers approach each other and the dicing line or chip dividing line as they progress in the thickness direction. And a step of separating the plurality of semiconductor chips of the wafer by forming a notch having two side surfaces inclined in opposite directions with respect to the thickness direction of the semiconductor chip.   3. The method of manufacturing a semiconductor chip according to claim 1, wherein after the semiconductor chips are separated from each other, plasma etching is performed from the back side of the semiconductor chip.   The notch is formed so that an angle formed between the surface of the semiconductor chip after separation and the side surface of the semiconductor chip formed by the side surface of the notch is 45 ° or more and 89 ° or less. The method for manufacturing a semiconductor chip according to claim 1.   A semiconductor chip is manufactured by the method for manufacturing a semiconductor chip according to any one of claims 1 to 4, and a laminated body of one or a plurality of the semiconductor chips is mounted on a wiring board, and the external terminals on the semiconductor chip and the above-mentioned A semiconductor device manufacturing method comprising manufacturing a semiconductor device by electrically connecting terminals on a wiring board and sealing with a sealing material.   6. The method of manufacturing a semiconductor device according to claim 5, wherein the thickness of the semiconductor chip is 100 [mu] m or less.

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