JP2005166807A - Method for manufacturing semiconductor element and method for segmenting substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor element having high planarity on the side opposite to a side where a circuit element is formed. <P>SOLUTION: A plurality of circuit elements and bump electrodes 12 are formed on one surface 11a of a semiconductor wafer 11 and a dicing groove 14 reaching the interior of the semiconductor wafer 11 is formed from one surface 11a of the semiconductor wafer 11 to define a region including one integrated circuit comprising the circuit element and the bump electrodes 12. A filler layer 15 is formed by filling the dicing groove 14 with a filler and after the other surface 11b of the semiconductor wafer 11 is polished until the filler layer 15 is exposed, the filler layer 15 is removed and the semiconductor wafer 11 is segmented thus manufacturing a semiconductor element 1. Since the dicing groove 14 is filled with the filler layer 15 when the other surface 11b of the semiconductor wafer 11 is polished, meandering due to polishing is prevented and planarity can be secured on the other surface 11b of the semiconductor wafer 11 after polishing. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor element manufacturing method for manufacturing a plurality of semiconductor elements from a single semiconductor substrate, and a substrate dividing method for dividing a substrate such as a semiconductor substrate into predetermined regions.

  A semiconductor device mounted on an electronic device such as a cellular phone or an integrated circuit (abbreviated name: IC) card has a semiconductor having an electronic circuit composed of various circuit elements on a wiring board on which wirings are formed. A plurality of elements are mounted.

  The manufacturing process of the semiconductor device was obtained by forming a plurality of electronic circuit patterns on one surface of the semiconductor wafer, and manufacturing a plurality of semiconductor elements by dividing the semiconductor wafer for each electronic circuit pattern. The process is roughly divided into a process of mounting a semiconductor element on a wiring board directly or in a package.

  Due to demands for thinning electronic devices such as mobile phones and IC cards, thinning is also required for semiconductor devices mounted on these electronic devices. In order to reduce the thickness of the semiconductor device, it is necessary to reduce the thickness of the semiconductor element. When reducing the thickness of the semiconductor element, the thickness of the entire semiconductor wafer is usually polished by polishing the other surface of the semiconductor wafer, that is, the surface opposite to the surface on which the pattern of the electronic circuit is formed, using a polishing grinder. Thin out. Thereafter, the semiconductor wafer is cut into pieces and manufactured into semiconductor elements.

  With the recent increase in demand for thinning electronic devices such as mobile phones and IC cards, further thinning of semiconductor elements is required. In addition, in order to improve the production efficiency of semiconductor elements, the diameter of semiconductor wafers has been increased. However, when manufacturing a thin semiconductor element from a semiconductor wafer having a large diameter, if the method of cutting the semiconductor wafer after polishing and thinning the semiconductor wafer is used, the bending strength of the semiconductor wafer is polished. Since the thickness decreases due to thinning, there is a problem that the semiconductor wafer is damaged during the manufacturing process, for example, in the process of transporting the polished semiconductor wafer to an apparatus used for cutting.

  Further, when polishing a semiconductor wafer, a fine crack is formed on a surface exposed by polishing the semiconductor wafer, that is, a polished surface. Further, when the semiconductor wafer is cut, a fine crack is formed on the cut surface formed by cutting the semiconductor wafer. This fine cracked portion is called a crushed layer and causes damage to the semiconductor wafer when an external stress is applied. The crushed layer generated by this polishing and cutting remains in each semiconductor element obtained after cutting the semiconductor wafer. Therefore, when the semiconductor element is manufactured by the above-described method, the bending strength of the semiconductor element is lowered, and there is a problem that the semiconductor element is damaged when the semiconductor element is mounted on the wiring board.

  As a technique for solving such a problem, a dicing groove whose depth reaches the inside of the semiconductor substrate from one surface of the semiconductor wafer is formed in advance, and then the other surface of the semiconductor wafer is polished to reach the dicing groove. A method called a pre-dicing method has been proposed in which a semiconductor element is manufactured by separating a wafer into individual pieces (see, for example, Patent Document 1).

  Hereinafter, a method of manufacturing a semiconductor device by a conventional tip dicing method will be described. 13 to 16 are cross-sectional views schematically showing the state of each step in the production of a semiconductor device by the conventional tip dicing method.

  FIG. 13 is a view showing a state in which the protruding electrode 52 is formed on one surface 51 a of the semiconductor wafer 51. A plurality of electronic circuit patterns including circuit elements (not shown) and protruding electrodes 52 electrically connected to the circuit elements are formed on one surface 51 a of the semiconductor wafer 51. Next, a scribe line (not shown) is formed on one surface 51a of the semiconductor wafer 51 on which the protruding electrodes 52 are formed so as to define each electronic circuit.

  FIG. 14 is a view showing a state where the dicing grooves 53 are formed. The semiconductor wafer 51 is cut along the formed scribe line, and a dicing groove 53 whose depth reaches the inside of the semiconductor wafer 51 from one surface 51 a of the semiconductor wafer 51 is formed.

  FIG. 15 is a diagram illustrating a state in which the protection member 54 is provided. A protective member 54 is provided on one surface 51a of the semiconductor wafer 51 on which the protruding electrodes 52 are formed so as to cover the protruding electrodes 52 and the circuit elements. As the protective member 54, a protective tape formed by applying an adhesive on a base material is often used because of easy handling. The protective tape is attached so that the adhesive contacts one surface 51 a of the semiconductor wafer 51.

  FIG. 16 is a diagram showing how the other surface 51 b of the semiconductor wafer 51 is polished. One surface 51 a of the semiconductor wafer 51 provided with the protection member 54 is opposed to the polishing chuck table 55, and the semiconductor wafer 51 is fixed to the polishing chuck table 55 via the protection member 54. In this state, the other surface 51 b of the semiconductor wafer 51 is polished until reaching the dicing groove 53, and the semiconductor wafer 51 is separated into individual pieces to obtain the semiconductor element 50. When polishing the other surface 51 b of the semiconductor wafer 51, the polishing grindstone 56 is lowered downward toward the paper surface of FIG. 16 while rotating in the direction of the arrow 70 around the axis 58 of the grindstone shaft 57. Then, the other surface 51b of the semiconductor wafer 51 is pressed to polish the other surface 51b of the semiconductor wafer 51.

  When the protective member 54 is not provided on one surface 51a of the semiconductor wafer 51, the semiconductor wafer 51 is placed so that the one surface 51a faces the polishing chuck table 55, and the other surface 51b is formed. When the polishing is performed, there is a problem that the uneven shape of one surface 51 a of the semiconductor wafer 51 generated by the formation of the protruding electrode 52 is transferred to the other surface 51 b of the semiconductor wafer 51. This is due to the following reason.

  When the protective member 54 is not provided on the one surface 51 a of the semiconductor wafer 51, the protruding electrode 52 is in an exposed state. Therefore, the semiconductor wafer 51 is placed on the polishing chuck table 55 so that the protruding electrode 52 is in contact therewith. Is done. In this state, when the polishing grindstone 56 is pressed against the other surface 51 b of the semiconductor wafer 51, the load applied to the semiconductor wafer 51 from the polishing grindstone 56 via the protruding electrode 52 is the polishing chuck table 55. To be loaded.

  On the other hand, a drag acts on the applied load from the polishing chuck table 55. Since the drag force from the polishing chuck table 55 acts on the semiconductor wafer 51 via the bump electrode 52, the drag force acting on the polishing grindstone 56 from the semiconductor wafer 51 is greater in the portion where the bump electrode 52 is provided. It becomes larger than the portion without the electrode 52. That is, the other surface 51 b of the semiconductor wafer 51 is not brought into contact with the surface 56 a of the polishing grindstone 56 facing the semiconductor wafer 51 with a uniform force.

  Therefore, the force with which the polishing grindstone 56 presses the other surface 51 b of the semiconductor wafer 51, that is, the pressing force from the polishing grindstone 56 loaded on the other surface 51 b of the semiconductor wafer 51, is as follows. Unlike the portion without the protruding electrode 52, the portion with the protruding electrode 52 is larger than the portion without the protruding electrode 52. For this reason, the concavo-convex shape formed by the protruding electrode 52 formed on the one surface 51 a of the semiconductor wafer 51 is transferred to the other surface 51 b of the semiconductor wafer 51.

  The pressing force applied to the other surface 51b of the semiconductor wafer 51 from the polishing grindstone 56 is made constant regardless of the portion where the protruding electrode 52 is present and the portion where the protruding electrode 52 is not present. In order to prevent the uneven shape from being transferred to the other surface 51b, it is necessary to flatten the one surface 51a side of the semiconductor wafer 51 so that the drag from the polishing chuck table 55 acts uniformly.

  Therefore, as shown in FIG. 16, a protection member 54 is provided on one surface 51 a of the semiconductor wafer 51, and the unevenness of the one surface 51 a of the semiconductor wafer 51 is covered with the protection member 54, whereby one surface 51 a of the semiconductor wafer 51 is covered. The side is made flat so that the drag from the polishing chuck table 55 is uniformly applied to the entire one surface 51 a side of the semiconductor wafer 51. As a result, the drag force from the polishing chuck table 55 acting on the semiconductor wafer 51 can be made substantially equal between the portion with the protruding electrode 52 and the portion without the protruding electrode 52, so that the polishing grindstone 56 is pressed. In this state, the pressing force applied to the other surface 51b of the semiconductor wafer 51 from the polishing grindstone 56 can be made substantially uniform over the entire other surface 51b.

  As described above, in the prior dicing method described in Patent Document 1 or the like, after forming the dicing groove 53 in the step shown in FIG. 14, the semiconductor wafer 51 is polished and thinned in the step shown in FIG. By doing so, the process of handling the thinned semiconductor wafer 51 is reduced, and the damage of the semiconductor wafer 51 during the manufacturing process is suppressed. In the technique described in Patent Document 1, after the polishing step shown in FIG. 16, the other polished surface 51b of the semiconductor wafer 51 is chemically etched to remove the crushed layer on the polished surface. Manufactures thin semiconductor elements with high bending strength.

JP 2002-16021 A (page 3-4, FIG. 1-6)

  In the prior dicing method described in Patent Document 1 and the like described above, when the other surface 51b of the semiconductor wafer 51 is polished in the step shown in FIG. Then, the portion 59 to be the semiconductor element 50 defined by the dicing groove 53 is in contact with the protective member 54. For this reason, when the protective member 54 is not provided, the pressing force applied from the polishing grindstone 56 to the other surface 51b of the semiconductor wafer 51 is divided between the portion with the protruding electrode 52 and the portion without the protruding electrode 52. Similarly, the pressing force applied from the polishing grindstone 56 to the other surface 51 b of the semiconductor wafer 51 differs between the portion 53 a where the dicing groove 53 is formed and the portion 59 defined by the dicing groove 53. Therefore, even if the protective member 54 is provided, the other surface 51b of the semiconductor wafer 51 is uniform with respect to the surface 56a of the polishing grindstone 56 facing the semiconductor wafer 51 when the polishing grindstone 56 is pressed. It is not abutted by force.

  Further, each portion 59 defined by the dicing groove 53 of the semiconductor wafer 51 is parallel to the surface 56 a of the polishing grindstone 56 facing the semiconductor wafer 51 based on the rotation around the axis 58 of the polishing grindstone 56. It is inclined toward the inner side of the dicing groove 53 by a force acting in a different direction.

  Therefore, when the semiconductor element 50 is manufactured using the tip dicing method described in the above-mentioned Patent Document 1 or the like, the other surface 51b of the semiconductor wafer 51 is wavy as shown in FIG. .

  This undulation is more likely to occur when a soft member in contact with the semiconductor wafer 51 such as a protective tape is used as the protective member 54. This is because the semiconductor wafer 51 sinks into the protective member 54 due to a load from the polishing grindstone 56, and each portion 59 defined by the dicing groove 53 of the semiconductor wafer 51 is likely to be inclined toward the inner side of the dicing groove 53. . In particular, when the thickness of the base material of the protective tape and the adhesive is increased so that the unevenness of the one surface 51a of the semiconductor wafer 51 is reliably covered, the occurrence of waviness becomes significant.

  Further, as described above, the semiconductor element is directly or packaged and mounted on a wiring board and used for a semiconductor device. In order to satisfy the above-described demand for thinning the semiconductor device, it is necessary to use a flip chip connection method as a connection method between the semiconductor element and the wiring board. Also, when a semiconductor element is packaged, it is necessary to use a flip chip connection method to connect the semiconductor element and the wiring board of the package in order to reduce the thickness of the package.

  FIG. 17 is a cross-sectional view schematically showing how the semiconductor element 50 and the wiring board 60 are connected by a flip-chip connection method. When the semiconductor element 50 and the wiring board 60 are connected by the flip chip connection method, as shown in FIG. 17, the protruding electrode 52 provided on the surface of the semiconductor element 50 and the wiring provided on the surface of the wiring board 60. The projecting electrode 52 and the wiring electrode 61 are electrically connected by directly facing the contact electrode 61 and applying a load with the bonding tool 62 and heating from above the semiconductor element 50.

  When the semiconductor element 50 and the wiring substrate 60 are connected by the flip chip connection method, the surface that contacts the bonding tool 62 on the opposite side to the surface on which the protruding electrode 52 of the semiconductor element 50, that is, the semiconductor that constitutes the semiconductor element 50. If waviness occurs on the other surface 51b of the wafer 51 as shown in FIG. 16, the following problem occurs. The semiconductor element 50 in which the undulation is generated on the other surface 51 b of the semiconductor wafer 51 cannot be brought into contact with the bonding tool 62 as a whole, so that the other surface 51 b is fixed while being inclined with respect to the bonding tool 62. For this reason, one surface 51 a of the semiconductor wafer 51, which is the surface on which the protruding electrode 52 of the semiconductor element 50 is formed, cannot be opposed in parallel to the surface 60 a of the wiring substrate 60 facing the semiconductor element 50. Therefore, of the two protruding electrodes 52 provided in the semiconductor element 50, one protruding electrode 52 and the wiring electrode 61 can be connected well, but the other protruding electrode 52 and the wiring electrode 61 are good. The problem of being unable to connect to the network arises.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor element manufacturing method capable of obtaining a semiconductor element having a high bending strength, a thin thickness, and a flatness on the surface opposite to the surface on which the circuit element is formed, and an individual element. It is an object of the present invention to provide a method for separating a substrate, which can ensure the flatness of the separated substrate surface.

The present invention includes a step of forming a plurality of circuit elements on one surface of a semiconductor substrate;
Forming a dicing groove whose depth reaches the inside of the semiconductor substrate from one surface of the semiconductor substrate so as to define a predetermined region that includes at least one circuit element; ,
Filling the dicing grooves with a filler;
Polishing the other surface of the semiconductor substrate until at least the filler filled in the dicing grooves is exposed;
And removing the filler filled in the dicing grooves to divide the semiconductor substrate into individual pieces.

Further, the present invention is after the step of filling the dicing groove with a filler, and before the step of polishing the other surface of the semiconductor substrate at least until the filler filled in the dicing groove is exposed. ,
The method further includes a step of providing a protective member on one surface of the semiconductor substrate so as to cover the circuit element.

Furthermore, the present invention removes the filler filled in the dicing grooves and separates the semiconductor substrate into pieces,
The method further includes a step of etching at least one of the surface exposed by the polishing of the semiconductor substrate and the surface exposed by removing the filler.

Furthermore, the present invention includes a step of etching at least one of the surface exposed by the polishing of the semiconductor substrate and the surface exposed by removing the filler.
A portion of 1 μm or more and 10 μm or less is removed by etching from the surface exposed by the polishing of the semiconductor substrate and the surface exposed by removing the filler.

Furthermore, the present invention includes a step of etching at least one of the surface exposed by the polishing of the semiconductor substrate and the surface exposed by removing the filler.
The portions of 30 μm or more and 50 μm or less are removed by etching from the surface exposed by the polishing of the semiconductor substrate and the surface exposed by removing the filler, respectively.

Furthermore, the present invention includes a step of etching at least one of the surface exposed by the polishing of the semiconductor substrate and the surface exposed by removing the filler.
Etching is performed by chemical etching using an etching solution.

Furthermore, the present invention includes a step of filling the dicing groove with a filler.
The ratio R (D1 / D2) between the thickness D1 of the filling layer formed by filling the dicing grooves with the filler and the depth D2 of the dicing grooves is 0.8 or more and 1.0 or less. It is characterized by.

Furthermore, the present invention is characterized in that the filler is a resin.
Furthermore, the present invention is characterized in that the resin is a photo-curing resin and is cured after being filled in the dicing grooves.

Further, the present invention is a method for dividing a substrate into pieces for each predetermined region,
Forming a dicing groove whose depth reaches the inside of the substrate from one surface of the substrate so as to define a predetermined region;
Filling the dicing grooves with a filler;
Polishing the other surface of the substrate until at least the filler filled in the dicing grooves is exposed;
And a step of removing the filling material filled in the dicing grooves.

  According to the present invention, a semiconductor element is formed by forming a plurality of circuit elements on one surface of a semiconductor substrate, and defining a predetermined area that includes at least one circuit element. Forming a dicing groove whose depth reaches the inside of the semiconductor substrate from one surface of the substrate, filling the dicing groove with a filler, and polishing the other surface of the semiconductor substrate until at least the filler filled in the dicing groove is exposed After that, the semiconductor substrate is manufactured by removing the filler filled in the dicing grooves and separating the semiconductor substrate. Here, the semiconductor element is composed of only one circuit element, one having a plurality of circuit elements, one having only one circuit composed of a plurality of circuit elements, and composed of a plurality of circuit elements. Any of those having a plurality of circuits is included. When polishing the other surface of the semiconductor substrate, the dicing grooves are filled with a filler. Thus, when polishing the other surface of the semiconductor substrate by applying a load to the semiconductor substrate with the grindstone, the pressing force applied from the grindstone to the portion where the dicing groove is formed on the semiconductor substrate, The difference from the pressing force applied to the part defined by the dicing groove can be reduced. Further, when a force acts in a direction parallel to the surface of the grindstone used for polishing facing the semiconductor substrate of the grindstone, it is possible to prevent each portion defined by the dicing grooves of the semiconductor substrate from being inclined toward the inner side of the dicing grooves. it can. Therefore, the occurrence of waviness on the other surface of the semiconductor substrate due to polishing can be prevented, and the flatness of the other surface of the semiconductor substrate after polishing can be ensured.

  In addition, after forming the dicing grooves as described above, the semiconductor substrate is thinned by polishing the other surface of the semiconductor substrate, thereby reducing the number of steps for handling the thinned semiconductor substrate. Therefore, a thin semiconductor element can be manufactured with a high yield. Therefore, it is possible to obtain a semiconductor element that is thin and has high flatness on the other surface of the semiconductor substrate, that is, the surface opposite to the surface on which the circuit element is formed.

  According to the invention, the semiconductor substrate in which the dicing groove is filled with the filler is provided with the protective member so as to cover the circuit element on one surface, and then the other surface is polished. As described above, when the other surface of the semiconductor substrate is polished, the dicing groove is filled with the filler, so that when the protective member is provided on one surface of the semiconductor substrate in this way, Even if the other surface of the semiconductor substrate is polished in this state, the semiconductor substrate is parallel to the surface of the grindstone facing the semiconductor substrate. When a force acts in the direction, each portion defined by the dicing groove of the semiconductor substrate can be prevented from being inclined toward the inner side of the dicing groove. In addition, even when the electrode of the circuit element or the electrode electrically connected to the circuit element is provided as a protruding electrode protruding from one surface of the semiconductor substrate, Since the unevenness is covered with the protective member, one surface side of the semiconductor substrate can be flattened. As a result, when the other surface of the semiconductor substrate is polished with the semiconductor substrate placed so that the one surface faces the support substrate, the drag from the support substrate is applied to the entire one surface side of the semiconductor substrate. It can be applied uniformly. In this way, the pressing force applied to the other surface of the semiconductor substrate from the grindstone can be made constant regardless of the portion with the protruding electrode and the portion without the protruding electrode. It is possible to prevent the concavo-convex shape formed by the protruding electrodes formed on the surface of the semiconductor substrate from being transferred to the other surface. Therefore, it is possible to manufacture a semiconductor element having a higher flatness on the surface opposite to the surface on which the circuit element is formed.

  In addition, when removing the filling material filled in the dicing grooves and separating the semiconductor substrate into individual pieces, a protective member is provided on one surface of the semiconductor substrate. It is divided into pieces in a continuous state. Therefore, after the step of dividing the semiconductor substrate into pieces, a process such as etching can be simultaneously performed on the separated semiconductor substrate, so that the production efficiency can be improved.

  According to the invention, the semiconductor substrate separated into pieces by removing the filler filled in the dicing grooves has at least one of a surface exposed by polishing, that is, a polished surface and a surface exposed by removing the filler. One of them is etched. By this, both or one of the crushed layer formed on the polishing surface of the semiconductor substrate during polishing and the crushed layer formed on the surface facing the dicing groove of the semiconductor substrate when forming the dicing groove, It can be removed by etching. Therefore, since the crushing layer that causes damage can be reduced, a semiconductor element with high bending strength can be manufactured.

  Further, according to the present invention, a portion of 1 μm to 10 μm from the polished surface of the semiconductor substrate and a portion of 1 μm to 10 μm from the surface exposed by removing the filler are removed by etching. Therefore, it is possible to reliably remove the crushing layer formed on the polishing surface of the semiconductor substrate during polishing and reduce the crushing layer formed on the surface facing the dicing groove of the semiconductor substrate when forming the dicing groove. Therefore, a semiconductor element with higher bending strength can be manufactured.

  Further, according to the present invention, the portion of 30 μm or more and 50 μm or less from the polished surface of the semiconductor substrate and the portion of 30 μm or more and 50 μm or less from the surface exposed by removing the filler are removed by etching. Therefore, both the crushing layer formed on the polishing surface of the semiconductor substrate during polishing and the crushing layer formed on the surface facing the dicing groove of the semiconductor substrate when forming the dicing groove can be reliably removed. Therefore, a semiconductor element with particularly high bending strength can be manufactured.

  Further, according to the present invention, etching of the polished surface of the semiconductor substrate and the surface exposed by removing the filler is performed by chemical etching using an etchant. As a result, the corners of the separated semiconductor substrate can be rounded to have a curvature and so-called corners R can be formed, so that the bending strength of the semiconductor element can be improved. In addition, when performing chemical etching using an etching solution in this way, a protective member is provided on one surface of the semiconductor substrate to prevent the etching solution from contacting one surface of the semiconductor substrate during etching. Therefore, the chemical etching can be performed without contaminating the circuit element provided on one surface of the semiconductor substrate with the etching solution.

  According to the present invention, the ratio R (D1 / D2) between the thickness D1 of the filling layer formed by filling the dicing grooves with the filler and the depth D2 of the dicing grooves is 0.8 or more and 1.0. It is as follows. Here, the ratio R (D1 / D2) is a straight line that is substantially perpendicular to the virtual plane α including one surface of the semiconductor substrate and intersects the exposed surface of the filling layer and the bottom surface of the dicing groove. In the above, the distance from the intersection A between the virtual straight line L and the exposed surface of the filling layer to the intersection B between the virtual straight line L and the bottom surface of the dicing groove is defined as a filling layer thickness D1, and the virtual straight line L and the virtual This is the value when the distance from the intersection C with the plane α to the intersection B between the virtual straight line L and the bottom surface of the dicing groove is the depth D2 of the dicing groove. By setting the ratio R to 0.8 or more, generation of voids in the filling layer is suppressed, and sufficient strength of the filling layer against the pressing force by the grindstone when polishing the other surface of the semiconductor substrate is ensured. be able to. Therefore, the pressing force applied from the grindstone to the portion where the dicing groove of the semiconductor substrate is formed can be made substantially equal to the pressing force applied from the grindstone to the portion defined by the dicing groove of the semiconductor substrate. Further, when a force acts in a direction parallel to the surface of the grindstone facing the semiconductor substrate, it is possible to reliably prevent each portion defined by the dicing grooves of the semiconductor substrate from being inclined toward the inner side of the dicing grooves. Further, by forming the filling layer so that the ratio R is 1.0 or less, that is, the surplus filler other than filling the dicing grooves does not protrude onto one surface of the semiconductor substrate, It is possible to prevent the circuit element provided on one surface from being contaminated with the filler.

  Further, according to the present invention, since the filler filled in the dicing grooves is resin, it can be easily filled up to the bottom of the dicing grooves and can be easily removed by the stripping solution. Further, when the resin is used for the filler as described above and the filler is removed by the stripping solution, a protective member is provided on one surface of the semiconductor substrate so that the stripping solution is removed from the semiconductor substrate when the filler is removed. Since contact with one surface can be prevented, the filler can be removed without contaminating the circuit element provided on one surface of the semiconductor substrate with the stripping solution.

  Further, according to the present invention, the filling material filled in the dicing grooves is a photo-curing resin such as a resist, and is filled after the dicing grooves are cured, so that the dicing grooves are filled with the filling material. The packed bed is hard. Accordingly, the strength of the filling layer against the pressing force by the grindstone when polishing the other surface of the semiconductor substrate can be sufficiently ensured, so that the pressing force applied from the grindstone to the portion where the dicing grooves of the semiconductor substrate are formed And the pressing force applied to the portion defined by the dicing groove of the semiconductor substrate from the grindstone can be made substantially equal. Further, when a force acts in a direction parallel to the surface of the grindstone facing the semiconductor substrate, it is possible to reliably prevent each portion defined by the dicing grooves of the semiconductor substrate from being inclined toward the inner side of the dicing grooves.

  According to the invention, the substrate forms a dicing groove whose depth reaches the inside of the substrate from one surface of the substrate so as to define a predetermined region, and the dicing groove is filled with the filler, After polishing the other surface of the substrate until the filling material filled in the dicing groove is exposed, the substrate is separated into pieces by removing the filling material filled in the dicing groove. When polishing the other surface of the substrate, the dicing grooves are filled with a filler. As a result, when polishing the other surface of the substrate by applying a load to the substrate with the grindstone, the pressing force applied to the portion where the dicing groove is formed on the substrate from the grindstone and the dicing groove on the substrate from the grindstone The difference from the pressing force applied to the applied portion can be reduced. Further, when a force acts in a direction parallel to the surface of the grindstone used for polishing facing the substrate of the grindstone, each portion defined by the dicing grooves of the substrate can be prevented from being inclined toward the inner side of the dicing grooves. Accordingly, the occurrence of waviness on the other surface of the substrate due to polishing can be prevented, and the flatness of the other surface of the singulated substrate can be ensured.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings, but the present invention is not limited thereto.

  As a method for manufacturing a semiconductor element according to an embodiment of the present invention, a method for manufacturing a semiconductor element 1 having an integrated circuit formed by integrating a plurality of circuit elements will be described below. 1-12 is a figure which shows typically the state of each process in manufacture of the semiconductor element 1. As shown in FIG.

  FIG. 1A is a cross-sectional view showing a state in which the protruding electrode 12 and the scribe line 13 are formed on one surface 11 a of the semiconductor wafer 11. FIG. 1B is a plan view showing the semiconductor wafer 11 on which the protruding electrode 12 and the scribe line 13 shown in FIG. 1A are formed as viewed from the one surface 11a side. FIG. This corresponds to a cross-sectional view taken along the section line II shown in FIG. In FIG. 1B, since the drawing is complicated and difficult to understand, only a part of the protruding electrode 12 shown in FIG. 1A is described, and the scribe line 13 is represented by a straight line.

  A plurality of circuit elements (not shown) are formed on one surface 11a of the semiconductor wafer 11 which is a semiconductor substrate. Several circuit elements are integrated and formed, and are electrically connected by an electric wiring (not shown) to constitute a plurality of integrated circuits. Examples of circuit elements constituting the integrated circuit include active elements such as diodes and transistors, and passive elements such as capacitors and resistors. Projecting electrodes 12 that are electrically connected to circuit elements directly or through electrical wiring are formed at predetermined positions of the integrated circuits provided on one surface 11a of the semiconductor wafer 11, respectively. The protruding electrode 12 is formed so as to protrude from one surface 11 a of the semiconductor wafer 11. Thus, by providing the protruding electrode 12 so as to protrude from the one surface 11a of the semiconductor wafer 11, the one surface 11a of the semiconductor wafer 11 becomes uneven.

  The semiconductor wafer 11 is a substrate made of a semiconductor material such as silicon. The protruding electrode 12 is formed of a conductive material such as lead (chemical formula: Pb) -tin (chemical formula: Sn) based solder or gold (chemical formula: Au). In the present embodiment, a semiconductor wafer 11 having a thickness T1, which is a distance from one surface 11a to the other surface 11b, of 725 μm is used as the protruding electrode 12, and the height from one surface 11a of the semiconductor wafer 11 is high. A film having a height H of 20 μm is formed.

  A predetermined region on the one surface 11a of the semiconductor wafer 11 on which the protruding electrode 12 is formed is defined as a region including one integrated circuit including a plurality of circuit elements and the protruding electrodes 12. A scribe line 13 is formed by making a cut with a diamond cutter or the like. In the present embodiment, the scribe line 13 is linearly extended in the vertical direction toward the paper surface of FIG. 1B and linearly extended in the horizontal direction, and is formed in a lattice shape. Each region includes one integrated circuit provided with two protruding electrodes 12.

  FIG. 2A is a cross-sectional view showing a state where the dicing grooves 14 are formed. FIG. 2B is a plan view showing the semiconductor wafer 11 formed with the dicing grooves 14 shown in FIG. 2A as viewed from one surface 11a side, and FIG. This corresponds to a cross-sectional view seen from the section line II shown in b). In FIG. 2B, only a part of the protruding electrode 12 shown in FIG. 2A is described because the drawing is complicated and difficult to understand.

  Along the formed scribe line 13, the semiconductor wafer 11 is cut from one surface 11a with a diamond blade or the like to form a groove that does not reach the other surface 11b. As a result, a dicing groove 14 whose depth reaches the inside of the semiconductor wafer 11 from one surface 11 a of the semiconductor wafer 11 is formed. Like the scribe line 13, the dicing groove 14 is a predetermined region, and defines a region including one integrated circuit composed of a plurality of circuit elements and protruding electrodes 12, as shown in FIG. b) extends linearly in the vertical direction toward the paper surface and linearly extends in the horizontal direction, and is formed up to the end of the semiconductor wafer 11.

  In the present embodiment, the dicing groove 14 has a cross-sectional shape viewed from the cutting plane line II shown in FIG. 2B and a cross-sectional shape viewed from the cutting plane line II-II, as shown in FIG. ) To form a concave shape. That is, in the dicing groove 14 according to the present embodiment, the bottom surface 14 a is substantially parallel to the one surface 11 a of the semiconductor wafer 11, and the wall surface 14 b is substantially perpendicular to the one surface 11 a of the semiconductor wafer 11. ing.

  The depth D2 of the dicing groove 14 is set in order to cut the semiconductor wafer 11 for each portion to be the semiconductor element 1 by polishing the other surface 11b of the semiconductor wafer 11 in the step shown in FIG. It is necessary to be at least 1.0 times the thickness T2 of the semiconductor element 1 shown in FIG. 1, and is preferably about 1.0 to 1.2 times the thickness T2. Here, the depth D2 of the dicing groove 14 is the distance from the virtual plane α including the one surface 11a of the semiconductor wafer 11 to the bottom surface 14a of the dicing groove 14. Further, the thickness T2 of the semiconductor element 1 shown in FIG. 9 is a distance from one surface 11a of the semiconductor wafer 11 constituting the semiconductor element 1 to the other surface 11b.

  However, when the polished surface 11b of the semiconductor wafer 11 is etched in the process shown in FIG. 9 to be described later as in the present embodiment, the depth D2 of the dicing groove 14 is removed by etching. The thickness of the portion to be formed needs to be larger than the thickness T2, and is preferably about 1.2 times the thickness T2. In this embodiment, the semiconductor element 1 is manufactured with the thickness T2 of 100 μm, and the dicing groove 14 is formed so that the depth D2 is about 120 μm.

  The dicing groove 14 does not need to be formed so that the bottom surface 14a is substantially parallel to the virtual plane α including the one surface 11a of the semiconductor wafer 11. For example, as shown in FIG. The cross-sectional shape seen from the cutting plane line II shown in (b) and the cross-sectional shape seen from the cutting plane line II-II are both U-shaped, that is, the bottom surface 14a has a curvature. It may be formed.

  Thus, when the bottom surface 14 a of the dicing groove 14 is not substantially parallel to the virtual plane α including the one surface 11 a of the semiconductor wafer 11, the distance is from the virtual plane α to the bottom surface 14 a of the dicing groove 14. The depth D2 of the dicing groove 14 described above is different in each part of the dicing groove 14. In such a case, the minimum value of the depth D2 of the dicing groove 14, that is, the shortest distance D2min from the virtual plane α to the bottom surface 14a of the dicing groove 14 is 1.0 to 1 of the thickness T2 of the semiconductor element 1. It is preferably about 2 times. For example, when the bottom surface 14a of the dicing groove 14 has a curvature as shown in FIG. 3, the distance from the virtual plane α to the curvature start point P of the bottom surface 14a is the minimum value D2min. The dicing grooves 14 are preferably formed so that this value is about 1.0 to 1.2 times the thickness T2 of the semiconductor element 1.

  FIG. 4A is a cross-sectional view showing a state in which the filling layer 15 is formed. FIG. 4B is a diagram showing a state in which the dicing groove 14 is filled with a filler, and FIG. 4A is a cross-sectional view seen from the cutting plane line II shown in FIG. Equivalent to. In FIG. 4B, only part of the protruding electrode 12 shown in FIG. 4A is described because the drawing is complicated and difficult to understand.

  The formed dicing groove 14 is filled with a filler to form a filling layer 15. Since the dicing groove 14 is formed up to the end of the semiconductor wafer 11 as described above, when filling the dicing groove 14 with a filler, as shown in FIG. 4B, the outer edge of the semiconductor wafer 11 is formed. It is preferable that the filler is supplied to the dicing groove 14 by the dispenser 17 in a state where the filler filling frame 16 made of resin or the like is installed. By doing so, it is possible to prevent the filler from flowing out from the dicing grooves 14 formed at the end of the semiconductor wafer 11.

  In the present embodiment, the filler 17 is supplied to the dicing grooves 14 while moving the dispenser 17 linearly in the vertical direction or the horizontal direction toward the paper surface of FIG. At this time, in a portion where the dicing groove 14 formed extending in the vertical direction toward the paper surface of FIG. 4B and the dicing groove 14 formed extending in the left-right direction intersect with each other, the supply amount is reduced and the dicing is performed. The amount of the filler filled in the groove 14 is adjusted so that the filler does not protrude from the one surface 11 a of the semiconductor wafer 11.

  A filling layer 15 having sufficient strength against the pressing force by the polishing grindstone 25 when polishing the other surface 11b of the semiconductor wafer 11 in the step shown in FIG. 7 to be described later can be formed on the filler. Any material may be used as long as it is a material, but a resin is preferably used. By using a resin as the filler, the filler can be easily filled up to the bottom of the dicing groove 14, and the filler layer 15 can be easily removed with a stripping solution in the process shown in FIG. .

  Examples of the resin used for the filler include epoxy resin and urethane resin. Among these resins, a photocurable resin such as a resist is preferably used. Here, the photo-curing resin includes both a resin that is cured by light irradiation and a resin that is cured by a crosslinking reaction with a crosslinking agent by light irradiation. When a photocurable resin is used as the filler, the filling layer 15 is formed by filling the dicing groove 14 with the photocurable resin and then curing it. Therefore, since the hard filling layer 15 can be formed by using a photocurable resin as the filler, a grinding wheel for polishing the other surface 11b of the semiconductor wafer 11 in the process shown in FIG. 7 to be described later. It is possible to sufficiently ensure the strength of the packed bed 15 against the pressing force of 25.

  The ratio R (D1 / D2) between the thickness D1 of the filling layer 15 formed by filling the dicing grooves 14 with the filler and the depth D2 of the dicing grooves 14 is 0.8 or more and 1.0 or less. Is preferred. Here, the ratio R (D1 / D2) is a straight line that is substantially perpendicular to the virtual plane α including one surface 11a of the semiconductor wafer 11, and is the surface 15a on which the filling layer 15 is exposed and the bottom surface 14a of the dicing groove 14. On the imaginary straight line L that intersects the imaginary straight line L, the distance from the intersection A between the imaginary straight line L and the exposed surface 15a of the filling layer 15 to the intersection B between the imaginary straight line L and the bottom surface 14a of the dicing groove 14 The thickness D1 is a value when the distance from the intersection C between the virtual straight line L and the virtual plane α to the intersection B between the virtual straight line L and the bottom surface 14a of the dicing groove 14 is the depth D2 of the dicing groove 14. is there. That is, the ratio R is a ratio between D1 and D2 on the same virtual straight line L and changes depending on the position of the virtual straight line L.

  By setting the ratio R to 0.8 or more, generation of voids in the packed layer 15 is suppressed, and a grinding wheel for polishing the other surface 11b of the semiconductor wafer 11 in the step shown in FIG. 7 to be described later. It is possible to sufficiently ensure the strength of the packed bed 15 against the pressing force of 25. Further, by forming the filling layer 15 so that the ratio R is 1.0 or less, that is, the surplus filling material other than filling the dicing grooves 14 does not protrude from the one surface 11a of the semiconductor wafer 11. The integrated circuit composed of the plurality of circuit elements and the protruding electrodes 12 provided on the one surface 11a of the semiconductor wafer 11 can be prevented from being contaminated with the filler.

  When a photocurable resin such as a resist is used as the filler, the ratio R is 0.8 or more and 1. in the filled layer 15 after the photocurable resin filled in the dicing grooves 14 is cured. It is preferably 0 or less.

  FIG. 5 is a cross-sectional view showing a state where the protective member 18 is provided on one surface 11 a of the semiconductor wafer 11. A protective member 18 is provided on one surface 11a of the semiconductor wafer 11 on which the filling layer 15 is formed so as to cover an integrated circuit composed of a plurality of circuit elements and protruding electrodes 12. At this time, the filling layer 15 is also covered with the protective member 18. Thus, by providing the protective member 18 on the one surface 11 a of the semiconductor wafer 11, the unevenness due to the protruding electrodes 12 formed on the one surface 11 a of the semiconductor wafer 11 is covered with the protective member 18, and one of the semiconductor wafers 11 is covered. The surface 11a side can be made flat.

  As the protective member 18, any material may be used as long as it has a structure capable of covering the unevenness of the one surface 11 a of the semiconductor wafer 11 formed by the protruding electrodes 12. For the protective member 18, a protective tape formed by applying an adhesive to one surface of the base material is preferably used because of easy handling. As a base material of the protective tape, an organic substance, for example, a resin such as polyester or polyimide is used. As the adhesive applied to the substrate, for example, an acrylic resin is used. In the present embodiment, the protruding electrode 12 is formed having a height H of 20 μm from the one surface 11a of the semiconductor wafer 11 as described above. The thickness is 100 to 300 μm, and the pressure-sensitive adhesive layer formed by applying the pressure-sensitive adhesive to one surface of the base material has a thickness of 30 to 60 μm. When a protective tape is used as the protective member 18, the protective member 18 can be provided on one surface 11a of the semiconductor wafer 11 as follows.

  FIG. 6 is a diagram illustrating a state where the protective tape 18 a is attached to one surface 11 a of the semiconductor wafer 11. The other surface 11 b of the semiconductor wafer 11, that is, the surface 11 b opposite to the surface 11 a on which the protruding electrodes 12 are formed, is fixed to the pasting table 19. In this state, the protective tape 18a is supplied to one surface 11a of the semiconductor wafer 11 so that the integrated circuit including the plurality of circuit elements and the protruding electrodes 12 is covered with the protective tape 18a. The protective tape 18 a is supplied so that the pressure-sensitive adhesive layer is in contact with one surface 11 a of the semiconductor wafer 11. While the sticking roller 20 is pressed against the surface of the protective tape 18 a opposite to the surface facing the semiconductor wafer 11, one side of the semiconductor wafer 11 is rotated around the axis 21 in the counterclockwise direction indicated by the arrow 22. Is moved in a direction indicated by an arrow 23 parallel to the surface 11a. The protective tape 18 a is stuck to one surface 11 a of the semiconductor wafer 11 by the pressing force of the sticking roller 20.

  FIG. 7A is a cross-sectional view showing a state where the other surface 11 b of the semiconductor wafer 11 is polished. FIG. 7B is a diagram illustrating a state in which the other surface 11 b of the semiconductor wafer 11 is polished by the polishing grindstone 25.

  The other surface 11 b of the semiconductor wafer 11, that is, the surface 11 b opposite to the surface 11 a provided with the protection member 18 is polished until at least the filling layer 15 that is a filling material filled in the dicing grooves 14 is exposed. As a result, the semiconductor wafer 11 is cut for each portion 30 to be the semiconductor element 1. The portion 30 of the semiconductor wafer 11 which becomes the semiconductor element 1 is in a state of being bonded by the filling layer 15 as shown in FIG. 7A, and the semiconductor wafer 11 is filled in the step shown in FIG. 15 is removed and separated.

  For polishing the other surface 11b of the semiconductor wafer 11, a method of grinding using a polishing grindstone 25 is preferably used. When the other surface 11b of the semiconductor wafer 11 is polished using the polishing grindstone 25, as shown in FIG. 7B, the one surface 11a provided with the protective member 18 of the semiconductor wafer 11 is used for polishing. The semiconductor wafer 11 is fixed to the polishing chuck table 24 through the protective member 18 so as to face the chuck table 24. In this state, while rotating the grinding wheel 25 around the axis 27 of the grinding wheel shaft 26 in the direction of the arrow 28, the grinding wheel 25 is lowered downward toward the paper surface of FIG. The other surface 11b of the semiconductor wafer 11 is polished by pressing against 11b. That is, a load is applied to the semiconductor wafer 11 by the polishing grindstone 25 to polish the other surface 11 b of the semiconductor wafer 11. By adjusting the position of the polishing grindstone 25 in the direction of the axis 27, the polishing amount of the other surface 11b of the semiconductor wafer 11 by the grindstone 25 can be controlled, and the semiconductor wafer 11 can be made to have a desired thickness.

  In the present embodiment, when the other surface 11b of the semiconductor wafer 11 is polished in the step shown in FIG. 7, the dicing groove 14 is filled with a filler, and the filling layer 15 is formed. Accordingly, the pressing force applied to the portion 29 where the dicing groove 14 of the semiconductor wafer 11 is formed from the polishing grindstone 25 and the portion 30 defined by the dicing groove 14 of the semiconductor wafer 11 from the polishing grindstone 25 are loaded. The difference from the pressing force is small. In addition, each portion 30 defined by the dicing groove 14 of the semiconductor wafer 11 is applied to the dicing groove even when a force acts in a direction parallel to the surface 25 a of the polishing grindstone 25 facing the semiconductor wafer 11. 14 is not inclined to the inner side.

  In particular, in the process shown in FIG. 4, the filling layer 15 is formed so that the ratio R (D1 / D2) between the thickness D1 of the filling layer 15 and the depth D2 of the dicing groove 14 is 0.8 or more. Thus, it is possible to sufficiently ensure the strength of the filling layer 15 against the pressing force by the polishing grindstone 25 when the other surface 11b of the semiconductor wafer 11 is polished, so that the dicing groove 14 of the semiconductor wafer 11 from the polishing grindstone 25 can be secured. It is possible to make the pressing force applied to the portion 29 formed with the same as the pressing force applied to the portion 30 defined by the dicing groove 14 of the semiconductor wafer 11 from the polishing grindstone 25. Further, when a force acts in a direction parallel to the surface 25 a of the polishing grindstone 25 facing the semiconductor wafer 11, each portion 30 defined by the dicing groove 14 of the semiconductor wafer 11 is inside the dicing groove 14. It can be surely prevented from tilting to the side.

  Further, as described above, the filling layer 15 is formed of a photocurable resin, thereby forming a hard filling layer 15 and filling the pressing force by the polishing grindstone 25 when the other surface 11b of the semiconductor wafer 11 is polished. The strength of the layer 15 can be sufficiently secured. Thus, as in the case where the filling layer 15 is formed so that the ratio R (D1 / D2) is 0.8 or more, the portion 29 where the dicing grooves 14 of the semiconductor wafer 11 are formed from the polishing grindstone 25. And the pressing force applied to the portion 30 defined by the dicing groove 14 of the semiconductor wafer 11 from the polishing grindstone 25 can be made substantially equal. Further, when a force acts in a direction parallel to the surface 25 a of the polishing grindstone 25 facing the semiconductor wafer 11, each portion 30 defined by the dicing groove 14 of the semiconductor wafer 11 is inside the dicing groove 14. It can be surely prevented from tilting to the side.

  Therefore, in the present embodiment, the occurrence of waviness on the other surface 11b of the semiconductor wafer 11 due to polishing can be prevented, so that the flatness of the other surface 11b of the semiconductor wafer 11 after polishing can be ensured. .

  FIG. 8 is a cross-sectional view showing a state where the filling layer 15 is removed. The exposed filling layer 15 is removed from the dicing grooves 14, and the semiconductor wafer 11 is separated into pieces for each portion 30 defined by the dicing grooves 14. When removing the filling layer 15, the protective member 18 is provided on the one surface 11 a of the semiconductor wafer 11, so that the semiconductor wafer 11 is separated into pieces in a state of being connected via the protective member 18. Therefore, in the step shown in FIG. 9 to be described later, the individual semiconductor wafer 11 can be etched simultaneously, so that the production efficiency can be improved.

  When the filling layer 15 is formed of a resin, it can be easily removed with a stripping solution as described above. As the remover, OMR (trade name; manufactured by Tokyo Ohka Kogyo Co., Ltd.) or the like is used. In the present embodiment, since one surface 11a of the semiconductor wafer 11 is covered with the protective member 18, when the filling layer 15 is removed with the stripping solution, the stripping solution contacts the one surface 11a of the semiconductor wafer 11. Never do. Therefore, the filling layer 15 can be removed without contaminating the circuit elements and the protruding electrodes 12 provided on the one surface 11a of the semiconductor wafer 11 with the stripping solution.

  FIG. 9 is a cross-sectional view showing a state in which the polished surface 41 of the semiconductor wafer 11 and the surface 42 exposed by removing the filling layer 15 are etched. The polished surface 41 of the semiconductor wafer 11, that is, the surface 41 exposed by polishing the other surface 11b in the step shown in FIG. 7 and the surface 42 exposed by removing the filling layer 15 in the step shown in FIG. 8 are etched. Thereby, the semiconductor element 1 is obtained.

  FIG. 10 is a diagram showing a comparison between the semiconductor wafer 11 before etching and the semiconductor wafer 11 after etching. 10A corresponds to a state where the filling layer 15 shown in FIG. 8 is removed, and FIG. 10B is exposed by removing the polishing surface 41 and the filling layer 15 of the semiconductor wafer 11 shown in FIG. This corresponds to a state where the surface 42 is etched.

  As shown in FIG. 10A, in the semiconductor wafer 11 before etching, the crushed layer 31 is present on the polishing surface 41 of the semiconductor wafer 11 and the crushed layer 32 is present on the surface 42 exposed by removing the filling layer 15. To do. The crushing layer 31 present on the polishing surface 41 of the semiconductor wafer 11 is formed at the time of polishing in the process shown in FIG. The crushing layer 32 present on the surface 42 exposed by the removal of the filling layer 15 is formed on the surface of the semiconductor wafer 11 facing the dicing groove 14 when the dicing groove 14 is formed in the process shown in FIG. It is.

  The semiconductor wafer 11 having the crushed layers 31 and 32 shown in FIG. 10A is etched in the above-described step shown in FIG. 9 so that the semiconductor is polished during polishing as shown in FIG. When the crushing layer 31 and the dicing groove 14 formed on the polishing surface 41 of the wafer 11 are formed, the crushing layer 32 formed on the surface facing the dicing groove 14 of the semiconductor wafer 11 and exposed by removing the filling layer 15 is removed. be able to. Therefore, since the crushing layer which causes damage can be reduced, the semiconductor element 1 having a high bending strength can be manufactured.

  In FIG. 10B, the amount of the semiconductor wafer 11 to be etched in the etching step shown in FIG. 9, that is, the etching amount is the same as that of the crushed layer 31 present on the polishing surface 41 of the semiconductor wafer 11 shown in FIG. It shows a case where both the crushing layer 31 and the crushing layer 32 are removed, which is larger than both the thickness s1 and the thickness s2 of the crushing layer 32 existing on the surface 42 exposed by the removal of the filling layer 15. If the etching amount is smaller than the thickness s1 of the crushed layer 31, a part of the crushed layer 31 is not removed. If the etching amount is smaller than the thickness s2 of the crush layer 32, a part of the crush layer 32 is not removed. Therefore, in order to improve the bending strength of the semiconductor element 1, the etching amount in the etching process shown in FIG. 9 is larger than at least one of the thickness s1 of the crushing layer 31 and the thickness s2 of the crushing layer 32. It is preferable that the thickness s1 of the crushed layer 31 and the thickness s2 of the crushed layer 32 are larger than each other.

  The thickness s1 of the crushing layer 31 formed on the polishing surface 41 of the semiconductor wafer 11 is about 1 μm when the count of the polishing grindstone 25 used in the polishing step shown in FIG. Also, the thickness s2 of the crushing layer 32 formed on the surface facing the dicing grooves 14 of the semiconductor wafer 11 in the dicing step shown in FIG. 2 and exposed by removing the filling layer 15 in the step shown in FIG. 8 is about 30 μm. Therefore, the etching amount in the etching process shown in FIG. 9 is preferably 1 μm or more and 10 μm or less from the polished surface 41 of the semiconductor wafer 11 and the surface 42 exposed by removing the filling layer 15, respectively, and is 30 μm or more and 50 μm or less. Is more preferable.

  The etching amount is 1 μm or more and 10 μm or less, and polishing is performed by removing a portion of 1 μm or more and 10 μm or less from the polishing surface 41 of the semiconductor wafer 11 and a portion of 1 μm or more and 10 μm or less from the surface 42 exposed by removing the filling layer 15 by etching. At this time, the crushed layer 31 formed on the polishing surface 41 of the semiconductor wafer 11 is reliably removed, and the dicing groove 14 is formed on the surface facing the dicing groove 14 when forming the dicing groove 14. The crushing layer 32 exposed by the removal can be reduced. Therefore, the semiconductor element 1 with higher bending strength can be manufactured.

  Further, the etching amount is 30 μm or more and 50 μm or less, and the portion of 30 μm or more and 50 μm or less from the polished surface 41 of the semiconductor wafer 11 and the portion exposed by removing the filling layer 15 are removed by etching from 30 μm or more and 50 μm or less. As shown in FIG. 10B, both the crushing layer 31 on the polishing surface 41 of the semiconductor wafer 11 and the crushing layer 32 on the surface 42 exposed by the removal of the filling layer 15 can be reliably removed. Therefore, the semiconductor element 1 having a particularly high bending strength can be manufactured.

  Etching of the polished surface 41 of the semiconductor wafer 11 and the surface 42 exposed by removing the filling layer 15 may be performed by either dry etching or wet etching, and is preferably performed by chemical etching using an etching solution. As the etchant, hydrofluoric acid (HF) or the like is used. The polished surface 41 of the semiconductor wafer 11 and the surface 42 exposed by removing the filling layer 15 are chemically etched with an etching solution, thereby rounding the corners of the separated semiconductor wafer 11 to have a curvature. Since the corner R can be formed, the bending strength of the semiconductor element 1 can be improved.

  In the present embodiment, since the protective member 18 is provided on the one surface 11a of the semiconductor wafer 11, the etchant comes into contact with the one surface 11a of the semiconductor wafer 11 during chemical etching using the etchant. There is nothing. Therefore, the circuit elements and the protruding electrodes 12 provided on the one surface 11a of the semiconductor wafer 11 are not chemically contaminated with the etching liquid, and the surface 42 exposed by removing the polishing surface 41 and the filling layer 15 of the semiconductor wafer 11 is chemically treated. Etching can be performed.

  FIG. 11 is a cross-sectional view showing a state where the dicing tape 33 is attached. A dicing tape 33, which is an adhesive tape, is attached to the other surface 11b of the semiconductor wafer 11 constituting the semiconductor element 1, that is, the surface 11b opposite to the surface 11a on which the protective member 18 is provided. As a result, the semiconductor element 1 is connected to both the protective member 18 and the dicing tape 33.

  As the dicing tape 33, a tape-like tape formed by applying an adhesive on one surface of a substrate is suitably used. As the base material of the dicing tape 33, for example, a resin such as polyester or polyolefin is used. As the adhesive applied to the substrate, for example, an acrylic resin is used. In the present embodiment, as the dicing tape 33, for example, the thickness of the base material is 100 to 200 μm, and the thickness of the adhesive layer formed by applying the adhesive to one surface of the base material is 20 to 50 μm. Some are used.

  FIG. 12 is a cross-sectional view showing a state where the protective member 18 is removed. The protective member 18 provided on the one surface 11a of the semiconductor wafer 11 constituting the semiconductor element 1 is removed. When the protective tape 18a shown in FIG. 6 is used as the protective member 18, the protective tape 18a can be peeled off with a peeling tape. By removing the protective member 18, the semiconductor element 1 is in a connected state via the dicing tape 33 attached to the other surface 11 b of the semiconductor wafer 11. The semiconductor element 1 is held in this state, individually removed from the dicing tape 33 as necessary, and connected to the wiring board of the semiconductor device or the wiring board of the package.

  As described above, in the method of manufacturing the semiconductor element 1 according to the present embodiment, when the other surface 11b of the semiconductor wafer 11 is polished by applying a load with the polishing grindstone 25 in the polishing step shown in FIG. The groove 14 is filled with a filler, and a filling layer 15 is formed. Thus, as described above, the occurrence of waviness on the other surface 11b of the semiconductor wafer 11 due to polishing can be prevented, and the flatness of the other surface 11b of the semiconductor wafer 11 after polishing can be ensured.

  That is, in the semiconductor element 1 according to the present embodiment shown in FIG. 9, the surface 11b opposite to the surface 11a on which the circuit element and the protruding electrode 12 are formed, which is the other surface 11b of the semiconductor wafer 11, has high flatness. Have. Thus, when the semiconductor element 1 is connected to the wiring board of the semiconductor device or the wiring board of the package by the flip chip connection method, the entire other surface 11b of the semiconductor wafer 11 constituting the semiconductor element 1 is brought into contact with the bonding tool. Since it can be fixed parallel to the bonding tool, one surface 11a of the semiconductor wafer 11, which is the surface on which the protruding electrodes 12 of the semiconductor element 1 are formed, is made to face the surface of the wiring board facing the semiconductor element 1 Can be opposed in parallel. Therefore, the protruding electrode 12 provided on the semiconductor element 1 and the wiring electrode provided on the wiring board can be connected well.

  Further, in the method for manufacturing the semiconductor element 1 of the present embodiment, after the dicing groove 14 is formed in the step shown in FIG. 2, the other surface 11b of the semiconductor wafer 11 is polished in the step shown in FIG. make it thin. As a result, the process of handling the thinned semiconductor wafer 11 can be reduced, and the damage of the semiconductor wafer 11 during the manufacturing process can be suppressed, so that the thin semiconductor element 1 can be manufactured with a high yield. Therefore, it is possible to obtain the semiconductor element 1 that is thin and has high flatness in the other surface 11b of the semiconductor wafer 11, that is, the surface 11b opposite to the surface 11a on which the circuit elements and the protruding electrodes 12 are formed.

  In the present embodiment, as described above, since the protective member 18 is provided on the one surface 11a of the semiconductor wafer 11, the unevenness caused by the protruding electrodes 12 formed on the one surface 11a of the semiconductor wafer 11 is reduced. Covered with the protective member 18, the one surface 11 a side of the semiconductor wafer 11 is flat. As a result, as shown in FIG. 7B, the other surface 11b of the semiconductor wafer 11 is mounted with the semiconductor wafer 11 placed so that one surface 11a faces the polishing chuck table 24, which is a support substrate. When polishing the surface, the drag force from the polishing chuck table 24 can be uniformly applied to the entire surface 11a side of the semiconductor wafer 11. In this way, the pressing force applied from the polishing grindstone 25 to the other surface 11b of the semiconductor wafer 11 can be made constant regardless of the portion with the protruding electrode 12 and the portion without the protruding electrode 12. It is possible to prevent the uneven shape due to the protruding electrodes 12 formed on the one surface 11 a of the semiconductor wafer 11 from being transferred to the other surface 11 b of the semiconductor wafer 11. Therefore, compared to the case where the protective member 18 is not provided on one surface 11a of the semiconductor wafer 11, the other surface 11b of the semiconductor wafer 11, that is, the surface 11b opposite to the surface 11a on which the circuit elements and the protruding electrodes 12 are formed. However, the semiconductor element 1 having higher flatness can be manufactured.

  As described above, in the present embodiment, the semiconductor element 1 has one integrated circuit composed of a plurality of circuit elements, but is not limited thereto, and is composed of a plurality of circuit elements. A plurality of integrated circuits may be provided. Further, the semiconductor element 1 may have only one circuit element, or may have a plurality of circuit elements that are not connected to each other by electric wiring.

  A substrate singulation method according to another embodiment of the present invention is a method of dividing various substrates such as a semiconductor substrate made of a semiconductor material or an insulating substrate made of an insulating material such as a resin into predetermined regions. FIG. 7 illustrates a method of singulation, and a step of forming the dicing groove 14 illustrated in FIG. 2, a step of forming the filling layer 15 illustrated in FIG. 4, and a method of manufacturing the semiconductor device 1 of the first embodiment. 8 includes at least a step of polishing the other surface 11b of the semiconductor wafer 11 until at least the filling layer 15 is exposed, and a step of removing the filling layer 15 shown in FIG.

  In other words, in the method for separating a substrate according to another embodiment of the present invention, the depth from one surface of the substrate is set so as to define a predetermined region in the same manner as in the step shown in FIG. A dicing groove reaching the inside is formed. As in the first embodiment, the dicing groove may be formed after the scribe line is formed so as to define a predetermined region in the same manner as in the step shown in FIG.

  The formed dicing groove is filled with a filler in the same manner as in the step shown in FIG. 4, and after forming the filling layer, the other surface of the substrate is at least formed into the dicing groove in the same manner as in the step shown in FIG. Polishing is performed until the filled material, that is, the filled layer is exposed. Similarly to the first embodiment, the other surface of the substrate is preferably polished after providing a protective member on one surface of the substrate in the same manner as in the step shown in FIG.

  The exposed filling layer is removed from the dicing groove 14 in the same manner as in the step shown in FIG. Thereby, the substrate is separated into pieces for each predetermined region.

  In the substrate singulation method of this embodiment, the dicing groove is filled with a filler when the other surface of the substrate is polished, as in the method of manufacturing the semiconductor element 1 of the first embodiment. A layer is formed. Accordingly, when the other surface of the substrate is polished by applying a load to the substrate with the polishing grindstone as in the step shown in FIG. 7, the pressing force applied from the grindstone to the portion where the dicing groove is formed on the substrate. And the pressing force applied to the portion defined by the dicing groove of the substrate from the grindstone is small. Further, each portion defined by the dicing groove of the substrate does not tilt toward the inner side of the dicing groove even when a force acts in a direction parallel to the surface of the grindstone used for polishing facing the substrate of the grindstone. Accordingly, the occurrence of waviness on the other surface of the substrate due to polishing can be prevented, and the flatness of the other surface of the singulated substrate can be ensured.

FIG. 1A is a cross-sectional view showing a state in which the protruding electrode 12 and the scribe line 13 are formed on one surface 11 a of the semiconductor wafer 11. FIG. 1B is a plan view showing the semiconductor wafer 11 on which the protruding electrodes 12 and the scribe lines 13 shown in FIG. 1A are formed as viewed from the one surface 11a side. FIG. 2A is a cross-sectional view showing a state where the dicing grooves 14 are formed. FIG. 2B is a plan view showing the semiconductor wafer 11 in which the dicing grooves 14 shown in FIG. 2A are formed as viewed from the one surface 11a side. It is sectional drawing which shows the other shape of the dicing groove | channel 14 typically. FIG. 4A is a cross-sectional view showing a state in which the filling layer 15 is formed. FIG. 4B is a diagram illustrating a state where the dicing groove 14 is filled with a filler. 2 is a cross-sectional view showing a state where a protective member 18 is provided on one surface 11a of a semiconductor wafer 11. FIG. It is a figure which shows a mode that the protective tape 18a is affixed on the one surface 11a of the semiconductor wafer 11. FIG. FIG. 7A is a cross-sectional view showing a state where the other surface 11 b of the semiconductor wafer 11 is polished. FIG. 7B is a diagram illustrating a state in which the other surface 11 b of the semiconductor wafer 11 is polished by the polishing grindstone 25. It is sectional drawing which shows the state which removed the filling layer. 4 is a cross-sectional view showing a state in which a polished surface 41 of a semiconductor wafer 11 and a surface 42 exposed by removing a filling layer 15 are etched. FIG. FIG. 2 is a diagram showing a comparison between a semiconductor wafer 11 before etching and a semiconductor wafer 11 after etching. It is sectional drawing which shows the state which affixed the dicing tape 33. FIG. It is sectional drawing which shows the state which removed the protection member. FIG. 3 is a view showing a state in which a protruding electrode 52 is formed on one surface 51a of a semiconductor wafer 51. It is a figure which shows the state in which the dicing groove | channel 53 was formed. It is a figure which shows the state which provided the protection member. It is a figure which shows a mode that the other surface 51b of the semiconductor wafer 51 is grind | polished. It is sectional drawing which shows typically a mode that the semiconductor element 50 and the wiring board 60 are connected by the flip-chip connection method.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor element 11 Semiconductor wafer 11a One surface 11b of the semiconductor wafer 11 The other surface of the semiconductor wafer 11 12 Protruding electrode 13 Scribe line 14 Dicing groove 15 Filling layer 18 Protection member 24 Polishing chuck table 25 Polishing grindstone 26 Grinding wheel axis

Claims (10)

Forming a plurality of circuit elements on one surface of the semiconductor substrate;
Forming a dicing groove whose depth reaches the inside of the semiconductor substrate from one surface of the semiconductor substrate so as to define a predetermined region that includes at least one circuit element; ,
Filling the dicing grooves with a filler;
Polishing the other surface of the semiconductor substrate until at least the filler filled in the dicing grooves is exposed;
Removing the filler filled in the dicing grooves and separating the semiconductor substrate into individual pieces. After the step of filling the dicing groove with a filler, and before polishing the other surface of the semiconductor substrate until at least the filler filled in the dicing groove is exposed,
2. The method of manufacturing a semiconductor element according to claim 1, further comprising a step of providing a protective member on one surface of the semiconductor substrate so as to cover the circuit element. After the step of removing the filler filled in the dicing grooves and dividing the semiconductor substrate into pieces,
3. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of etching at least one of a surface exposed by the polishing of the semiconductor substrate and a surface exposed by removing the filler. Method. In the step of etching at least one of the surface exposed by the polishing of the semiconductor substrate and the surface exposed by removing the filler,
4. The method of manufacturing a semiconductor device according to claim 3, wherein portions of 1 μm or more and 10 μm or less are removed by etching from the surface exposed by the polishing of the semiconductor substrate and the surface exposed by removal of the filler. 5. In the step of etching at least one of the surface exposed by the polishing of the semiconductor substrate and the surface exposed by removing the filler,
4. The method of manufacturing a semiconductor device according to claim 3, wherein portions of 30 [mu] m to 50 [mu] m are respectively removed from the surface exposed by the polishing of the semiconductor substrate and the surface exposed by removing the filler. In the step of etching at least one of the surface exposed by the polishing of the semiconductor substrate and the surface exposed by removing the filler,
6. The method of manufacturing a semiconductor device according to claim 3, wherein the etching is performed by chemical etching using an etching solution. In the step of filling the dicing groove with a filler,
The ratio R (D1 / D2) between the thickness D1 of the filling layer formed by filling the dicing grooves with the filler and the depth D2 of the dicing grooves is 0.8 or more and 1.0 or less. The method for manufacturing a semiconductor element according to claim 1, wherein:   The method for manufacturing a semiconductor element according to claim 1, wherein the filler is a resin.   9. The method of manufacturing a semiconductor element according to claim 8, wherein the resin is a photocurable resin, and is cured after being filled in the dicing groove. A method for dividing a substrate into pieces for each predetermined region,
Forming a dicing groove whose depth reaches the inside of the substrate from one surface of the substrate so as to define a predetermined region;
Filling the dicing grooves with a filler;
Polishing the other surface of the substrate until at least the filler filled in the dicing grooves is exposed;
And a step of removing the filling material filled in the dicing grooves.

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