JP2008227068A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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JP2008227068A
JP2008227068A JP2007061836A JP2007061836A JP2008227068A JP 2008227068 A JP2008227068 A JP 2008227068A JP 2007061836 A JP2007061836 A JP 2007061836A JP 2007061836 A JP2007061836 A JP 2007061836A JP 2008227068 A JP2008227068 A JP 2008227068A
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adhesive film
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semiconductor
substrate
semiconductor chip
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Yuichi Shigemaru
雄一 重丸
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Toshiba Corp
株式会社東芝
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device made by stacking a plurality of semiconductor chips via adhesive films while preventing the adhesive films from protruding out of the semiconductor chips, and also to provide its manufacturing method. <P>SOLUTION: The semiconductor device comprises a plurality of semiconductor chips 13, 15 and 17 stacked on a substrate 11 via the adhesive films 12, 14 and 16; a plurality of connecting conductors 22, 23, 24 for electrically connecting bonding pads 18, 19 and 20 formed on the semiconductor chips 13, 15 and 17 to a plurality of bonding pads 21 formed on the substrate 11; and a resin 27 for molding the plurality of semiconductor chips 13, 15 and 17 and the plurality of connecting conductors 22, 23 and 24. The adhesive films 12, 14 and 16 are smaller in size than the semiconductor chips 13, 15 and 17 placed on the adhesive films 12, 14 and 16. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、半導体装置およびその製造方法に関する。 The present invention relates to a semiconductor device and a manufacturing method thereof.

近年、集積回路の高密度化、大容量化に伴い複数の半導体チップを1つのパッケージに収納した、所謂MCP(Multi Chip Package)と呼ばれる半導体装置が広く使用されている。 Recently, a high density of integrated circuits, accommodating a plurality of semiconductor chips in one package increase in capacity, a semiconductor device has been widely used so-called MCP (Multi Chip Package).

従来、複数の半導体チップを縦方向に積み重ねたMCPタイプの半導体装置では、集積回路が形成された半導体ウェーハの裏面に接着フィルムを貼り付け、接着フィルムを貼り付けたまま半導体ウェーハをダイシングして得た半導体チップを基板上に積層し、半導体チップのボンディングパッドと基板のボンディングパッドとをワイヤボンディングしていた。 Conventionally, in the semiconductor device of the MCP type stacked a plurality of semiconductor chips in the longitudinal direction, stuck to the adhesive film on the back surface of the semiconductor wafer on which an integrated circuit is formed, by dicing the semiconductor wafer while stuck adhesive film obtained the semiconductor chips are stacked on a substrate, the bonding pads of the bonding pad and the substrate of the semiconductor chip were wire-bonded.

然しながら、接着フィルムを貼り付けたまま半導体ウェーハをダイシングする場合、接着フィルムにクラックや剥がれが生じる、接着フィルムに切削粉が固着するなどの問題がある。 However, when dicing the semiconductor wafer while pasting adhesive film, cracks or peeling occurs in the adhesive film, cutting powder adhesive film has a problem such as sticking.

半導体チップの側面に接着フィルムの切れ端が残留していると、上段の半導体チップの接着フィルムの切れ端が、下段の半導体チップのワイヤボンディングの作業領域にはみ出す恐れがある。 When a piece of adhesive film on the side surface of the semiconductor chip is left, piece of adhesive film of the upper semiconductor chip, which may protrude into the work area of ​​the wire bonding of the lower semiconductor chip.
ワイヤボンディングの作業領域にはみ出した接着フィルムの切れ端は、ボンディングパッドと接触するなどして、ワイヤボンディング作業を妨げるので、ボンディング不良が発生する問題がある。 Piece of adhesive film which protrudes into the work area of ​​the wire bonding, such as by contact with the bonding pad, so interfering with the wire bonding operation, there is a problem of bonding failure.

予め、上段の半導体チップの接着フィルムの切れ端が、下段の半導体チップのワイヤボンディング部と接触しない距離だけ離間しておけば、ボンディング不良を未然に防止することができるが、上段に積層される半導体チップのサイズが小さくなるという問題がある。 Previously, the semiconductor piece of the adhesive film of the upper semiconductor chip, if separated by a distance that is not in contact with the wire bonding portion of the lower semiconductor chip, can be prevented defective bonding in advance, to be laminated on the upper there is a problem that the size of the chip becomes smaller.

これに対して、半導体チップから接着フィルムがはみ出さないようにマウントできる半導体装置の製造方法が知られている(例えば、特許文献1参照。)。 In contrast, the method of manufacturing a semiconductor device that can be mounted so does not protrude adhesive film from the semiconductor chip is known (for example, see Patent Document 1.).

特許文献1に開示された半導体装置の製造方法は、支持フィルム上に設けられた接着フィルムに対して、接着フィルム側から支持フィルムの表面または途中の深さまでの切り込みを入れ、接着フィルムを所定サイズに切断する。 The method of manufacturing a semiconductor device disclosed in Patent Document 1, with respect to the adhesive film provided on the support film, cut put from the adhesive film side to the surface or during the depth of the support film, the adhesive film a predetermined size cut into.

次に、支持フィルムを引き延ばして、切断された個々の接着フィルムに分離し、切断された個々の接着フィルムに半導体チップを貼り合わせ、半導体チップを接着フィルムにより基板上にマウントしている。 Next, stretching the support film is separated into individual adhesive film is cut, the individual adhesive film is cut bonded to the semiconductor chip, it is mounted on the substrate by the adhesive film semiconductor chip.

然しながら、特許文献1に開示された半導体装置の製造方法は、半導体チップと接着フィルムを別々に個片化して貼り合わせているので、工程が複雑であり、位置合わせが難しいという問題がある。 However, a method of manufacturing a semiconductor device disclosed in Patent Document 1, since the bonding by separately singulated adhesive film and the semiconductor chip, the process is complicated, it is difficult alignment.
特開2005−116545号公報 JP 2005-116545 JP

本発明は、半導体チップから接着フィルムがはみ出さないようにして、複数の半導体チップを積層した半導体装置およびその製造方法を提供する。 The present invention, as the adhesive film does not protrude from the semiconductor chip, a semiconductor device and a manufacturing method thereof by laminating a plurality of semiconductor chips.

本発明の一態様の半導体装置は、基板上に、それぞれ接着フィルムを介して積層された複数の半導体チップと、前記複数の半導体チップにそれぞれ形成されたボンディングパッドを、前記基板に形成された複数のボンディングパッドに電気的に接続する複数の接続導体と、前記複数の半導体チップおよび前記複数の接続導体をモールドする樹脂と、を具備し、前記接着フィルムのサイズが、前記接着フィルムの上に載置されている前記半導体チップのサイズより小さいことを特徴としている。 Multiple one embodiment of a semiconductor device of the present invention, which on a substrate, a plurality of semiconductor chips stacked via respective adhesive films, the bonding pad formed respectively on the plurality of semiconductor chips, which is formed on the substrate a plurality of connecting conductors for electrically connecting the bonding pads of, anda resin for molding the plurality of semiconductor chips and said plurality of connecting conductors, the size of the adhesive film, placing on the adhesive film it is characterized in that less than the size of the semiconductor chip that is location.

また、本発明の一態様の半導体装置の製造方法は、半導体ウェーハのボンディングパッドが形成された第1の面と対向する第2の面に、接着フィルムを貼り付け、前記第2の面側からダイシングラインに沿って、前記接着フィルムを第1の切削幅で前記半導体ウェーハに至るまで切断する工程と、前記第1の面側から前記ダイシングラインに沿って、前記半導体ウェーハを前記第1の切削幅より小さい第2の切削幅で切断し、複数の半導体チップに分割する工程と、複数のボンディングパッドが形成された基板上に、それぞれ前記第2の面に貼り付けられた前記接着フィルムを介して前記複数の半導体チップを積層する工程と、前記複数の半導体チップにそれぞれ形成された前記ボンディングパッドを、前記基板に形成された前記ボンディン A method of manufacturing a semiconductor device of one embodiment of the present invention, the second surface facing the first surface where the bonding pads of the semiconductor wafer is formed, paste adhesive film from the side of the second surface along dicing lines, wherein the step of cutting the adhesive film until the semiconductor wafer at a first cutting width, along the dicing line from said first surface, cutting the semiconductor wafer the first cut with a width smaller than the second width of cut, through the step of dividing the plurality of semiconductor chips, the plurality of bonding pads formed on the substrate, the adhesive film which are respectively adhered to the second surface wherein the step of stacking a plurality of semiconductor chips, the bonding pads formed respectively on the plurality of semiconductor chips, which is formed on the substrate Te said Bondin パッドに接続導体を介して電気的に接続する工程と、前記複数の半導体チップおよび前記複数の接続導体を樹脂でモールドする工程と、を具備することを特徴としている。 A step of electrically connected via connection conductors to the pads, and the plurality of semiconductor chips and said plurality of connecting conductors and characterized by comprising a step of resin molding, a.

本発明によれば、半導体チップから接着フィルムがはみ出さないようにして、複数の半導体チップを積層した半導体装置およびその製造方法が得られる。 According to the present invention, as the adhesive film does not protrude from the semiconductor chip, a semiconductor device and a manufacturing method thereof by laminating a plurality of semiconductor chips are obtained.

以下、本発明の実施例について図面を参照しながら説明する。 It will be described below with reference to the accompanying drawings embodiments of the present invention.

本発明の実施例について、図1乃至図3を用いて説明する。 Examples of the present invention will be described with reference to FIGS. 図1は本発明の実施例に係る半導体装置を示す図で、図1(a)はその平面図、図1(b)は図1(a)のA−A線に沿って切断し、矢印方向に眺めた断面図、図2および図3は半導体装置の製造工程を順に示す断面図である。 Figure 1 is a diagram showing a semiconductor device according to an embodiment of the present invention, FIG. 1 (a) is a plan view thereof, FIG. 1 (b) taken along line A-A of FIG. 1 (a), arrows sectional view as viewed in direction, FIG. 2 and FIG. 3 is a sectional view showing a manufacturing step of the semiconductor device in the order.

本実施例は、基板上に3個の半導体チップが積層され、各半導体チップのボンディングパッドが、基板のボンディングパッドにそれぞれワイヤで接続されたMCPタイプの半導体装置である。 This embodiment is laminated three semiconductor chips on a substrate, the bonding pads of the semiconductor chip, a semiconductor device of the connected MCP type each wire to the bonding pad of the substrate.

図1に示すように、本実施例の半導体装置10は、半導体基板11上に接着フィルム12を介して載置された半導体チップ13と、半導体チップ13上に接着フィルム14を介して載置された半導体チップ15と、半導体チップ15上に接着フィルム16を介して載置された半導体チップ17とを具備している。 1, the semiconductor device 10 of this embodiment includes a semiconductor chip 13 placed through the adhesive film 12 on the semiconductor substrate 11 is placed over the adhesive film 14 on the semiconductor chip 13 and a semiconductor chip 15, and a semiconductor chip 17 placed through the adhesive film 16 on the semiconductor chip 15.

基板11は、例えばセラミックス基板である。 Substrate 11 is, for example, a ceramic substrate. 接着フィルムは、例えば厚さ20μmの熱硬化性のポリマー系フィルムである。 Adhesive film, for example, a thermosetting polymer based film having a thickness of 20 [mu] m. 各半導体チップ13、15、17は、例えばメモリ回路あるいはロジック回路である。 Each of the semiconductor chips 13, 15 and 17 is a memory circuit or a logic circuit, for example.

各半導体チップ13、15、17の端部には、例えばサイズが100μm□のボンディングパッド18、19、20がそれぞれ複数形成されている。 At the end of each of the semiconductor chips 13, 15, 17, for example, size is the bonding pads 18, 19 and 20 of the 100 [mu] m □ are a plurality form. 基板11の端部には、ボンディングパッド21が複数形成されている。 At the end of the substrate 11, the bonding pad 21 are formed.

半導体チップ13のボンディングパッド18は、ワイヤ22を介して基板11の複数のディングパッド21のうち、ボンディングパッド21aに接続されている。 Bonding pads 18 of the semiconductor chip 13, among the plurality of loading pads 21 of the substrate 11 through the wire 22 is connected to the bonding pad 21a.
半導体チップ15のボンディングパッド19は、ワイヤ23を介して基板11の複数のディングパッド21のうち、ボンディングパッド21bに接続されている。 Bonding pads 19 of the semiconductor chip 15, among the plurality of loading pads 21 of the substrate 11 through the wire 23 is connected to the bonding pad 21b.
半導体チップ17のボンディングパッド20は、ワイヤ24を介して基板11の複数のディングパッド21のうち、ボンディングパッド21cに接続されている。 Bonding pads 20 of the semiconductor chip 17, among the plurality of loading pads 21 of the substrate 11 through the wire 24 is connected to the bonding pad 21c.

基板11の裏面には、ビア25を介してボンディングパッド21に接続された端子26、例えばハンダバンプが複数形成されている。 The back surface of the substrate 11, terminal 26, for example, solder bumps are formed in plural connected to the bonding pad 21 through a via 25.
これにより、各半導体チップ13、15、17は、端子26を介して外部回路に電気的に接続される。 Thus, the semiconductor chips 13, 15, 17 is electrically connected to an external circuit via the terminal 26.

基板11上に接着フィルム12、14、16を介して積層された半導体チップ13、15、17およびワイヤ22、23、24は、樹脂27でモールドされ、パッケージ28に収納されている。 Semiconductor chips 13, 15, 17 and the wires 22, 23 and 24 are laminated with an adhesive film 12, 14, 16 on the substrate 11 is molded with resin 27, it is housed in a package 28.

接着フィルム12のサイズL1aは、接着フィルム12をダイシングしたときに接着フィルム12の切れ端が発生しても、半導体チップ13からはみ出さないように、半導体チップ13のサイズL1bより、2ΔL1=L1b−L1aだけ小さく設定されている。 Size L1a of the adhesive film 12 may be a piece of adhesive film 12 is generated when dicing the adhesive film 12, so as not to protrude from the semiconductor chip 13, than the size L1b of the semiconductor chip 13, 2ΔL1 = L1b-L1a It is set as small.
接着フィルム14のサイズL2aは、接着フィルム14をダイシングしたときに接着フィルム14の切れ端が発生しても、半導体チップ15からはみ出さないように、半導体チップ15のサイズL2bより、2ΔL2=L2b−L2aだけ小さく設定されている。 Size L2a of the adhesive film 14, even if a piece of adhesive film 14 is generated when dicing the adhesive film 14, so as not to protrude from the semiconductor chip 15, than the size L2b of the semiconductor chip 15, 2ΔL2 = L2b-L2a It is set as small.
接着フィルム16のサイズL3aは、接着フィルム16をダイシングしたときに接着フィルム16の切れ端が発生しても、半導体チップ17からはみ出さないように、半導体チップ17のサイズL3bより、2ΔL3=L3b−L3aだけ小さく設定されている。 Size L3a of the adhesive film 16, even if a piece of adhesive film 16 is generated when dicing the adhesive film 16, so as not to protrude from the semiconductor chip 17, than the size L3b of semiconductor chip 17, 2ΔL3 = L3b-L3a It is set as small.

2ΔL1、2ΔL2、2ΔL3は、接着フィルム12、14、16をダイシングしたときに生じる切れ端の長さが、例えば100乃至200μm程度なので、切れ端の長さのばらつきとマージンを見込んで、それぞれ0.2乃至1mm程度が適当である。 2ΔL1,2ΔL2,2ΔL3 the length of a piece produced when dicing the adhesive film 12, 14, 16, for example, since 100 to an approximately 200 [mu] m, in anticipation of variation and margin of the length of a piece, 0.2 to each it is appropriate about 1mm.

各接着フィルム12、14、16の側面は、各半導体チップ13、15、17側に向かってそれぞれ末広がり状に傾斜している。 Side of each adhesive film 12, 14, 16 are respectively inclined flared toward each semiconductor chip 13, 15, 17 side.
各接着フィルム12、14、16の側面の傾斜角度θは特に限定されないが、接着フィルムの切断の容易性から、例えば30度程度が適当である。 But not the inclination angle θ is particularly limited aspect of the adhesive film 12, 14, 16, the ease of cutting the adhesive film, for example, about 30 degrees is appropriate.

半導体チップ13は、半導体チップ13のエッジと基板11のボンディングパッド21のエッジと距離L1だけ離間して基板11上に載置されている。 The semiconductor chip 13 is mounted on the substrate 11 spaced apart by an edge and a distance L1 of the bonding pads 21 of the edge and the substrate 11 of the semiconductor chip 13.
半導体チップ19は、半導体チップ19のエッジと半導体チップ13のボンディングパッド18のエッジと距離L2だけ離間して半導体チップ13上に積層されている。 The semiconductor chip 19 is stacked on the semiconductor chip 13 are separated by the edge and a distance L2 of the bonding pad 18 of the edge of the semiconductor chip 13 of the semiconductor chip 19.
半導体チップ17は、半導体チップ17のエッジと半導体チップ15のボンディングパッド19のエッジと距離L3だけ離間して半導体チップ15上に積層されている。 The semiconductor chip 17 is stacked on the semiconductor chip 15 spaced apart by an edge and a distance L3 of the bonding pads 19 of the edge of the semiconductor chip 15 of the semiconductor chip 17.

距離L1、L2、L3は、ボンディング装置のボンディングヘッド(図示せず)の作業領域に応じて、その動作を妨げない距離、例えばそれぞれ140μm程度に等しく設定されている。 Distance L1, L2, L3, depending on the working area of ​​the bonding of the bonding apparatus head (not shown), a distance that does not interfere with its operation, for example, is set equal to about 140μm, respectively.

次に、半導体装置10の製造方法について説明する。 Next, a method for manufacturing the semiconductor device 10.
図2(a)に示すように、半導体ウェーハ30のボンディングパッド(図示せず)が形成されている第1の面30aに、例えば厚さが20μmのダイシングシート31を貼り付け、第1の面30aと対向する第2の面30bに接着フィルム32を貼り付ける。 As shown in FIG. 2 (a), the first surface 30a where the bonding pads of the semiconductor wafer 30 (not shown) is formed, is stuck a dicing sheet 31 of 20μm thickness, for example, the first surface paste adhesive film 32 on the second surface 30b to 30a facing.
半導体ウェーハ30とは、ダイシングにより各半導体チップ13、15、17が得られる半導体ウェーハを意味している。 The semiconductor wafer 30 means a semiconductor wafer, each semiconductor chip 13, 15, 17 is obtained by dicing.

次に、図2(b)に示すように、ブレード33を用いて、第2の面30b側からダイシングライン34に沿って、接着フィルム32を第1の切削幅W1で、半導体ウェーハ30の第2の面30bに至るまで切断する。 Next, as shown in FIG. 2 (b), using a blade 33, along the second surface 30b side to the dicing line 34, the adhesive film 32 in the first cutting width W1, the semiconductor wafer 30 cutting up to the second face 30b.
これにより、半導体チップ13、15、17に貼り付けられる接着フィルム12、14、16がそれぞれ形成される。 Thus, the adhesive film 12, 14, 16 affixed to the semiconductor chips 13, 15, 17 are respectively formed.

次に、図2(c)に示すように、半導体ウェーハ30の接着フィルム32上にダイシングシート35を貼り付け、半導体ウェーハ30を上下反転して、ダイシングシート31を半導体ウェーハ30から剥離する。 Next, as shown in FIG. 2 (c), paste the dicing sheet 35 on the adhesive film 32 of the semiconductor wafer 30, the semiconductor wafer 30 upside down, peeling the dicing sheet 31 from the semiconductor wafer 30.

次に、ブレード36を用い、第1の面30a側からダイシングライン34に沿って、半導体ウェーハ30を第1の切削幅W1より小さい第2の切削幅W2で切断する。 Then, using a blade 36, along the first surface 30a side to the dicing line 34, cutting the semiconductor wafer 30 in the first cutting width W1 smaller than the second cutting width W2.
これにより、半導体ウェーハ30から、側面が傾斜し、小さいサイズの接着フィルムが貼り付けられた複数の半導体チップ37が得られる。 Thus, the semiconductor wafer 30, the side surface is inclined, the plurality of semiconductor chips 37 adhesive film is adhered in small size is obtained.

第1の切削幅W1は、ブレード33の刃の厚さを、例えば2ΔL1−W2とすることにより定めることができる。 First cutting width W1 can be determined by the thickness of the blade of the blade 33, for example a 2ΔL1-W2.
第2の切削幅W2は特に限定されないが、材料節約の観点からできるだけ小さいほうが望ましい。 Second cutting width W2 is not particularly limited, as small as possible in view of the material savings is desirable.
接着フィルム12、14、16の側面の傾斜角度θは、ブレード33の刃先の形状を、例えば30度とすることにより定めることができる。 The inclination angle of the side surface of the adhesive film 12, 14, 16 theta can be defined by the cutting edge of the shape of the blade 33, for example, 30 degrees.

半導体ウェーハ30と接着フィルム32とは、材質および厚さが異なるので、それぞれ最適なダイシング条件、例えばブレードの回転数、ブレード厚さ、ダイシング速度を有している。 The semiconductor wafer 30 and the adhesive film 32, since the material and thickness are different, has the optimum dicing conditions respectively, for example, the rotation speed of the blades, blade thickness, the dicing speed.

従来、最適なダイシング条件が異なる半導体ウェーハ30および接着フィルム32を、半導体ウェーハ30側から同時に切断していたので、接着フィルム32が過大な応力によりダメージを受けて切れ端が生じ易かった。 Conventionally, a semiconductor wafer 30 and the adhesive film 32 optimal dicing conditions are different, because I cut simultaneously from a semiconductor wafer 30 side, swarf is was easy to occur damaged by the adhesive film 32 is overstressed.

しかし、本実施例では、半導体ウェーハ30および接着フィルム32を、別々に切断するようにしたので、それぞれ最適な条件で切断することができる。 However, in this embodiment, the semiconductor wafer 30 and the adhesive film 32, since the to cut separately, can be cut at each optimum condition. 従って、接着フィルム32の切断時に、切れ端を出にくくすることが可能である。 Therefore, when cutting the adhesive film 32, it is possible to hardly leave the snips.

更に、接着フィルム32の側面を末広がり状に傾斜させることができるので、切り終わり時でも、ブレード33の切断力が接着フィルム32に適切に伝わり、滑らかな断面形状が得られる。 Furthermore, it is possible to incline the side of the adhesive film 32 to the flared, even when end cutting, the cutting force of the blade 33 is transmitted to the appropriate adhesive film 32, a smooth sectional shape can be obtained.

次に、図3(a)に示すように、接着フィルム12を基板11に当接させ、ボンディングパッド21から距離L1だけ離間させて最初の半導体チップ13を載置する。 Next, as shown in FIG. 3 (a), the adhesive film 12 is in contact with the substrate 11, is spaced from the bonding pad 21 by a distance L1 placing a first semiconductor chip 13.
接着フィルム14を半導体チップ13に当接させ、半導体チップ13のボンディングパッド18から距離L2だけ離間させて2番目の半導体チップ15を載置する。 The adhesive film 14 is in contact with the semiconductor chip 13, for mounting a second semiconductor chip 15 is separated from the bonding pads 18 of the semiconductor chip 13 by a distance L2.
接着フィルム16を半導体チップ15に当接させて、半導体チップ15のボンディングパッド19から距離L3だけ離間させて3番目の半導体チップ17を載置する。 The adhesive film 16 is brought into contact with the semiconductor chip 15 places the third semiconductor chip 17 is separated from the bonding pads 19 of the semiconductor chip 15 by a distance L3.

次に、図3(b)に示すように、基板11を、例えばホットプレート38で175℃×1h程度加熱して、接着フィルム12、14、16を硬化させることにより、各半導体チップ13、15、17を固着する。 Next, as shown in FIG. 3 (b), the substrate 11, for example by heating about 175 ° C. × 1h in a hot plate 38, by curing the adhesive film 12, 14, 16, each of the semiconductor chips 13 and 15 to secure the 17.
これにより、基板11上に各接着フィルム12、14、16を介して各半導体チップ13、15、17が積層される。 Thus, the semiconductor chips 13, 15, and 17 via the respective adhesive films 12, 14, 16 on the substrate 11 is laminated.

次に、図3(c)に示すように、ワイヤボンダ(図示せず)により超音波を印加して、ワイヤ22を半導体チップ13のボンディングパッド18と基板11のボンディングパッド21aに接続する。 Next, as shown in FIG. 3 (c), by applying ultrasonic waves by wire bonder (not shown), connecting the wire 22 to the bonding pad 21a of the bonding pad 18 and the substrate 11 of the semiconductor chip 13.
同様に、ワイヤ23を半導体チップ15のボンディングパッド19と基板11のボンディングパッド21bに接続する。 Similarly, to connect the wire 23 to the bonding pad 21b of the bonding pad 19 and the substrate 11 of the semiconductor chip 15.
ワイヤ24を半導体チップ17のボンディングパッド20と基板11のボンディングパッド21cに接続する。 Connecting the wire 24 to the bonding pad 21c of the bonding pad 20 and the substrate 11 of the semiconductor chip 17.

次に、基板11上に接着フィルム12、14、16を介して積層された半導体チップ13、15、17およびワイヤ22、23、24を、樹脂27でモールドし、パッケージ28に収納する。 Next, the semiconductor chips 13, 15 and the wires 22, 23 and 24 are laminated with an adhesive film 12, 14, 16 on the substrate 11, it is molded with a resin 27, housed in a package 28. これにより、図1に示す半導体装置10が得られる。 Thus, the semiconductor device 10 shown in FIG. 1 is obtained.

図4は、本実施例に係る半導体装置10の効果を、比較例と対比して示す図で、図4(a)が本実施例の場合、図4(b)、図4(c)が比較例の場合である。 4, the effect of the semiconductor device 10 according to the present embodiment, a view showing by comparison with a comparative example, if FIGS. 4 (a) is in this embodiment, FIG. 4 (b), the 4 (c) is it is a case of the comparative example.
ここで、比較例とは、接着シートのサイズと半導体チップのサイズとが等しく設定された半導体装置を意味している。 Here, a comparative example means a semiconductor device and the size of the size of the semiconductor chip of the adhesive sheet was set to be equal.

図4(a)に示すように、本実施例では、接着フィルム12に切れ端が生じにくいが、例え切れ端64が生じても、半導体チップ13からはみ出す恐れが無いので、基板11のボンディングパッド21から距離L1だけ離間して、半導体チップ13を基板11上に載置することが可能である。 As shown in FIG. 4 (a), in this embodiment, but less likely to occur scraps the adhesive film 12, even if a piece 64 occurs, there is no possibility that protrudes from the semiconductor chip 13, the bonding pad 21 of the substrate 11 distance L1 only apart, the semiconductor chip 13 can be placed on the substrate 11.
同様に、接着フィルム14に切れ端が生じにくいが、例え切れ端65が生じても、半導体チップ15からはみ出す恐れが無いので、半導体チップ13のボンディングパッド18から距離L2だけ離間して、半導体チップ15を半導体チップ13上に載置することが可能である。 Similarly, although less likely to occur scraps to the adhesive film 14, even if a piece 65 occurs, there is no possibility that protrudes from the semiconductor chip 15, spaced from the bonding pad 18 of the semiconductor chip 13 by a distance L2, the semiconductor chip 15 It can be placed on the semiconductor chip 13.
接着フィルム16に切れ端66が生じにくいが、例え切れ端66が生じても、半導体チップ17からはみ出す恐れが無いので、半導体チップ15のボンディングパッド19から距離L3だけ離間して、半導体チップ17を半導体チップ15上に載置することが可能である。 The adhesive film 16 snips 66 is unlikely to occur in but even if a piece 66 occurs, since there is no risk that protrudes from the semiconductor chip 17, spaced from the bonding pad 19 of the semiconductor chip 15 by a distance L3, the semiconductor chip and the semiconductor chip 17 It can be placed on 15.

これに対して、図4(b)に示すように、比較例1では、接着フィルム42に切れ端61が生じ易いので、ワイヤボンディングが妨げられ、基板11のボンディングポッド21にワイヤ52、53、54をボンディングすることができなくなる。 In contrast, as shown in FIG. 4 (b), in Comparative Example 1, because it is easy snips 61 is generated in the adhesive film 42, wire bonding is prevented, wire bonding pod 21 of the substrate 11 52 53 it is impossible to bonding.

同様に、接着フィルム44に切れ端62が生じ易いので、ワイヤボンディングが妨げられ、半導体チップ43のボンディングパッド48にワイヤ52をボンディングすることができなくなる。 Similarly, because it is easy snips 62 is generated in the adhesive film 44, wire bonding is prevented, it becomes impossible to bond the wire 52 to the bonding pads 48 of the semiconductor chip 43.
接着フィルム46に切れ端63が生じ易いので、ワイヤボンディングが妨げられ、半導体チップ45のボンディングパッド49にワイヤ53をボンディングすることができなくなる。 Snips 63 is so liable to occur in the adhesive film 46, wire bonding is prevented, it becomes impossible to bond the wire 53 to the bonding pads 49 of the semiconductor chip 45.

そのため、図4(c)に示すように、比較例2では、半導体チップ43を基板11のボンディングパッド21から距離L1+ΔL1だけ離間して基板11上に載置しなければならない。 Therefore, as shown in FIG. 4 (c), in Comparative Example 2, it shall be placed on the substrate 11 by a semiconductor chip 43 away from the bonding pad 21 of the substrate 11 by a distance L1 + .DELTA.L1.
同様に、半導体チップ45を半導体チップ43のボンディングパッド48から距離L2+ΔL2だけ離間して、半導体チップ43上に載置しなければならない。 Similarly, separate the semiconductor chips 45 from the bonding pads 48 of the semiconductor chip 43 by a distance L2 + [Delta] L2, it must be placed on the semiconductor chip 43.
半導体チップ47を半導体チップ45のボンディングパッド49から距離L3+ΔL3だけ離間して半導体チップ45上に載置しなければならない。 It shall placed on the semiconductor chip 45 to separate the semiconductor chips 47 from the bonding pads 49 of the semiconductor chip 45 by a distance L3 + .DELTA.L3.

従って、本実施例では、同一基板11上に、比較例よりサイズの大きな半導体チップ13、15、17を積層することができるので、集積度の高いMCPタイプの半導体装置が得られる。 Thus, in this embodiment, on the same substrate 11, it is possible to stack a large semiconductor chip 13, 15, and 17 of size than the comparative example, the semiconductor device of high integration density MCP type is obtained.

以上説明したように、本実施例では、半導体ウェーハ30と接着フィルム32とを、それぞれ別々に最適ダイシング条件で切断している。 As described above, in this embodiment, the semiconductor wafer 30 and the adhesive film 32 is cut with separately optimized dicing condition.
これにより得られた、サイズが小さく且つ側面が傾斜した接着フィルム12、14、16を有する半導体チップ13、15、17を、基板11上に積層している。 Thus obtained, the semiconductor chip 13, 15 and 17 having an adhesive film 12, 14, 16 the size is small and the side surface is inclined, are stacked on the substrate 11.

その結果、接着フィルム12、14、16の側面に切れ端が生じにくく、仮に切れ端が生じても半導体チップ13、15、17からはみ出す恐れが無いので、支障なくワイヤボンディングを行うことができる。 As a result, hardly occurs scraps on the side surface of the adhesive film 12, 14, 16, if there is no possibility that protrudes from the semiconductor chip 13, 15, and 17 even if a piece can be performed without hindrance wire bonding.
従って、半導体チップから接着フィルムがはみ出さないようして、複数の半導体チップを積層した半導体装置およびその製造方法が得られる。 Thus, by so does not protrude adhesive film from the semiconductor chip, a semiconductor device and a manufacturing method thereof by laminating a plurality of semiconductor chips are obtained.

ここでは、基板11上に、3個の半導体チップ13、15、17を積層した場合について説明したが、積層する個数には特に制限は無く、更に多くの半導体チップを積層しても構わない。 Here, on the substrate 11 has been described as being laminated three semiconductor chips 13, 15 and 17, not particularly limited to the number of laminating, it may be laminated more semiconductor chips.

また、基板11に最も近い半導体チップ13が、接着フィルム12を介して基板11に固着されている場合について説明したが、半導体チップ13を接着フィルム12と異なる接着材、例えばペーストや共晶で基板11上に固着しても構わない。 Further, the substrate closest to the semiconductor chip 13 to the substrate 11, the description has been given of the case via the adhesive film 12 is fixed to the substrate 11, the semiconductor chip 13 the adhesive film 12 is different from the adhesive, for example, paste or eutectic it may be fixed on the 11.
これによれば、ダイシング回数を減らすことができるので、製造工程が簡単になる利点がある。 According to this, it is possible to reduce a dicing number, there is an advantage that the manufacturing process is simplified.

接着フィルム32を、半導体ウェーハ30の第2の面30bに至るところまで切断する場合について説明したが、半導体ウェーハ30の第2の面30bを少し切り込むところまで切断しても構わない。 The adhesive film 32 has been described for the case of cutting up everywhere on the second surface 30b of the semiconductor wafer 30, it may be cut to the point where little cutting a second face 30b of the semiconductor wafer 30.
これによれば、接着フィルム32および半導体ウェーハ30の厚さのばらつきあっても、接着フィルム32の切断が確実に行えるとともに、ダイシングの切り込み量の調節が容易になる利点がある。 According to this, even if variations in the thickness of the adhesive film 32 and the semiconductor wafer 30, cutting with can be reliably performed in the adhesive film 32, there is an advantage that it is easy to adjust the cutting depth of the dicing.

本発明の実施例に係る半導体装置の構成を示す図で、図1(a)はその平面図、図1(b)は図1(a)のA−A線に沿って切断し、矢印の方向に眺めた断面図。 A diagram showing a structure of a semiconductor device according to an embodiment of the present invention, FIG. 1 (a) is a plan view thereof, FIG. 1 (b) taken along line A-A of FIG. 1 (a), the arrow a cross-sectional view as viewed in the direction. 本発明の実施例に係る半導体装置の製造工程を順に示す断面図。 Sectional view sequentially illustrating the fabrication process of the semiconductor device according to the embodiment of the present invention. 本発明の実施例に係る半導体装置の製造工程を順に示す断面図。 Sectional view sequentially illustrating the fabrication process of the semiconductor device according to the embodiment of the present invention. 本発明の実施例に係る半導体装置の効果を比較例と対比して示す図で、図4(a)は本実施例を示す断面図、図4(b)、図4(c)は比較例を示す断面図。 In view showing by comparing the effect of the semiconductor device according to the embodiment of the present invention and comparative example, FIGS. 4 (a) is a sectional view showing an embodiment, FIG. 4 (b), the FIG. 4 (c) Comparative Example sectional view showing a.

符号の説明 DESCRIPTION OF SYMBOLS

10、60 半導体装置11 基板12、14、16、32、42、44、46 接着フィルム13、15、17、37、43、45、47 半導体チップ18,19、20、21、48、49、50 ボンディングパッド22、23、24、52、53、54 ワイヤ(接続導体) 10, 60 semiconductor device 11 substrate 12,14,16,32,42,44,46 adhesive film 13,15,17,37,43,45,47 semiconductor chip 18,19,20,21,48,49,50 bonding pads 22,23,24,52,53,54 wires (connection conductor)
25 ビア26 端子27 樹脂28 パッケージ30 半導体ウェーハ30a 第1の面30b 第2の面31、35 ダイシングシート33、36 ブレート34 ダイシングライン38 ホットプレート61、62、63、64、65、66 切れ端 25 via 26 pin 27 first surface 30b resin 28 package 30 semiconductor wafer 30a a second surface 31, 35 the dicing sheet 33, 36 Bureto 34 dicing lines 38 hot plate 61 to 66 scraps

Claims (5)

  1. 基板上に、それぞれ接着フィルムを介して積層された複数の半導体チップと、 On a substrate, a plurality of semiconductor chips stacked via respective adhesive film,
    前記複数の半導体チップにそれぞれ形成されたボンディングパッドを、前記基板に形成された複数のボンディングパッドに電気的に接続する複数の接続導体と、 A plurality of connecting conductors for electrically connecting the bonding pads formed respectively on the plurality of semiconductor chips, the plurality of bonding pads formed on the substrate,
    前記複数の半導体チップおよび前記複数の接続導体をモールドする樹脂と、 A resin for molding the plurality of semiconductor chips and said plurality of connection conductors,
    を具備し、 Equipped with,
    前記接着フィルムのサイズが、前記接着フィルムの上に載置されている前記半導体チップのサイズより小さいことを特徴とする半導体装置。 The size of the adhesive film, a semiconductor device wherein the smaller than the size of the semiconductor chip is placed on the adhesive film.
  2. 前記接着フィルムのサイズが、前記半導体チップのサイズより0.2mm乃至1mm小さいことを特徴とする請求項1に記載の半導体装置。 The size of the adhesive film, the semiconductor device according to claim 1, wherein the 0.2mm to 1mm smaller than the size of the semiconductor chip.
  3. 前記接着フィルムの側面が、前記接着フィルムの上に載置されている前記半導体チップ側に向かって末広がり状に傾斜していることを特徴とする請求項1に記載の半導体装置。 The side of the adhesive film, the semiconductor device according to claim 1, characterized in that inclined flared toward the semiconductor chip side, which is placed on the adhesive film.
  4. 前記基板に最も近い前記半導体チップが、前記接着フィルムと異なる接着材を介して前記基板に固着されていることを特徴とする請求項1に記載の半導体装置。 The semiconductor device of claim 1, nearest the semiconductor chip to the substrate, characterized in that it is fixed to the substrate via an adhesive different from the adhesive film.
  5. 半導体ウェーハのボンディングパッドが形成された第1の面と対向する第2の面に、接着フィルムを貼り付け、前記第2の面側からダイシングラインに沿って、前記接着フィルムを第1の切削幅で前記半導体ウェーハに至るまで切断する工程と、 A second surface facing the first surface where the bonding pads of the semiconductor wafer is formed, pasting an adhesive film, along the dicing line from said second surface, said adhesive film first cutting width and cutting up to the semiconductor wafer in,
    前記第1の面側から前記ダイシングラインに沿って、前記半導体ウェーハを前記第1の切削幅より小さい第2の切削幅で切断し、複数の半導体チップに分割する工程と、 Along the dicing line from said first surface, said semiconductor wafer is cut by the first cutting width smaller than a second width of cut, a step of dividing the plurality of semiconductor chips,
    複数のボンディングパッドが形成された基板上に、それぞれ前記第2の面に貼り付けられた前記接着フィルムを介して前記複数の半導体チップを積層する工程と、 A plurality of bonding pads formed on the substrate, laminating the plurality of semiconductor chips through the adhesive film which are respectively affixed to said second surface,
    前記複数の半導体チップにそれぞれ形成された前記ボンディングパッドを、前記基板に形成された前記ボンディングパッドに接続導体を介して電気的に接続する工程と、 A step of electrically connecting the plurality of the bonding pads formed respectively on the semiconductor chip, via the connecting conductors to the bonding pads formed on the substrate,
    前記複数の半導体チップおよび前記複数の接続導体を樹脂でモールドする工程と、 A step of molding a resin to the plurality of semiconductor chips and said plurality of connection conductors,
    を具備することを特徴とする半導体装置の製造方法。 The method of manufacturing a semiconductor device characterized by comprising a.
JP2007061836A 2007-03-12 2007-03-12 Semiconductor device and its manufacturing method Pending JP2008227068A (en)

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Publication number Priority date Publication date Assignee Title
KR101333398B1 (en) 2012-02-14 2013-11-28 앰코 테크놀로지 코리아 주식회사 Semiconductor device and manufacturing method thereof
JP2014516419A (en) * 2011-03-21 2014-07-10 ジョンソン・アンド・ジョンソン・ビジョン・ケア・インコーポレイテッドJohnson & Johnson Vision Care, Inc. Method and apparatus for functional insert having a power layer
US9675443B2 (en) 2009-09-10 2017-06-13 Johnson & Johnson Vision Care, Inc. Energized ophthalmic lens including stacked integrated components
US9698129B2 (en) 2011-03-18 2017-07-04 Johnson & Johnson Vision Care, Inc. Stacked integrated component devices with energization
US9703120B2 (en) 2011-02-28 2017-07-11 Johnson & Johnson Vision Care, Inc. Methods and apparatus for an ophthalmic lens with functional insert layers
US9889615B2 (en) 2011-03-18 2018-02-13 Johnson & Johnson Vision Care, Inc. Stacked integrated component media insert for an ophthalmic device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9675443B2 (en) 2009-09-10 2017-06-13 Johnson & Johnson Vision Care, Inc. Energized ophthalmic lens including stacked integrated components
US9703120B2 (en) 2011-02-28 2017-07-11 Johnson & Johnson Vision Care, Inc. Methods and apparatus for an ophthalmic lens with functional insert layers
US9889615B2 (en) 2011-03-18 2018-02-13 Johnson & Johnson Vision Care, Inc. Stacked integrated component media insert for an ophthalmic device
US9914273B2 (en) 2011-03-18 2018-03-13 Johnson & Johnson Vision Care, Inc. Method for using a stacked integrated component media insert in an ophthalmic device
US9698129B2 (en) 2011-03-18 2017-07-04 Johnson & Johnson Vision Care, Inc. Stacked integrated component devices with energization
US9804418B2 (en) 2011-03-21 2017-10-31 Johnson & Johnson Vision Care, Inc. Methods and apparatus for functional insert with power layer
JP2014516419A (en) * 2011-03-21 2014-07-10 ジョンソン・アンド・ジョンソン・ビジョン・ケア・インコーポレイテッドJohnson & Johnson Vision Care, Inc. Method and apparatus for functional insert having a power layer
KR101333398B1 (en) 2012-02-14 2013-11-28 앰코 테크놀로지 코리아 주식회사 Semiconductor device and manufacturing method thereof

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