CN212434614U - Silicon-based three-dimensional fan-out integrated packaging structure - Google Patents
Silicon-based three-dimensional fan-out integrated packaging structure Download PDFInfo
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- CN212434614U CN212434614U CN202020874147.4U CN202020874147U CN212434614U CN 212434614 U CN212434614 U CN 212434614U CN 202020874147 U CN202020874147 U CN 202020874147U CN 212434614 U CN212434614 U CN 212434614U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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Abstract
The utility model discloses an integrated packaging structure of three-dimensional fan-out of silica-based belongs to integrated circuit wafer level packaging technology field. The silicon-based three-dimensional fan-out integrated packaging structure comprises a silicon substrate, wherein TSV blind holes are formed in the front surface of the silicon substrate, and an inorganic passivation layer is deposited on the surface of the silicon substrate; a copper column is manufactured in the TSV blind hole, and a first n-layer rewiring and a metal welding pad are manufactured on the surface of the TSV blind hole; a groove is etched in the back surface of the silicon substrate, a first chip is buried in the groove through a bonding agent, and a welding pad of the first chip faces outwards; the back surface of the silicon substrate is filled with a dry film material, and a passivation layer, a second n-layer rewiring and salient points are sequentially manufactured on the back surface of the silicon substrate. The utility model discloses an use silica-based three-dimensional fan-out type wafer level encapsulation of realization, accomplish the three-dimensional integration of high density heterogeneous chip, its packaging efficiency, integrated level, performance improve greatly.
Description
Technical Field
The utility model relates to an integrated circuit wafer level encapsulation technical field, in particular to integrated packaging structure of three-dimensional fan-out of silica-based.
Background
As transistor feature sizes shrink below 10nm, gate oxide thicknesses are only a few tenths or even a few atoms thick, which has begun to approach physical limits. Leakage due to quantum tunneling effects will be very severe, and chip development and manufacturing costs based on moore law (MooreLaw) will also increase by geometric multiples. Therefore, attention is turned to advanced packaging, wherein a fan-out package is innovated from a system integration mode, functional application and product requirements are used as driving, performance in aspects of product transmission, power consumption, size, reliability and the like is effectively improved, and the fan-out package is a good choice in view of cost and research and development difficulty.
There are two main types of fan-out packages: resin-type and silicon-based fan-out. Silicon-based fan-out is also receiving increasing attention as silicon-based processes are the most widely used technology at the present time. The TSV technology based on the dry etching process can realize three-dimensional fan-out integration, for example, patent CN201710608974.1 provides a thin 3D fan-out packaging structure and a wafer level packaging method, TSV and silicon-based grooves are etched out simultaneously by the method, and due to the fact that the sizes of openings are different, the etching depths of the TSV and the grooves are different; in addition, the TSV is filled with copper under the condition that the silicon-based surface is provided with the groove, and the difficulty is high.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide an integrated packaging structure of three-dimensional fan-out of silica-based to solve the not high and performance relatively poor of present packaging mode integrated level, the problem that preparation efficiency is also low.
In order to solve the technical problem, the utility model provides a silicon-based three-dimensional fan-out integrated packaging structure, which comprises a silicon substrate,
the front surface of the silicon substrate is provided with TSV blind holes and an inorganic passivation layer is deposited on the surface of the silicon substrate; a copper column is manufactured in the TSV blind hole, and a first n-layer rewiring and a metal welding pad are manufactured on the surface of the TSV blind hole;
a groove is etched in the back surface of the silicon substrate, a first chip is buried in the groove through a bonding agent, and a welding pad of the first chip faces outwards;
the back surface of the silicon substrate is filled with a dry film material, and a passivation layer, a second n-layer rewiring and salient points are sequentially manufactured on the back surface of the silicon substrate.
Optionally, the silicon-based three-dimensional fan-out integrated package structure further includes a plurality of second chips, and the second chips are connected with the first n layers of rewiring or metal pads through micro-bumps; the bottom of the second chip is filled with filling material.
Optionally, the filler is a polymer material.
Optionally, the thickness of the inorganic passivation layer is more than 0.1 μm, and the material is one of inorganic materials;
wherein the inorganic material includes SiO2, SiC, and SiN.
Optionally, the metal pad is made of Ti, W, Cu, Ni, or Au.
Optionally, the size of the groove is larger than the size of the first chip.
Optionally, the first chip is attached to the inorganic passivation layer by the adhesive.
The utility model provides a silicon-based three-dimensional fan-out integrated package structure, which comprises a silicon substrate, wherein the front surface of the silicon substrate is provided with TSV blind holes and an inorganic passivation layer is deposited on the surface of the silicon substrate; a copper column is manufactured in the TSV blind hole, and a first n-layer rewiring and a metal welding pad are manufactured on the surface of the TSV blind hole; a groove is etched in the back surface of the silicon substrate, a first chip is buried in the groove through a bonding agent, and a welding pad of the first chip faces outwards; the back surface of the silicon substrate is filled with a dry film material, and a passivation layer, a second n-layer rewiring and salient points are sequentially manufactured on the back surface of the silicon substrate. The utility model discloses an use silica-based three-dimensional fan-out type wafer level encapsulation of realization, accomplish the three-dimensional integration of high density heterogeneous chip (like CPU, DSP, FPGA and HBM etc.), its encapsulation efficiency, integrated level, performance improve greatly.
Drawings
Fig. 1 is a schematic diagram of a silicon-based three-dimensional fan-out integrated package structure provided by the present invention;
FIG. 2 is a schematic illustration of a silicon substrate provided;
FIG. 3 is a schematic diagram of fabricating a TSV blind via on a front side of a silicon substrate;
FIG. 4 is a schematic illustration of depositing an inorganic passivation layer on a surface of a silicon-based front side;
FIG. 5 is a schematic diagram of fabricating a copper pillar in a TSV blind via and fabricating a first n-layer rewiring and a metal pad on the surface;
fig. 6 is a schematic diagram of bonding a glass carrier on a silicon-based front surface through a temporary bonding layer;
FIG. 7 is a schematic illustration of thinning a silicon-based backside;
FIG. 8 is a schematic diagram illustrating etching to expose TSV blind vias;
FIG. 9 is a schematic diagram of etching a recess in a silicon substrate backside;
FIG. 10 is a schematic view of a silicon-based backside filled with a dry film material and opened with holes;
FIG. 11 is a schematic diagram illustrating the inorganic passivation layer on the surface layer of the TSV blind via is etched clean;
fig. 12 is a schematic diagram of sequentially fabricating a passivation layer, a second n-layer rewiring and bumps on a silicon-based backside.
Detailed Description
The silicon-based three-dimensional fan-out integrated package structure provided by the present invention is further described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more fully apparent from the following description and appended claims. It should be noted that the drawings are in simplified form and are not to precise scale, and are provided for convenience and clarity in order to facilitate the description of the embodiments of the present invention.
Example one
The utility model provides a silicon-based three-dimensional fan-out integrated packaging structure, the structure of which is shown in figure 1, comprising a silicon substrate 101, wherein TSV blind holes are manufactured on the front surface of the silicon substrate 101 and an inorganic passivation layer 103 is deposited on the surface of the silicon substrate 101; a copper pillar 104 is manufactured in the TSV blind hole, and a first n-layer rewiring 105 and a metal welding pad 106 are manufactured on the surface of the TSV blind hole; the thickness of the inorganic passivation layer 103 is more than 0.1 μm, the material is one of inorganic materials, and the inorganic materials include SiO2, SiC and SiN. The metal pad 106 is made of Ti, W, Cu, Ni, or Au.
A groove is etched in the back surface of the silicon substrate 101, the first chip 201 is buried in the groove through the bonding agent 203, and the welding pad 202 of the first chip 201 faces outwards; the back surface of the silicon substrate 101 is filled with a dry film material 110, and a passivation layer 111, a second n-layer rewiring 112 and bumps 113 are sequentially formed on the back surface of the silicon substrate 101. The size of the groove is larger than that of the first chip 201; the first chip 201 is adhered to the inorganic passivation layer 103 by the adhesive 203.
The silicon-based three-dimensional fan-out integrated packaging structure further comprises a plurality of second chips (comprising a second chip 301, a second chip 302 and a second chip 303), wherein the second chips are connected with the first n layers of rewirings 105 or metal welding pads 106 through micro bumps 304; the second chip 301 and the second chip 303 are connected with the first n-layer rewiring 105 through a micro bump 304, and the second chip 302 is connected with the metal pad 106 through the micro bump 304; the bottom of the second chip is filled with a filling material 305, and the filling material 305 is a polymer material.
The silicon-based three-dimensional fan-out integrated packaging structure is manufactured by the following method:
as shown in fig. 2, a silicon substrate 101 is provided, and the front surface of the silicon substrate 101 is finely ground to 5 to 50 μm;
as shown in fig. 3, a TSV blind hole 102 is formed in the front surface of the silicon substrate 101 by photolithography and dry etching;
as shown in fig. 4, depositing an inorganic passivation layer 103 on the surface of the front surface of the silicon substrate 101; wherein, the thickness of the inorganic passivation layer 103 is more than 0.1 μm, and the material is one of inorganic materials; the inorganic material includes SiO2, SiC, and SiN;
as shown in fig. 5, a copper pillar 104 is formed in the TSV blind hole 102, and a first n-layer rewiring 105 and a metal pad 106 are formed on the surface; the metal pad 106 is made of Ti, W, Cu, Ni or Au;
as shown in fig. 6, a glass carrier 108 is bonded to the front surface of the silicon substrate 101 through a temporary bonding layer 107, where the bonding mode is laser, thermal decomposition, or mechanical; the thickness of the glass carrier 108 is more than 50 μm, and the thickness of the temporary bonding layer 107 is more than 1 μm;
as shown in fig. 7, after bonding is completed, the back surface of the silicon substrate 101 is thinned in a mechanical grinding manner, so that the distance H from the back surface of the silicon substrate 101 to the bottom of the TSV blind hole 102 is 1-50 μm;
as shown in fig. 8, the TSV blind holes are exposed by continuing to use dry etching or wet etching, and the exposure height T is not less than 1 μm;
as shown in fig. 9, a groove 109 is etched on the back surface of the silicon substrate 101, the groove 109 is etched to the inorganic passivation layer 103, and the size of the groove 109 is larger than that of the first chip to be embedded; embedding a first chip 201 in the groove 109 by using a high-precision chip mounting technology, wherein a welding pad 202 of the first chip 201 faces outwards, and the first chip 201 is adhered to the inorganic passivation layer 103 through an adhesive 203;
as shown in fig. 10, the dry film material 110 is filled on the back surface of the silicon substrate 101, and a hole is formed at the pad 202 and the TSV blind hole 102 by using a photolithography technique, wherein the size of the hole is greater than or equal to 1 μm, but smaller than the size of the hole diameter of the pad 202 and the TSV blind hole 102;
as shown in fig. 11, the inorganic passivation layer 103 on the surface layer of the TSV blind hole 102 is completely etched by using an inorganic passivation layer etching technology, and the over-etching is kept at 10%;
as shown in fig. 12, a passivation layer 111, a second n-layer rewiring 112 and bumps 113 are sequentially formed on the back surface of the silicon substrate 101 by photolithography, physical vapor deposition and electroplating;
as shown in fig. 1, the glass carrier 108 is removed and the temporary bonding layer 107 is cleaned, and a plurality of second chips (including a second chip 301, a second chip 302 and a second chip 303) are soldered on the front surface of the silicon substrate 101 by using a flip chip soldering technique, and the second chips are connected with the first n-layer rewiring 105 or the metal pad 106 through the micro bumps 304; the second chip 301 and the second chip 303 are connected with the first n-layer rewiring 105 through a micro bump 304, and the second chip 302 is connected with the metal pad 106 through the micro bump 304; the bottom of the second chip is filled with a filling material 305, the filling material 305 is a high molecular material, and finally, the final packaging is completed by cutting.
The above description is only for the preferred embodiment of the present invention and is not intended to limit the scope of the present invention, and any modification and modification made by those skilled in the art according to the above disclosure are all within the scope of the claims.
Claims (7)
1. A silicon-based three-dimensional fan-out integrated package structure, comprising a silicon base (101),
TSV blind holes are formed in the front surface of the silicon substrate (101) and an inorganic passivation layer (103) is deposited on the surface of the silicon substrate; a copper column (104) is manufactured in the TSV blind hole, and a first n-layer rewiring (105) and a metal welding pad (106) are manufactured on the surface of the TSV blind hole;
a groove is etched in the back surface of the silicon substrate (101), a first chip (201) is buried in the groove through a bonding agent (203), and a welding pad (202) of the first chip (201) faces outwards;
the back surface of the silicon substrate (101) is filled with a dry film material (110), and a passivation layer (111), a second n-layer rewiring (112) and bumps (113) are sequentially manufactured on the back surface of the silicon substrate (101).
2. The silicon-based three-dimensional fan-out integrated package structure of claim 1, further comprising a number of second chips connected to the first n layers of rewiring (105) or metal pads (106) through micro bumps (304); the second chip bottom is filled with a filling material (305).
3. The silicon-based three-dimensional fan-out integrated package structure of claim 2, wherein the filler (305) is a polymer-based material.
4. The silicon-based three-dimensional fan-out integrated package structure of claim 1, wherein the inorganic passivation layer (103) has a thickness of 0.1 μm or more and is made of one of inorganic materials;
wherein the inorganic material includes SiO2, SiC, and SiN.
5. The silicon-based three-dimensional fan-out integrated package structure of claim 1, wherein the metal pads (106) are made of Ti, W, Cu, Ni or Au.
6. The silicon-based three-dimensional fan-out integrated package structure of claim 1, wherein a size of the recess is larger than a size of the first chip (201).
7. The silicon-based three-dimensional fan-out integrated package structure of claim 1, wherein the first chip (201) is attached to the inorganic passivation layer (103) by the adhesive (203).
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111463137A (en) * | 2020-05-22 | 2020-07-28 | 中国电子科技集团公司第五十八研究所 | Silicon-based three-dimensional fan-out integrated packaging method and structure thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111463137A (en) * | 2020-05-22 | 2020-07-28 | 中国电子科技集团公司第五十八研究所 | Silicon-based three-dimensional fan-out integrated packaging method and structure thereof |
| CN111463137B (en) * | 2020-05-22 | 2024-05-28 | 中国电子科技集团公司第五十八研究所 | Silicon-based three-dimensional fan-out integrated packaging method and structure thereof |
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