CN111029411A - Wafer-level packaging method and structure of photoelectric device - Google Patents
Wafer-level packaging method and structure of photoelectric device Download PDFInfo
- Publication number
- CN111029411A CN111029411A CN201911297393.6A CN201911297393A CN111029411A CN 111029411 A CN111029411 A CN 111029411A CN 201911297393 A CN201911297393 A CN 201911297393A CN 111029411 A CN111029411 A CN 111029411A
- Authority
- CN
- China
- Prior art keywords
- wafer
- groove
- chip
- chip wafer
- grinding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 46
- 238000000034 method Methods 0.000 title claims abstract description 36
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 36
- 229910052802 copper Inorganic materials 0.000 claims abstract description 36
- 239000010949 copper Substances 0.000 claims abstract description 36
- 239000004033 plastic Substances 0.000 claims abstract description 26
- 239000011521 glass Substances 0.000 claims abstract description 23
- 238000000227 grinding Methods 0.000 claims abstract description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 19
- 239000010410 layer Substances 0.000 claims abstract description 19
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 19
- 239000010703 silicon Substances 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 13
- 239000002346 layers by function Substances 0.000 claims abstract description 12
- 238000011049 filling Methods 0.000 claims abstract description 10
- 239000005022 packaging material Substances 0.000 claims abstract description 10
- 229910000679 solder Inorganic materials 0.000 claims abstract description 10
- 238000005520 cutting process Methods 0.000 claims abstract description 7
- 239000003292 glue Substances 0.000 claims abstract description 7
- 239000000463 material Substances 0.000 claims description 17
- 239000000853 adhesive Substances 0.000 claims description 12
- 230000001070 adhesive effect Effects 0.000 claims description 12
- 150000001875 compounds Chemical class 0.000 claims description 10
- 238000000465 moulding Methods 0.000 claims description 10
- 229920005989 resin Polymers 0.000 claims description 7
- 239000011347 resin Substances 0.000 claims description 7
- 239000007769 metal material Substances 0.000 claims description 5
- 239000002861 polymer material Substances 0.000 claims description 5
- 239000004642 Polyimide Substances 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 238000004090 dissolution Methods 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 229920001721 polyimide Polymers 0.000 claims description 3
- 238000002360 preparation method Methods 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 claims description 2
- 230000005693 optoelectronics Effects 0.000 claims 3
- 238000003384 imaging method Methods 0.000 abstract description 3
- 230000031700 light absorption Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000009740 moulding (composite fabrication) Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0203—Containers; Encapsulations, e.g. encapsulation of photodiodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/02002—Arrangements for conducting electric current to or from the device in operations
- H01L31/02005—Arrangements for conducting electric current to or from the device in operations for device characterised by at least one potential jump barrier or surface barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Dicing (AREA)
Abstract
The invention discloses a wafer-level packaging method and structure of a photoelectric device, and belongs to the technical field of integrated circuit packaging. Providing a glass cover plate, and manufacturing a mask pattern on the surface of the glass cover plate; plastically packaging the mask pattern, and grinding to the target thickness of the cofferdam; removing the grinding pattern, and bonding the chip wafer with the cofferdam through bonding glue; thinning a chip wafer, etching a groove on the back of the chip wafer, and growing a copper column in the groove; filling the groove, and grinding until the copper pillar is exposed; and manufacturing n layers of rewiring, a solder mask layer and salient points, and cutting to form a single packaged chip. The cofferdam is manufactured through primary plastic packaging, the functional layer is interconnected with the back surface of the silicon substrate through secondary plastic packaging, and the rewiring area of the back surface of the silicon substrate is increased. Except one surface of the glass cover plate, other five surfaces of the whole packaging body are wrapped by the plastic packaging material, so that the problem of imaging ghost of the photoelectric device caused by light leakage is solved; the packaging method and the structure are simple, the cost is low, the yield is high, and the packaging method is suitable for large-scale mass production.
Description
Technical Field
The invention relates to the technical field of integrated circuit packaging, in particular to a wafer-level packaging method and structure of a photoelectric device.
Background
In recent years, with the appearance and development of three-shot, four-shot and even five-shot mobile phone cameras, the packaging requirements of photoelectric devices, especially image sensors, are increasing. At present, how to reduce the packaging cost of the camera module becomes a key point of attention of various large design, packaging and terminal companies. Among many packaging schemes, CSP packaging costs the lowest. However, CSP packaging also has the problems of high difficulty in manufacturing TSV and cofferdam, high cost, ghost image of wafer level packaging products and the like. In addition, as wafer fabrication progresses toward smaller process nodes, the number of I/os of sensor chips of photoelectric devices increases, and how to increase the rewiring area and the rewiring interconnection density also becomes an urgent problem to be solved in CSP packaging.
The patent applications 201310667563.1 and 201910605108.6 describe cofferdam fabrication and ghost image resolution, respectively, but the packaging scheme is relatively complex. The patent with the application number of 201610528310.X introduces a manufacturing method of a TSV of a photoelectric device package, although the rewiring area of the back surface of a silicon substrate can be increased, the scheme needs to be drilled by processes such as laser ablation, the appearance of the TSV is difficult to control, and the subsequent rewiring difficulty is improved.
Disclosure of Invention
The invention aims to provide a wafer-level packaging method and a wafer-level packaging structure of a photoelectric device, which are used for solving the problem of imaging ghost caused by light leakage of the conventional photoelectric device.
In order to solve the above technical problem, the present invention provides a wafer level packaging method for a photoelectric device, comprising:
providing a glass cover plate, and manufacturing a mask pattern on the surface of the glass cover plate;
plastically packaging the mask pattern, and grinding to a target thickness;
removing the grinding pattern to form a cofferdam, and bonding the chip wafer and the cofferdam through bonding glue;
thinning a chip wafer, etching a groove on the back of the chip wafer, and growing a copper column in the groove;
filling the groove, and grinding until the copper pillar is exposed;
and manufacturing n layers of rewiring, a solder mask layer and salient points, and cutting to form a single packaged chip.
Optionally, the chip wafer is thinned, the back of the chip wafer is etched with a groove, and the copper column growing in the groove comprises:
thinning the back silicon substrate of the chip wafer to a target thickness by a grinding or etching process;
etching a V-shaped groove by using a dry etching process, wherein the groove depth is more than 5 microns, the lower opening of the groove is more than 5 microns, and the groove angle is more than 90 degrees;
and growing a copper column in the groove by using a copper column salient point preparation technology, wherein the diameter of the copper column is more than 1 mu m, and the height of the copper column exceeds the silicon substrate on the back surface of the chip wafer by more than 1 mu m.
Optionally, the thickness of the mask pattern is greater than that of the bank, and the mask pattern is made of a polymer material or a metal material;
the high polymer material comprises resin and polyimide; the metal material includes copper and aluminum.
Optionally, the plastic package mask pattern and the material filling the groove are both plastic package materials, and the plastic package materials are black resin materials, and the light absorption rate of the plastic package materials is greater than 90%.
Optionally, after the plastic package material filling the groove is ground, the plastic package material covers the silicon substrate on the back side of the chip wafer, and the thickness of the plastic package material is greater than 1 μm.
Optionally, the process of removing the abrasive pattern includes affinity dissolution and etching.
Optionally, one surface of the adhesive is connected with the functional layer of the chip wafer, and the other surface of the adhesive is connected with the cofferdam;
the adhesive is black, and the light absorptivity of the adhesive is greater than 90%.
The invention also provides a wafer-level packaging structure of the photoelectric device, which comprises the following components:
the chip wafer comprises a glass cover plate, wherein a cofferdam is manufactured on the glass cover plate and is bonded with a functional layer on the front surface of the chip wafer through bonding glue;
the silicon substrate on the back of the chip wafer is provided with a groove, a copper column is manufactured in the groove and is plastically packaged through a second plastic packaging material, and n layers of rewiring, a solder mask and bumps are sequentially formed on the surface of the second plastic packaging material.
The invention provides a wafer-level packaging method and a structure of a photoelectric device, wherein a glass cover plate is provided, and mask patterns are manufactured on the surface of the glass cover plate; plastically packaging the mask pattern, and grinding to the target thickness of the cofferdam; removing the grinding pattern, and bonding the chip wafer with the cofferdam through bonding glue; thinning a chip wafer, etching a groove on the back of the chip wafer, and growing a copper column in the groove; filling the groove, and grinding until the copper pillar is exposed; and manufacturing n layers of rewiring, a solder mask layer and salient points, and cutting to form a single packaged chip.
The chip wafer is bonded with the glass cover plate through the cofferdam, and the functional layer of the chip is connected with the rewiring layer on the back of the chip through the copper column; the cofferdam is manufactured through primary plastic packaging, the functional layer is interconnected with the back surface of the silicon substrate through secondary plastic packaging, and the rewiring area of the back surface of the silicon substrate is increased. Except one surface of the glass cover plate, other five surfaces of the whole packaging body are wrapped by the plastic packaging material, so that the problem of imaging ghost of the photoelectric device caused by light leakage is solved; the packaging method and the structure are simple, the cost is low, the yield is high, and the packaging method is suitable for large-scale mass production.
Drawings
FIG. 1 is a schematic flow chart of a wafer level packaging method for a photoelectric device according to the present invention;
FIG. 2 is a schematic view of a mask pattern formed on a glass cover plate;
FIG. 3 is a schematic illustration of plastic encapsulation on a glass cover plate with a first molding compound;
FIG. 4 is a schematic view of polishing the first molding compound to a target thickness;
FIG. 5 is a schematic view of a bank formed by removing a mask pattern;
FIG. 6 is a schematic view of bonding a chip wafer on a dam;
FIG. 7 is a schematic view of a silicon substrate with a recess formed on the backside of a chip wafer;
FIG. 8 is a schematic illustration of growing copper pillars in the grooves;
FIG. 9 is a schematic view of the backside of the chip wafer being encapsulated with a second encapsulant;
FIG. 10 is a schematic view of the backside of the wafer with the chip polished until the copper pillars are exposed;
FIG. 11 is a schematic diagram of making n-layer rewires;
FIG. 12 is a schematic view of the formation of a solder mask and bumps;
fig. 13 is a schematic diagram of cutting to form individual packages.
Detailed Description
The wafer level packaging method and structure of the photoelectric device proposed by the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Example one
The invention provides a wafer-level packaging method of a photoelectric device, the flow of which is shown in figure 1, and the method comprises the following steps:
step S11, providing a glass cover plate, and manufacturing a mask pattern on the surface of the glass cover plate;
step S12, plastic-packaging the mask pattern, and grinding to a target thickness;
step S13, removing the grinding pattern to form a cofferdam, and bonding the chip wafer and the cofferdam through bonding glue;
step S14, thinning the chip wafer, etching a groove on the back of the chip wafer, and growing a copper column in the groove;
step S15, filling the groove, and grinding until the copper column is exposed;
and step S16, manufacturing n layers of rewiring, solder mask and salient points, and cutting to form a single packaged chip.
Firstly, providing a glass cover plate 101, and making a mask pattern 102 on the surface of the glass cover plate, as shown in fig. 2; the thickness of the mask pattern 102 is greater than that of the bank 104 to be manufactured, and the material of the mask pattern 102 may be a polymer material such as resin, polyimide, or a metal material such as copper, aluminum;
the mask pattern 102 is plastically packaged by a first plastic package material 103, as shown in fig. 3, the first plastic package material 103 is a black resin material, and the light absorption rate is greater than 90%; then, grinding the first plastic package material 103 to the target thickness of the cofferdam 104 to be manufactured in a grinding way, as shown in fig. 4;
removing the mask pattern 102 by processes such as similar dissolution or etching, and forming a bank 104, as shown in fig. 5;
bonding a functional layer 106 of a chip wafer 105 with the cofferdam 104 through an adhesive 107, wherein one surface of the adhesive 107 is connected with the functional layer 106, and the other surface of the adhesive 107 is connected with the cofferdam 104; as shown in fig. 6; wherein the bonding layer 107 is black, and has a light absorption rate of more than 90%;
the back silicon substrate of the chip wafer 105 is thinned to a target thickness by grinding or etching process, and a V-shaped groove 109 is etched by using a dry etching method, wherein the groove depth of the V-shaped groove is greater than 5 μm, the lower opening of the groove is greater than 5 μm, and the groove angle is greater than 90 degrees, as shown in fig. 7;
as shown in fig. 8, a copper pillar 110 is grown in the V-shaped groove 109 by a copper pillar bump preparation technique, the copper pillar 110 is connected to the functional layer 106, the height of the copper pillar 110 is more than 1 μm higher than the silicon substrate on the back surface of the chip wafer 105, and the diameter of the copper pillar 110 is greater than 1 μm;
filling the V-shaped groove 109 with a second molding compound 111 and completely covering the copper pillar 110, as shown in fig. 9; the second molding compound 111 is a black resin material like the first molding compound 103, and has a light absorption rate of more than 90%; then, the second molding compound 111 is ground to expose the copper pillar 110, and the thickness of the ground second molding compound 111 is more than 1 μm, so that the silicon-based back surface is completely covered by the second molding compound 111, as shown in fig. 10;
as shown in fig. 11, n layers of rewiring 112 are manufactured through photolithography and electroplating processes, so that the functional layer 106 and the back silicon-based interconnection are realized;
finally, as shown in fig. 12, the solder mask layer 113 and the bump 114 are formed, and then cut to form a single packaged chip as shown in fig. 13.
The wafer-level packaging structure of the photoelectric device prepared by the method is shown in fig. 12 and comprises a glass cover plate 101, wherein a cofferdam 104 is manufactured on the glass cover plate 101, and the cofferdam 104 is bonded with a functional layer 106 on the front surface of a chip wafer 105 through an adhesive 107; a groove 109 is formed in a silicon substrate on the back surface of the chip wafer 105, a copper column 110 is manufactured in the groove 109 and is plastically packaged by a second plastic packaging material 111, and n layers of rewiring 112, a solder resist layer 113 and bumps 114 are sequentially formed on the surface of the second plastic packaging material 111. The single packaged chip shown in fig. 13 is obtained by cutting the package structure as shown in fig. 12.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (8)
1. A wafer-level packaging method for photoelectric devices is characterized by comprising the following steps:
providing a glass cover plate, and manufacturing a mask pattern on the surface of the glass cover plate;
plastically packaging the mask pattern, and grinding to a target thickness;
removing the grinding pattern to form a cofferdam, and bonding the chip wafer and the cofferdam through bonding glue;
thinning a chip wafer, etching a groove on the back of the chip wafer, and growing a copper column in the groove;
filling the groove, and grinding until the copper pillar is exposed;
and manufacturing n layers of rewiring, a solder mask layer and salient points, and cutting to form a single packaged chip.
2. The wafer-level packaging method of optoelectronic devices according to claim 1, wherein the chip wafer is thinned, a groove is etched in the back surface of the chip wafer, and the growing of the copper pillar in the groove comprises:
thinning the back silicon substrate of the chip wafer to a target thickness by a grinding or etching process;
etching a V-shaped groove by using a dry etching process, wherein the groove depth is more than 5 microns, the lower opening of the groove is more than 5 microns, and the groove angle is more than 90 degrees;
and growing a copper column in the groove by using a copper column salient point preparation technology, wherein the diameter of the copper column is more than 1 mu m, and the height of the copper column exceeds the silicon substrate on the back surface of the chip wafer by more than 1 mu m.
3. The wafer-level packaging method for the photoelectric device according to claim 1, wherein the thickness of the mask pattern is greater than that of the dam, and the material of the mask pattern is a polymer material or a metal material;
the high polymer material comprises resin and polyimide; the metal material includes copper and aluminum.
4. The wafer-level packaging method for optoelectronic devices according to claim 1, wherein the plastic mask pattern and the material filling the grooves are both plastic packaging materials, and the plastic packaging materials are black resin materials with light absorptivity greater than 90%.
5. The wafer-level packaging method for photoelectric devices as claimed in claim 4, wherein after grinding the molding compound filling the grooves, the molding compound covers the silicon base on the back surface of the chip wafer and has a thickness greater than 1 μm.
6. The wafer-level packaging method for optoelectronic devices according to claim 1, wherein the process of removing the grinding pattern comprises similar dissolution and etching.
7. The wafer-level packaging method for photoelectric devices according to claim 1, wherein one side of the adhesive is connected to the functional layer of the chip wafer, and the other side is connected to the dam;
the adhesive is black, and the light absorptivity of the adhesive is greater than 90%.
8. A wafer level package structure of a photoelectric device is characterized by comprising:
the chip wafer structure comprises a glass cover plate (101), wherein a cofferdam (104) is manufactured on the glass cover plate (101), and the cofferdam (104) is bonded with a functional layer (106) on the front surface of a chip wafer (105) through adhesive glue (107);
the silicon substrate on the back of the chip wafer (105) is provided with a groove (109), a copper column (110) is manufactured in the groove (109) and is plastically packaged by a second plastic packaging material (111), and n layers of rewiring (112), a solder mask layer (113) and bumps (114) are sequentially formed on the surface of the second plastic packaging material (111).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911297393.6A CN111029411A (en) | 2019-12-17 | 2019-12-17 | Wafer-level packaging method and structure of photoelectric device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911297393.6A CN111029411A (en) | 2019-12-17 | 2019-12-17 | Wafer-level packaging method and structure of photoelectric device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111029411A true CN111029411A (en) | 2020-04-17 |
Family
ID=70209235
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911297393.6A Pending CN111029411A (en) | 2019-12-17 | 2019-12-17 | Wafer-level packaging method and structure of photoelectric device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111029411A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112436073A (en) * | 2020-11-20 | 2021-03-02 | 武汉美格科技股份有限公司 | Solar cell cutting method |
| CN112713162A (en) * | 2020-12-29 | 2021-04-27 | 苏州科阳半导体有限公司 | Manufacturing method of wafer-level packaging structure containing optical sensing chip |
| WO2023208207A1 (en) * | 2022-04-29 | 2023-11-02 | 清华大学 | Multi-mode sensing micro-system integration device based on conductive holes and manufacturing method therefor |
-
2019
- 2019-12-17 CN CN201911297393.6A patent/CN111029411A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112436073A (en) * | 2020-11-20 | 2021-03-02 | 武汉美格科技股份有限公司 | Solar cell cutting method |
| CN112713162A (en) * | 2020-12-29 | 2021-04-27 | 苏州科阳半导体有限公司 | Manufacturing method of wafer-level packaging structure containing optical sensing chip |
| WO2023208207A1 (en) * | 2022-04-29 | 2023-11-02 | 清华大学 | Multi-mode sensing micro-system integration device based on conductive holes and manufacturing method therefor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103021983B (en) | Wafer level chip size package and manufacturing method thereof | |
| CN103000649B (en) | A kind of cmos image sensor encapsulating structure and manufacture method thereof | |
| CN111029411A (en) | Wafer-level packaging method and structure of photoelectric device | |
| CN102157492B (en) | Chip package | |
| US8319347B2 (en) | Electronic device package and fabrication method thereof | |
| JP2018523315A (en) | Fan-out type package structure embedded in silicon substrate and manufacturing method thereof | |
| CN103000648B (en) | Large chip sized package and manufacture method thereof | |
| WO2017124670A1 (en) | Packaging method and packaging structure for fan-out chip | |
| CN104392958A (en) | Semiconductor packaging method of wafer level silicon-based through hole | |
| CN111463137B (en) | Silicon-based three-dimensional fan-out integrated packaging method and structure thereof | |
| CN111354652B (en) | High-reliability image sensor wafer-level fan-out packaging structure and method | |
| CN103213936B (en) | Prepare the method for wafer-level MEMS inertia device TSV stack package structure | |
| CN110911291A (en) | Resin type wafer level fan-out integrated packaging method and structure | |
| US20130075892A1 (en) | Method for Three Dimensional Integrated Circuit Fabrication | |
| CN113990966A (en) | Chip packaging structure and packaging method | |
| CN105070732A (en) | High-pixel image sensor packaging structure and manufacturing method thereof | |
| CN210223949U (en) | Three-dimensional system-level integrated silicon-based fan-out type packaging structure | |
| CN210805781U (en) | Wafer-level packaging structure of photoelectric device | |
| TW201903985A (en) | Package structure and manufacturing method thereof | |
| CN109037082B (en) | Package structure and method for forming the same | |
| CN110491792A (en) | A kind of resin type three-dimensional is fanned out to integrated encapsulation method and structure | |
| CN212434614U (en) | Silicon-based three-dimensional fan-out integrated packaging structure | |
| CN210805739U (en) | Resin type wafer level fan-out integrated packaging structure | |
| CN210296360U (en) | Silicon-based fan-out type three-dimensional integrated packaging structure with embedded TSV (through silicon via) adapter chip | |
| CN209822644U (en) | Wafer-level packaging structure of image sensor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |