CN112713162A - Manufacturing method of wafer-level packaging structure containing optical sensing chip - Google Patents
Manufacturing method of wafer-level packaging structure containing optical sensing chip Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 45
- 230000003287 optical effect Effects 0.000 title claims abstract description 33
- 238000004806 packaging method and process Methods 0.000 title abstract description 8
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 91
- 239000010703 silicon Substances 0.000 claims abstract description 91
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 87
- 229910052751 metal Inorganic materials 0.000 claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 24
- 229910000679 solder Inorganic materials 0.000 claims abstract description 24
- 239000011521 glass Substances 0.000 claims abstract description 19
- 238000003825 pressing Methods 0.000 claims abstract description 19
- 238000003466 welding Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000002161 passivation Methods 0.000 claims abstract description 7
- 238000005553 drilling Methods 0.000 claims abstract description 6
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 65
- 239000010410 layer Substances 0.000 claims description 39
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 19
- 229920002120 photoresistant polymer Polymers 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 17
- 239000010936 titanium Substances 0.000 claims description 16
- 229910052719 titanium Inorganic materials 0.000 claims description 16
- 238000001312 dry etching Methods 0.000 claims description 13
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 12
- 229910052802 copper Inorganic materials 0.000 claims description 12
- 239000010949 copper Substances 0.000 claims description 12
- 238000001259 photo etching Methods 0.000 claims description 12
- 238000000227 grinding Methods 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 8
- 229910052731 fluorine Inorganic materials 0.000 claims description 7
- 239000011737 fluorine Substances 0.000 claims description 7
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- 238000005240 physical vapour deposition Methods 0.000 claims description 5
- 238000005516 engineering process Methods 0.000 claims description 4
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- 238000000206 photolithography Methods 0.000 claims description 4
- 238000007747 plating Methods 0.000 claims description 4
- 238000010146 3D printing Methods 0.000 claims description 3
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 3
- 239000000853 adhesive Substances 0.000 claims description 3
- 230000002708 enhancing effect Effects 0.000 claims description 3
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- 238000001039 wet etching Methods 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract description 4
- 238000005476 soldering Methods 0.000 abstract description 3
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 12
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- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
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- 238000003754 machining Methods 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14685—Process for coatings or optical elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1462—Coatings
- H01L27/14623—Optical shielding
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
The invention discloses a manufacturing method of a wafer-level packaging structure containing an optical sensing chip, which comprises the following steps: manufacturing a cofferdam on the surface of the glass; pressing a wafer and glass with cofferdams, wherein the wafer is provided with a signal welding pad and a photosensitive area; thinning silicon of the wafer; manufacturing a groove above the thinned silicon substrate; manufacturing a shading layer on the silicon surface; manufacturing a silicon through hole above the groove; passivating the silicon surface to form a passivation layer; performing laser drilling, puncturing the signal welding pad, and forming a laser hole on the signal welding pad; depositing seed layers on the surface of the wafer and the inner wall of the silicon through hole, and arranging a metal circuit; and arranging a solder mask layer and solder balls on the surface of the wafer. The invention has the beneficial effects that: the shading layer is directly arranged on the silicon surface of the wafer instead of the top layer, so that the problem that the soldering tin salient points (solder balls) have no shading structure can be solved, and the marking can be carried out by using a conventional laser coding mode.
Description
Technical Field
The invention relates to the field of optical sensing, in particular to a manufacturing method of a wafer-level packaging structure comprising an optical sensing chip.
Background
The optical sensor chip plays an important role in capturing images, and the optical sensor chip is widely used in electronic products such as digital cameras (digital cameras), digital video cameras (digital video recorders), mobile phones (mobile phones), solar cells, screens, lighting devices, and the like.
With the development of technology, the demand for the sensing accuracy of the optical sensor chip is also increasing. The conventional wafer level package structure including the optical sensor chip has the following problems:
the solder bumps (solder balls) are not provided with shading structures, so that the solder bumps (solder balls) are still transparent in a special application scene, and shadows projected by the solder bumps (solder balls) appear during chip imaging; moreover, the light shielding layer is at the top, and if the code marking is performed by using a laser method, the light shielding layer is damaged, so that light leakage is caused.
Disclosure of Invention
The invention aims to solve the technical problem of providing a manufacturing method of a wafer level packaging structure containing an optical sensing chip, aiming at the special application scenes of a photosensitive chip, and avoiding the imaging interference problem caused by structures such as metal wiring, soldering tin salient points (solder balls) and the like manufactured by packaging the back of the chip.
In order to solve the above technical problem, the present invention provides a method for manufacturing a wafer level package structure including an optical sensor chip, including: manufacturing a cofferdam on the surface of the glass; pressing a wafer and glass with cofferdams, wherein the wafer is provided with a signal welding pad and a photosensitive area; thinning silicon of the wafer; manufacturing a groove above the thinned silicon substrate; manufacturing a shading layer on the silicon surface; manufacturing a silicon through hole above the groove; passivating the silicon surface to form a passivation layer; performing laser drilling, puncturing the signal welding pad, and forming a laser hole on the signal welding pad; depositing seed layers on the surface of the wafer and the inner wall of the silicon through hole, and arranging a metal circuit; and arranging a solder mask layer and solder balls on the surface of the wafer.
The invention has the beneficial effects that:
the shading layer is directly arranged on the silicon surface of the wafer instead of the top layer, so that the problem that the soldering tin salient points (solder balls) have no shading structure can be solved, and the marking can be carried out by using a conventional laser coding mode.
In one embodiment, the thickness of the glass is in the range of 100-1100 um; the cofferdams are arranged in an annular mode, and the cofferdams are single-ring or multi-ring; the cofferdam is manufactured by the photoetching technology of organic photosensitive materials or 3D printing or screen printing; the cofferdam material is self-adhesive.
In one embodiment, in the "pressing the wafer and the glass with the cofferdam", the pressing is performed by using bonding glue according to the characteristics of the cofferdam material, and a special wafer-level pressing machine equipment is used, and the wafer-level pressing machine equipment performs the whole pressing on the wafer by means of equipment parameters such as temperature, vacuum, pressure and the like.
In one embodiment, in the "silicon with thinned wafer", a diamond-impregnated wheel is used for mechanical grinding process processing, or mechanical chemical grinding and polishing, or plasma dry etching, or wet etching with a fluorine-containing chemical solution, or mechanical grinding with a diamond-impregnated wheel, and then plasma dry etching is used; the thickness of the thinned silicon of the wafer is within a range of 50-200 um.
In one embodiment, in the step of manufacturing a groove above the thinned silicon substrate, the excess silicon is etched by adopting a photoetching process and a dry etching process to etch the groove; covering a silicon surface with a photoetching material with photosensitive characteristic, then applying a mask plate with a special pattern to carry out photosensitive treatment under light with a specific wavelength, and then developing with a chemical agent to manufacture a photoresist pattern; the part uncovered by the photoresist is etched and reacted by active fluorine ions to be removed, thereby achieving the purpose of removing the silicon; after the silicon etching is finished, the photoresist on the surface of the protective layer is removed, and then the silicon surface is cleaned.
In one embodiment, "a light shielding layer is made on a silicon surface", the light shielding layer is a metal or an organic material; the process for manufacturing the shading layer adopts physical vapor deposition to sputter required metal to a silicon surface, firstly titanium plating and then copper plating are carried out, the titanium plays a role in enhancing the binding force with silicon, the titanium is plated on the silicon surface firstly, the thickness of the copper is 2-20 microns, and the thickness of the titanium is 0.1-1 micron.
In one embodiment, in the step of manufacturing the silicon through hole above the groove, redundant silicon is etched by adopting a photoetching process and a dry etching process, and a guide hole is etched; covering a silicon surface with a photoetching material with photosensitive characteristic, then applying a mask plate with a special pattern to carry out photosensitive treatment under light with a specific wavelength, and then developing with a chemical agent to manufacture a photoresist pattern; the part uncovered by the photoresist is etched and reacted by active fluorine ions to be removed, thereby achieving the purpose of removing the silicon; after the silicon etching is finished, the photoresist on the surface of the protective layer is removed, and then the silicon surface is cleaned.
In one embodiment, the seed layer metal is a titanium/copper structure; the thickness of titanium is 0.1-1 um, and the thickness of copper is 0.5-3 um.
In one embodiment, the method further comprises wafer dicing, namely dicing the wafer into single chips after wafer level packaging.
In one embodiment, the wafer dicing is performed using a metal blade or a laser dicing technique.
Drawings
FIG. 1 is a schematic view of a dam for fabricating a wafer level package structure including an optical sensor chip according to a method of the present invention
FIG. 2 is a schematic diagram illustrating the bonding of the wafer and the glass dam in the method for fabricating a wafer level package structure including an optical sensor chip according to the present invention.
FIG. 3 is a schematic diagram of thinning a silicon surface in the method for manufacturing a wafer level package structure including an optical sensor chip according to the present invention.
FIG. 4 is a schematic diagram of forming a trench in the method for fabricating a wafer level package structure including an optical sensor chip according to the present invention.
FIG. 5 is a schematic diagram of a light-shielding layer in a method for fabricating a wafer-level package structure including an optical sensor chip according to the present invention.
FIG. 6 is a schematic diagram of through-silicon-via fabrication in the method for fabricating a wafer-level package structure including an optical sensor chip according to the present invention.
FIG. 7 is a schematic diagram of passivation in the method for fabricating a wafer level package structure including an optically sensitive chip according to the present invention.
FIG. 8 is a schematic diagram of laser drilling in the method for fabricating a wafer level package structure including an optical sensor chip according to the present invention.
FIG. 9 is a schematic diagram of PVD in a method of fabricating a wafer level package structure including optically sensitive chips according to the invention.
FIG. 10 is a schematic diagram of a metal circuit for manufacturing a wafer level package structure including an optical sensor chip according to the method of the present invention.
Fig. 11 is a schematic diagram of manufacturing a solder mask layer in the method for manufacturing a wafer level package structure including an optical sensor chip according to the present invention.
FIG. 12 is a schematic diagram of a method for manufacturing solder balls in the method for manufacturing a wafer level package structure including an optical sensor chip according to the present invention.
FIG. 13 is a schematic diagram illustrating wafer dicing in the method for manufacturing a wafer level package structure including an optical sensor chip according to the present invention.
Detailed Description
The present invention is further described below in conjunction with the following figures and specific examples so that those skilled in the art may better understand the present invention and practice it, but the examples are not intended to limit the present invention.
Referring to fig. 1 to 13, a method for fabricating a wafer level package structure including an optical sensor chip includes: manufacturing a cofferdam 102 on the surface of the glass 101; pressing a wafer 106 and glass with cofferdams, wherein the wafer is provided with a signal pad 104 and a photosensitive area 105; thinning silicon of the wafer; manufacturing a groove 107 above the thinned silicon substrate; manufacturing a light shielding layer 201 on the silicon surface; fabricating a through-silicon via 108 over the trench; passivating the silicon surface to form a passivation layer 109; performing laser drilling to break down the signal welding pad and form a laser hole 110 on the signal welding pad; depositing a seed layer 111 on the surface of the wafer and the inner wall of the silicon through hole, and arranging a metal circuit 112; a solder resist layer 113 and solder balls 114 are provided on the surface of the wafer.
The following describes a specific application scenario of the manufacturing method of the wafer level package structure including the optical sensor chip of the present invention:
firstly, the method comprises the following steps: processing the cofferdam:
referring to FIG. 1, a bank 102 is formed on a surface of a glass 101, and the thickness of the glass is generally in the range of 100 to 1100 μm. The glass dam serves to protect the photosensitive region 105 from external contamination, and is a supporting connection between the glass and the wafer 106 where the optical sensor chips are located. The cofferdams are annularly arranged on the single optical induction chip and can have different annular shapes. Can be a single circle or a plurality of circles. The cofferdam can be manufactured by the photoetching technology of organic photosensitive materials, or the methods of 3D printing, screen printing and the like. Preferably, the dam material is self-adhesive and has good thermal and chemical stability.
II, secondly: and (3) pressing the wafer and the glass cofferdam:
referring to fig. 2, the glass with dam is attached to the wafer 106 of optical sensor chips. Because the material of the cofferdam is sticky, each optical sensing chip is stuck by the cofferdam. According to the characteristics of the dam material, bonding glue 103 is used for pressing in order to obtain better bonding strength. If necessary, a special wafer-level pressing machine equipment can be used, and the wafer-level pressing machine equipment performs whole-piece pressing on the wafer-level pressing machine equipment by means of equipment parameters such as temperature, vacuum and pressure.
Thirdly, the method comprises the following steps: thinning of silicon surface
Referring to fig. 3, the silicon 106 of the wafer is thinned. In order to realize ultra-thin packaged chips, the silicon substrate needs to be thinned. The diamond grinding wheel can be used for mechanical grinding processing, or mechanical chemical grinding and polishing, or plasma dry etching, or wet etching by using fluorine-containing chemical liquid. The thickness of the silicon of the thinned wafer is generally within the range of 50-200 um, and the thickness can be adjusted at will according to specific application requirements. Preferably, the method comprises mechanically grinding with a diamond-impregnated wheel and then dry etching with plasma. The method has the advantages that the mechanical grinding processing is fast, but stress and micro-damage layers are generated on the silicon surface, and then the micro-damage layers are removed by using a plasma dry etching method, so that the surface stress is released, and the problem of wafer warping is solved. After thinning as shown in fig. 3.
Fourthly, the method comprises the following steps: etching bath
Referring to fig. 4, a trench is etched. A trench 107 is formed above the thinned silicon substrate 102. The most mature method is to etch away the excess silicon by using photolithography and dry etching processes to form the trench. Covering a silicon surface with a photoetching material with photosensitive characteristic, then applying a mask plate with a special pattern to carry out photosensitive treatment under light with specific wavelength, and then developing by using a chemical agent to manufacture a photoresist pattern. The part uncovered by the photoresist is etched and removed by active fluorine ion, thereby achieving the purpose of removing the silicon. A wet etch process may also be used instead of a dry etch process. After the silicon etching is finished, the photoresist on the surface of the protective layer is removed, and then the silicon surface is cleaned.
Fifthly: manufacture of light-shielding layer
Referring to fig. 5, a layer of metal 201 is fabricated on the silicon surface. The metal is mainly used for eliminating defects such as poor imaging (shadow of solder bumps) and ghost images of the photosensitive chip. In order to meet the light shielding requirement, the light shielding layer is on the silicon surface, and the area of the light shielding layer covers the whole back surface of the chip as much as possible.
A shading layer is manufactured on the silicon surface, and the shading layer is mainly used for eliminating defects such as poor imaging and ghost of the photosensitive chip. The material may be metal (titanium/copper/nickel/chromium) or organic material. The process for manufacturing the shading layer can be that the needed metal is sputtered to the silicon surface through physical vapor deposition, titanium is firstly plated and then copper is plated in order to enhance the bonding force, the titanium is firstly plated on the silicon surface through enhancing the bonding force with the silicon, the thickness of the copper is generally 2-20 microns, and the thickness of the titanium is 0.1-1 micron. Specifically, the method can be realized by a single process or a combination of processes such as spin coating, spraying, semiconductor photoetching and semiconductor etching.
Sixthly, the method comprises the following steps: through silicon via
Referring to fig. 6, the through silicon via 108 is etched. A through-silicon via 108 is made over the trench 107. The most mature method is to etch away the excess silicon by using a photolithography process and a dry etching process to etch out the through-silicon via. Covering a silicon surface with a photoetching material with photosensitive characteristic, then applying a mask plate with a special pattern to carry out photosensitive treatment under light with specific wavelength, and then developing by using a chemical agent to manufacture a photoresist pattern. The part uncovered by the photoresist is etched and removed by active fluorine ion, thereby achieving the purpose of removing the silicon. A wet etch process may also be used instead of a dry etch process. After the silicon etching is finished, the photoresist on the surface of the protective layer is removed, and then the silicon surface is cleaned. The structure is shown as figure six;
seventhly, the method comprises the following steps: passivation of
Referring to fig. 7, since silicon is a semiconductor, passivation may function as insulation. The structure is shown in figure seven.
Eighthly: laser drilling
Referring to fig. 8, the back lead is padded by breaking through the signal pad.
Nine: physical vapor deposition
Referring to fig. 9, a thin seed layer 111 is deposited on the back surface of the wafer and the inner wall of the through silicon via by magnetron sputtering. The seed layer achieves two purposes, namely, the bonding force between metal and a substrate is enhanced, and the seed layer is prepared for electroplating and depositing metal circuits. Common seed layer metals are titanium/copper, chromium/copper, and the like. Preferably an environmentally friendly and low cost titanium/copper structure. The thickness of titanium is 0.1-1 um, and the thickness of copper is 0.5-3 um, generally according to the degree of depth and the angle of through-silicon-via and adjust.
Ten: metal circuit
Referring to fig. 10, the metal lines may be disposed by a conventional method, which is not described herein.
Eleven: solder mask
Referring to fig. 11, the purpose of providing the solder mask is to protect the circuit, and the solder mask may be provided by using an existing method, which is not described herein again.
Twelve: tin ball
Referring to fig. 12, the solder balls may be disposed by a conventional method, which is not described herein again.
Thirteen: cutting of
Referring to fig. 13, the wafer is diced, and the wafer after wafer level packaging is diced into individual chips 115; the machining may be performed using a metal blade or a laser cutting technique.
The above-mentioned embodiments are merely preferred embodiments for fully illustrating the present invention, and the scope of the present invention is not limited thereto. The equivalent substitution or change made by the technical personnel in the technical field on the basis of the invention is all within the protection scope of the invention. The protection scope of the invention is subject to the claims.
Claims (10)
1. A method for manufacturing a wafer level package structure including an optical sensor chip, comprising: manufacturing a cofferdam on the surface of the glass; pressing a wafer and glass with cofferdams, wherein the wafer is provided with a signal welding pad and a photosensitive area; thinning silicon of the wafer; manufacturing a groove above the thinned silicon substrate; manufacturing a shading layer on the silicon surface; manufacturing a silicon through hole above the groove; passivating the silicon surface to form a passivation layer; performing laser drilling, puncturing the signal welding pad, and forming a laser hole on the signal welding pad; depositing seed layers on the surface of the wafer and the inner wall of the silicon through hole, and arranging a metal circuit; and arranging a solder mask layer and solder balls on the surface of the wafer.
2. The method of claim 1, wherein the glass has a thickness of 100-1100 um; the cofferdams are arranged in an annular mode, and the cofferdams are single-ring or multi-ring; the cofferdam is manufactured by the photoetching technology of organic photosensitive materials or 3D printing or screen printing; the cofferdam material is self-adhesive.
3. The method as claimed in claim 1, wherein the step of pressing the wafer and the glass with the dam is performed by using a bonding glue according to the characteristics of the dam material, and a dedicated wafer-level pressing machine is used, and the wafer-level pressing machine performs the whole pressing process by using the parameters of temperature, vacuum, pressure, etc.
4. The method for manufacturing a wafer-level package structure containing an optical sensor chip according to claim 1, wherein in the "thinned silicon" wafer, a diamond-impregnated wheel is used for mechanical grinding processing, or mechanical chemical grinding polishing, or plasma dry etching, or wet etching with a fluorine-containing chemical solution, or plasma dry etching is used after mechanical grinding with the diamond-impregnated wheel; the thickness of the thinned silicon of the wafer is within a range of 50-200 um.
5. The method for fabricating a wafer-level package structure including an optical sensor chip according to claim 1, wherein in the step of fabricating a trench above the thinned silicon substrate, the trench is etched by using a photolithography process and a dry etching process to remove excess silicon; covering a silicon surface with a photoetching material with photosensitive characteristic, then applying a mask plate with a special pattern to carry out photosensitive treatment under light with a specific wavelength, and then developing with a chemical agent to manufacture a photoresist pattern; the part uncovered by the photoresist is etched and reacted by active fluorine ions to be removed, thereby achieving the purpose of removing the silicon; after the silicon etching is finished, the photoresist on the surface of the protective layer is removed, and then the silicon surface is cleaned.
6. The method as claimed in claim 1, wherein the step of forming the light-shielding layer on the silicon surface is a step of forming a metal or organic light-shielding layer; the process for manufacturing the shading layer adopts physical vapor deposition to sputter required metal to a silicon surface, firstly titanium plating and then copper plating are carried out, the titanium plays a role in enhancing the binding force with silicon, the titanium is plated on the silicon surface firstly, the thickness of the copper is 2-20 microns, and the thickness of the titanium is 0.1-1 micron.
7. The method for fabricating a wafer-level package structure including an optical sensor chip according to claim 1, wherein in the step of fabricating a through-silicon via above the trench, the excess silicon is etched away by using a photolithography process and a dry etching process to form a via hole; covering a silicon surface with a photoetching material with photosensitive characteristic, then applying a mask plate with a special pattern to carry out photosensitive treatment under light with a specific wavelength, and then developing with a chemical agent to manufacture a photoresist pattern; the part uncovered by the photoresist is etched and reacted by active fluorine ions to be removed, thereby achieving the purpose of removing the silicon; after the silicon etching is finished, the photoresist on the surface of the protective layer is removed, and then the silicon surface is cleaned.
8. The method of claim 1, wherein the seed layer metal is a titanium/copper structure; the thickness of titanium is 0.1-1 um, and the thickness of copper is 0.5-3 um.
9. The method as claimed in claim 1, further comprising dicing the wafer into individual chips.
10. The method of claim 9, wherein the wafer level package structure with the optical sensor chip is processed by a metal blade or a laser dicing technique.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023109087A1 (en) * | 2021-12-14 | 2023-06-22 | 上海集成电路装备材料产业创新中心有限公司 | Chip package structure and chip package method |
| CN116598326A (en) * | 2023-06-05 | 2023-08-15 | 华天科技（昆山）电子有限公司 | Wafer level packaging method and packaging structure for improving image problem |
| CN117936636A (en) * | 2023-12-29 | 2024-04-26 | 成都阜时科技有限公司 | Light sensing chip, preparation method thereof, laser radar and electronic equipment |
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